KR100382467B1 - Serial interface system - Google Patents

Abstract

PURPOSE: A serial interface system is provided to reduce cost by recovering a clock without a PLL(Phase Locked Loop) as branching/using the clock inputted from the system as a system clock, and simplify hardware by using no channel coding technique such as the NRZ(Non Return to Zero) and the NRZI(Non Return to Zero Inverse). CONSTITUTION: A latch(21) latches a data/frame synchronization signal inputted from the first system. A clock generator(23) generates the clock needed to the serial interface system by receiving clock information from the first system. A FIFO(First Input First Output) controller(24) controls read/write of a FIFO(22). A parallel/serial converter(25) converts output data of the FIFO into serial data according to the clock generated from the clock generator. An AC coupling filter(26) limits a band by filtering the output of the parallel/serial converter. A marker inserter(27) inserts marker information for recovering the clock at a receiving terminal into the output of the AD coupling filter and outputs the data.

Description

Serial interface system

The present invention relates to a serial interface system, which enables clock recovery without a PLL in the system, and uses a FIFO capable of read / write clock control to enable stable operation even when a system having any clock is connected. It relates to an interface system.

1 is a block diagram of a general serial interface system, in which input video data and other necessary auxiliary data are processed through a transmitter processing unit 1 and then input to a serial encoder 2.

The parallel data input to the serial encoder 2 is converted into serial data and then transmitted through a coaxial cable 4 via a line driver 3 for sending a stable signal to a receiver.

The signal transmitted through the coaxial cable 4 is input to the serial decoder 5 of the receiving end, and serial data is converted into parallel data. The parallel converted data is processed and output by the receiver processor 6. .

On the other hand, the most important aspect in serial transmission is the clock recovery at the time of reception so that the PLL works well by generating edge information using channel coding technique.

These functions are performed by the serial encoder (2), and currently known channel coding methods include Non Return to Zero (NRZ), Non Return to Zero Inverse (NRZI), Bi-Phase Mark (Manchster Code), and Miller Coding. There is this.

These coding techniques compare the input data with a reference clock to produce edge information that ultimately makes the PLL work well.

FIG. 2 is a view illustrating a clock recovery unit at the receiving end, which corresponds to a PLL with a partial configuration of the serial decoder 5, and input serial data transmitted from the transmitter is input to the edge pulse generator 8 to be delayed. It is used for edge information detection along with the signal input delayed through 7).

The edge information is used as information for driving the PLL, and the phase between the edge information detected by the edge pulse generator 8 and the output of the VCO 10 is compared by the phase detector 9, and then the PLL control signal. Then, the data recovery unit 11 which receives the output signal of the delay 7 and the output signal of the VCO 10 outputs data synchronized with the clock.

However, the conventional serial interface system as described above has a high cost because the PLL has a VCO, and the transmitter includes a scrambler, NRZ to NRZI, a channel equalizer, and the receiver includes an RF PLL, NRZI to NRZ, and a descrambler. Therefore, not only hardware but also peripheral circuits had complex disadvantages.

The present invention has been made to solve this problem, and an object of the present invention is to divide the clock input into the system and use it as the clock of the system so that the clock can be recovered without a separate PLL, thereby reducing the cost, and generating three levels of serial data. The present invention provides a serial interface system that allows a hardware to be configured more simply by adopting a format so that it can be used as clock information at a receiving end and not using channel coding techniques such as NRZ and NRZI.

Another object of the present invention is to provide a serial interface system that enables stable operation even when a system having any clock is connected by using a FIFO that facilitates read / write clock control.

A characteristic of the present invention for achieving this object is to receive clock information from a first system connected externally, generate a clock required for a serial interface system, and latch data and frame synchronization signals inputted from the connected system. A serial interface transmitter for converting into serial data and inserting marker information to be used as clock information at the receiving end and transmitting the serial data; and slicing serial data transmitted from the serial interface transmitter to serial data and a marker. Obtains information and sends clock information and frame synchronization signal necessary for driving the connected second system, receives the clock information necessary for the serial interface system from the connected second system, and generates the required clock for the serial interface system. Accordingly, in the serial interface system configured to convert the input serial data into parallel data and output the parallel data to the connected second system, the serial data transmitted from the serial interface transmitter is configured in three levels, And a FIFO for temporarily storing input data through the latch and a FIFO control unit for controlling read / write of the FIFO.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a serial interface system according to the present invention, in which a latch 21 for latching data and a frame synchronization signal VRST input from a connected system and an output of the latch 21 FIFO 22 which is temporarily stored, clock generators 2 and 3 which receive clock information from a connected system and generate clocks necessary for a serial interface system, and clocks from the clock generator 23 And a FIFO control unit 24 using the clock and reset information of the FIFO 22 as the read clock and reset information of the FIFO 22, and the FIFO controller 22 using the clock received from the connected system as the reset clock and reset information. A parallel / serial converter 25 for converting the output data of the < RTI ID = 0.0 >) < / RTI > into serial data according to a clock from the clock generator 23, and filtering the output of the parallel / serial converter 25 to limit a band. AC couple Serial interface transmitter 28 comprising a filter 26, a marker inserter 27 for inserting and outputting marker information for clock recovery at the receiving end during the output of the filter 26, and the serial A marker detector 29A for compensating for signal distortion by transmission of serial data transmitted from the transmitter 28 of the interface, a slicer 29B for slicing the output of the marker detector 29A into data and marker information, A synchronization detector 20 which detects a frame synchronization signal VRST and clock information from the serial data and marker information output of the slicer 29B and outputs it to a PLL of a connected system, and the clock information of the synchronization detector 30. And generating clocks required for the serial interface system by receiving clock information from a PLL of a system connected to the serial interface system driven according to the output of the frame synchronization signal VRST. Is a clock generator 31, a serial / parallel converter 32 for converting serial data output of the slicer 29B into parallel data according to the clock generated by the clock generator 31, and the serial / It consists of a latch 32 which latches the output of the parallel converter 32 and outputs it to the connected system.

The filter 26 is composed of a feedback and forward filter composed of adders 26A, 26B, and delays 26C, 26D, as shown in FIG.

Meanwhile, FIG. 5A illustrates a configuration diagram of the marker insertion unit 27. The analog switch 27A-27C for three-level output of + 5V or 0V or -5V, and the analog switch ( And a driving unit 27D for driving the output of 27A-27C without deterioration of the signal.

In addition, Figure 5 (b) shows another configuration diagram of the marker insert 27, D / A limiter (27E-27G) for three-level output of + 5V or 0V or -5V, And a driver 27H for driving the outputs of the D / A converters 27E-27G without deterioration of the signal.

The present invention configured as described above is divided into recording mode and playback mode between HDTV and HDVCR and described with reference to FIGS. 6A and 6B.

1) Record Mode

First, in the recording mode, the serial interface transmitter 28 receives data (8 bits), frame synchronization signal (VRST), 37 MHz clock, and the like from the HDTV receiver.

The 37 MHz clock is input to the clock generator 23 and used as a write clock of the FIFO 22. The read clock of the FIFO 22 is a clock received from the PLL of the HDTV receiver by the clock generator 23. The clock created using the information is used.

Read / write control of the FIFO 22 is performed by the FIFO controller 24 according to the clock generation of the clock generator 23.

In this case, the write clock of the FIFO 22 uses the clock input from the HDTV receiver, and the read clock uses the clock generated by using the clock information received from the PLL of the HDTV receiver in the clock generator 23. The reason is that the serial interface system can operate stably even if any clock information is input from the HDTV receiver.

On the other hand, the data and frame synchronization signal (VRST) input from the HDTV receiver is input to the parallel / serial converter 25 through the FIFO 22 through the latch 21, the parallel / serial converter Numeral 25 converts parallel data into serial data by supplying the clock from the clock generator 23.

At this time, the serial data format converted into serial by the parallel / serial converter 25 has a structure having three levels (Tri-Level) such as -5V, 0, 5V, as shown in FIG. Marker information is 2 bits, B is 2 bits as frame synchronization signal (VRST), C is 8 bits as data, and E is erasure information, which is a signal exchanged between each other when ambiguous signal. One bit, E, is extra and consists of one bit.

Then, the signal converted into the serial data format through the parallel / serial converter 25 as shown in FIG. 8A is shown in FIG. 8B through the filter 26.

That is, the filter 26 outputs two input levels (level 1, level 0) at three levels (level 1, level 0, level-1) as shown in Table 1 below.

『Table 1』

Meanwhile, at the output of the filter 26, level 1 means 5V, level 0 means 0V, and level-1 means -5V.

In more detail, the input / output operation of the filter 26 will be described. First, as shown in FIG. 8A, the level 1 is 5V, the level 0 is 0V, the level 1 is 1, and the level 0 is -1. to be.

And the second level of input through the filter 26

Becomes

That is, 2 (5V) is level 1, 0 (0V) is level 0, and -2 (-5V) is level-1, indicating that two input levels are output at three levels as shown in FIG.

Meanwhile, the output of the filter 26 is input to the marker inserter 27 to insert marker information, and the marker information is loaded with 2 bits having a -5V value as shown in FIG.

The marker inserter 17 outputs + 5V or 0V or -5V to the output of the filter 26 by switching the respective analog switches 27A-27C as shown in FIG. The double -5V (level-1) is inserted into two bits and transmitted in the same manner as in the seventh degree, and the output of the analog switches 27A-27C is output by the driving unit 27D without attenuation of the signal. do.

In addition, the marker insertion unit 27 is + 5V, 0V or -5V by the D / A converter (27E-27G) for output of + 5V, 0V, -5, respectively, as shown in FIG. The marker information is selected and loaded through the driving unit 27H as shown in the seventh diagram. The analog switches 27A-27C and the D / A converters 27E-27G are each formed of one IC in accordance with an external control signal. It is designed to operate, and the high speed device is used due to the cooperative operation with the system.

The output of the constant marker inserter 27 is input to the serial interface receiver 34 via a coaxial cable, and is input to the marker detector 29A that controls the gain according to the voltage.

The marker detector 29A has a built-in AGC to compensate for the distorted signal and transmits the clean signal to the slicer 29B so that the slicer 29B can slice well.

Accordingly, the slicer 29B slices the input serial data into data and marker portions, and slicing the data at 2.5V because the data has an amplitude of 0- + 5V, and the marker information is -5V-. Slicing at -2.5V because it has an amplitude of 0V.

The sliced data, that is, the serial data, is input to the serial / parallel converter 31 to convert to parallel data, and the marker information is input to the synchronization detector 30.

In addition, the serial data information is also input to the synchronization detector 30, and the marker information is also input to the serial / parallel converter 32.

Accordingly, the synchronization detector 30 detects the frame synchronization signal VRST from the serial data received from the slicer 29B, and references the clock synchronization signal 171H based on the marker information to drive the PLL of the HDVCR. As a result, 37MHz clock information is input to the clock generator 32 from the PLL of the HDVCR.

Accordingly, the clock generator 32 generates a clock required for a serial interface using the clock information received from the PLL of the HDVCR and inputs it to the serial / parallel converter 39.

Accordingly, the serial / parallel converter 32 converts the input serial data into parallel data and inputs the same to the HDVCR through the latch 33 to be recorded in the HDVCR.

2) .Playback mode

The playback mode is the reverse of the recording mode. The serial interface transmitter 28 receives data (8 bits), erasures, and frame synchronization signals (VRST) from the HDVCR through the latch 21, wherein the erasure Indicates an ambiguous state of the sliced data in the HDVCR.

The output of the latch 21 is input to the FIFO 22, and the clock and reset of the FIFO 22 are used by the clock received from the HDVCR, and the lead clock and the reset are made by the clock generator 23. A clock is used, and the control of the FIFO 22 is performed by the FIFO control unit 24.

The data output from the FIFO 22 is input to the parallel / serial converter 25 to be converted into serial data according to the control of the FIFO controller 24. At this time, the parallel / serial converter 25 is used for the clock. It is operated by the clock generated by the generator 21.

The output of the parallel / serial converter 25 is input to the marker inserter 27 through the filter 26 in the same manner as in the recording mode to insert the marker information. Is sent to 34.

The signal transmitted from the serial interface transmitter 28 is input to the marker detector 29A in the serial interface receiver 34 on the HDTV receiver side, and the distorted signal is compensated for during transmission, and then input to the slicer 29B. Data and marker information are obtained.

The serial data and marker information obtained through the slicer 29B are input to the synchronization detector 30, and the synchronization detector 30 detects a frame synchronization signal VRST from the serial data and clocks from the marker information. The information 17H is obtained, and 171H and frame synchronization signal VRST are sent to the PLL in the HDTV receiver. As a result, the clock generator 31 receives 37MHz clock information from the PLL of the HDTV receiver.

Accordingly, the clock generator 31 generates a clock necessary for the serial interface receiver 34 and inputs it to the serial / parallel converter 32 and the latch 33. Accordingly, the serial / parallel converter 32 is a slicer. Serial data inputted from ((29B)) is converted into parallel data so as to be inputted to the HDTV receiver through the latch 33 and reproduced.

Meanwhile, the present invention can be used not only between HDTV and HDVCR but also between serial interfaces as shown in FIG. 9, and can be used for signal transmission in all digital systems.

In addition, the serial interface system according to the present invention operates well at a distance of 200 feet when a 75 ohm coaxial cable is used when using an HDTV and an HDVCR or a D3VTR.

As described above, the present invention does not need to use a PLL as in the related art, and thus, costs are reduced, and since a FIFO capable of controlling read / write is used, stable operation is possible even when connected to a system having any clock.

In addition, by using a serial data format having three levels to obtain clock information from the receiving system, hardware is simplified by not using channel coding techniques such as NRZ or NRZI as in the prior art.

1 is a block diagram of a conventional serial interface system

2 is a block diagram of the clock recovery unit of FIG.

3 is a block diagram of a serial interface system according to the present invention

4 is a detailed configuration diagram of the filter of FIG.

5 (a) and (b) are detailed block diagrams of the marker insert of FIG.

6A is an example of applying the present invention to a recording mode between HDTV and HDVCR.

(B) is an example of applying the present invention to the playback mode between HDTV and HDVCR

7 illustrates a serial data format according to the present invention.

8 (a) and (b) show the input and output waveforms of the filter of FIG.

9 is an explanatory diagram of an application of the present invention.

* Description of the symbols for the main parts of the drawings *

21,23: Latch 22: FIFO

23,31: clock generator 24: FIFO controller

25: parallel / serial converter 26: filter

27: marker insert 28: serial interface transmitter

29A: marker detection unit 29B: slicer

30: Sync detector 32: Serial / parallel converter

34 serial interface receiver

Claims (8)

A serial interface transmitter for transmitting serial data inserted with clock and marker information necessary for a serial interlace system to a connected first system, and converting the serial data into parallel data using a clock transmitted from the serial interface transmitter. In the serial interface system comprising a serial interface receiver for output to the second system, the serial interface transmitter A latch for latching data and a frame synchronization signal VRST input from the first system; A FIFO for temporarily storing input data through the latch, A clock generator for receiving clock information from the first system and generating a clock necessary for the serial interface system; A FIFO controller for controlling read / write of the FIFO; A parallel / serial converter for converting output data of the FIFO into serial data according to a clock from the clock generator; An AC coupling filter for limiting a band by filtering an output of the parallel / serial converter; And a marker insertion unit for inserting and outputting marker information for clock recovery at a receiving end during output of the filter. The method of claim 1, The serial data converted by the parallel / serial converter comprises three levels (+ 1,0, -1), and the marker information is inserted into two bits at -1 of the three levels. . The method of claim 1, And the clock generated by the clock generator is used as the read clock and the reset of the FIFO, and the clock input from the first system connected to the serial interface transmitter is used as the write clock and the reset. The method of claim 1, wherein the marker insertion portion An analog switch for outputting any one of three levels of + 5V, 0V or -5V, And a driver for driving the output of the analog switch without deterioration of the signal. The method of claim 1, wherein the marker insertion portion A D / A converter for outputting any one of three levels of + 5V, 0V or -5V, And a driver for driving the output of the D / A converter without deterioration of the signal. The method of claim 1, The format of the serial data converted by the parallel / serial converter is 2 bits carrying marker information, 2 bits carrying frame sync signal, 8 bits carrying data, and erasure information. A serial interface system comprising 1 bit and extra 1 bit. The method of claim 1, And the AC coupling filter outputs two levels at three levels as inputs. The method of claim 1, wherein the serial interface receiver A marker detector for compensating for signal distortion caused by transmission of serial data transmitted from the serial interface transmitter; A slicer for slicing the output of the marker detector into data and marker information; A sync detection unit for detecting frame sync signal (VRST) and clock information from the serial data and marker information output of the slicer and outputting the frame sync signal (VRST) and clock information to a PLL of a connected system A clock generator for generating a clock required for the serial interface system driven according to the clock information of the synchronization detector and the output of the frame synchronization signal VRST; A serial / parallel converter configured to convert serial data output of the slicer into parallel data according to a clock generated by the clock generator; And a latch configured to latch an output of the serial / parallel converter to output the connected system.