KR0143098B1 - High speed asynchronous serial communication interface apparatus for information storage system - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A high speed asynchronous serial communication interface device for information storage.

2. The technical problem to be solved by the invention

An asynchronous serial communication interface device for storing the processing result of the communication device main board at high speed in the information storage device is implemented.

3. Summary of Solution to Invention

The interface device of the present invention writes the processing result of the main board in word memory in the transmission memory, generates a transmission start signal, performs reading for transmission, and serially converts and duty converts the data to the interface device of the information storage device. Receives the information output from the information storage device, latches it into a predetermined bit, converts it into serial, writes it into the receiving memory in units of words, and sends the interrupt signal to the CPU board of the communication device when the received information is a predetermined number of received words. The CPU board reads the received information stored in the receiving memory.

Description

High Speed Asynchronous Serial Communication Interface Device for Information Storage

1 is a block diagram for storing the processing result of the main CPU board 12 in the information storage device 20 in the communication device 10 is composed of a plurality of boards operating

2 is a schematic diagram of a communication interface board 14 and 22 according to the present invention.

3A to 3C are diagrams, and FIG. 3A is a waveform diagram of each part according to an initialization operation and a data transmission operation state of the communication interface board 14 according to the present invention, and FIG. 3B is a duty converter 40. And a specific waveform diagram of the transmission / reception data TDXT and RXDT output from the data reception section 44, and FIG. 3C is a waveform diagram of each section according to the data reception operation state of the communication interface board 14. FIG.

* Explanation of symbols for main parts of the drawings

10: communication device 12: CPU board

14, 22: communication interface board 20: information storage device

30: FIFO memory unit for transmission 32: Address decoder

36: Timing control unit 40: Duty conversion unit

42: data transmitter 44: data receiver

46: Receive bit latch unit 50: Receive word detection unit

54: relay drive part 56: relay part

16-1, 16-2: Transmission and reception transmission line

The present invention relates to a communication system, and more particularly to an asynchronous serial communication interface device for storing the processing result of the main board at high speed in the information storage device.

FIG. 1 shows a configuration diagram for storing the processing result of the main CPU board 12 in the information storage device 20 in the communication device 10 which is composed of several boards. In order to store in the information storage device 20, a transmission line 16 for connecting both communication interface boards 14 and 22 and both communication interface boards 14 and 22 is provided. Information storage device 20 of FIG. 1 may be comprised of a general purpose computer and similar equipment. The information storage device 20 stores all the processing results of the main CPU board 12 so as to reduce the information processing burden of the first diagram and the communication device 10.

In the configuration of FIG. 1, the result of processing in the main CPU board 12 is gradually increased for use in maintenance, improvement, and other purposes, and the information electronic device 20 must store as much processing information as it is. The main CPU board 12 for storing such processing information in the information storage device 20 is gradually increasing the communication control burden.

To reduce this burden, the communication interface boards 14 and 22 are equipped with the following standards or options. Among them, interfacing method for transmitting data in parallel such as GP-IB or Centronics interface, and interface method for transmitting data such as RS-23C, RS422, RS423 interface, etc. in serial There is this. In the parallel interface method, since the lines of the transmission line 16 of FIG. 1 are provided in parallel, the resultant information processed by the main CPU board 12 can be processed at a time and at a high speed. However, although the parallel interface method is high speed, when the distance between the communication device 10 and the information storage device 20 is far, the transmission line 16 and the interface boards 14 and 22 for input / output communication are expensive. In addition, the ease of movement of the information storage device 20 is impaired.

Alternatively, the interface method for transmitting data serially has a smaller number of transmission lines 16, easier access, and easier noise countermeasure than the interface method for parallel transmission, but has a lower transmission speed than the parallel method. There is this. In addition, the RS-232C interface specifies the length of the transmission line between the communication device 10 and the information storage device 20 as a standard of 15 meters, and the distance is rather short.

Accordingly, an object of the present invention is to provide an asynchronous serial communication interface device for storing the processing result of the communication device main board at high speed in an information storage device.

Another object of the present invention is to provide an asynchronous serial communication interface device capable of communicating at high speed while efficiently reducing the number of transmission lines connecting a communication device and an information storage device.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Note that the same configuration in the present invention uses the same reference numerals and symbols wherever possible.

2 is a communication interface board 14 and 22 according to the present invention, and the processing result of the main CPU board 12 of the communication device 10 shown in FIG. 1 is stored at high speed in the information storage device 20. It is an asynchronous serial communication interface device.

The serial communication interface device according to the present invention includes a transmission FIFO memory unit 30, an address decoder 32, a clock generator 34, a timing controller 36, a duty converter 40, and a data transmitter 42. And a data receiving interface section including a reception bit latch section 46, a serial / parallel conversion section 48, a reception word detection section 50, and a receiving FIFO memory section 52, a relay driver 54 and a relay section. It consists of a loopback test formation part containing 56.

According to the present invention, the communication transmission line 16 connecting both communication interface boards 14 to each other is composed of four lines. Two wires are used for transmission data TXDT (+) (-) as transmission transmission line 16-1 and the remaining two wires are for transmission data RXDT (+) (-) as transmission transmission line 16-2 for reception. Used. And it can be achieved by the serial interface method implemented in the present invention, such as the RS422 interface.

Hereinafter, the operation of the present invention will be described in more detail based on the above configuration.

First, the operation of the communication interface board 12 according to the present invention when transmitting the processing information of the CPU board 12 to the information storage device 20 will be described.

The CPU board 12 transmits the processing result to the communication interface board 12 using the data bus, address bus and control signals to store the processing result in the communication device 10 in the information storage device 20. do. The address bus ADD carries signals for initialization as shown in FIG. 3A and is applied to the address decode 32, and the control signal has an address enable signal AEN and an interface board for enabling the signals carried on the address bus ADD. An enable signal IORD for enabling input / output read of (12) is applied to the address decoder 32. Referring to FIG. 3A, the address bus ADD sets the reset signal TCLR for initializing the transmission FIFO memory unit 30 to 004, the reset signal for board initialization to 0, and the reception FIFO memory unit 52. The reset signal RCLR for initialization is set to 9, and the transmission start signal START for transmission start is set to 3. Therefore, the address decoder 32 transmits the FIFO memory unit 30 in response to the address enable signal AEN in the initialization operation. The initialization signals TCLR and RCLR are applied to the reception FIFO memory unit 52 and initialized, and the transmission start signal START is output to the timing controller 36. The CPU board 12 initializes the communication interface board 14 and outputs a control signal to the address decoder 32 to write enable the transmission FIFO memory unit 30. Then, the address decode 32 responds in response thereto. The write enable signal TXWE is output to the transmission FIFO memory section 30. The address decoder 32 may be implemented with, for example, an LSI 38 chip.

The transmission FIFO memory unit 30 stores processing information, that is, data DI, of the CPU board 12 via the data bus in response to the write enable signal TXWE output from the address decoder 32. At this time, data DI is transmitted as serial data and stored in word unit. The transmission FIFO memory unit 30 has a capacity of 16 bits x 16 (width), that is, 16 words.

On the other hand, the clock generator 34 provides the timing controller 36 with a clock signal CLK of several tens of megahertz, for example, 16 MHz. The timing controller 36 is composed of predetermined counters, dividers, and latches that operate in response to the clock signal CLK output from the clock generator 34, and is adapted to the transmission start signal START output from the address decoder 32. In response, as shown in FIG. 3A, the read operation pulse TXRD is applied to the transmitting FIFO memory section 30. FIG. The transmission FIFO memory section 30 converts the stored data DI in 16-bit parallel form in response to the read operation pulse TXRD. The conversion 38 outputs 16-bit parallel data output from the transmission FIFO memory section 30. Is converted to serial in response to the synchronization signal SYNC of the timing controller 36, and output to the duty converter 40. The duty converter 40 converts the duty of the serially converted data in response to the duty conversion control signal DUT. To print. Data output from the parallel / serial conversion unit 38 is word streams # 1, # 2, .... # 512 as shown in FIG. 3B, and one word stream has 16 data. It consists of a bit stream consisting of bits and a logic low state where no data is applied. The 16 serial data bits are 16 microseconds and the logic low state is 4 microseconds. Therefore, one word stream is 20 mu sec. The data bits [data 1 or 0] have a duty ratio as shown in FIG. 3B when output from the duty converter 40. FIG.

The synchronization signal SYNC applied from the timing controller 36 to the parallel / serial conversion unit 38 is a signal generated by dividing and latching the clock signal CLK of the clock generation unit 34, and the duty conversion from the timing control unit 36 is performed. The duty conversion control signal DUT applied to the unit 40 is a clock set to comply with the duty conversion ratio of the present invention.

The transmission data TXDT (16 word units) output from the duty converter 40 is applied to the data transmitter 42, and the data transmitter 42 differentially amplifies the data TXDT and transmits the data TXDT (+) and TXDT (−). Is applied to the transmission transmission line 16-1. The data transmission unit 42 is implemented as a differential amplifier circuit, which is suitable for short-range communication and high-speed data transmission and reception. The data transmitter 42 may be implemented with a commercially available AM26LS31 chip or a DS26LS31 chip. The data transmitted through the transmission transmission preference 16-1 is stored in the predetermined information storage area of the information storage device 20 through the communication interface board 22 of the information storage device 20.

Next, when the stored information of the information storage device 20 is received at the interface board 14 of the communication device 10 through the communication interface board 20 and the reception transmission path 16-2, the communication information according to the present invention. The operation of the interface board 12 will be described.

The relay unit 56 of the communication interface board 12 always connects the receiving transmission line 16-2 and the data receiving unit 44 when performing a data transmission / reception operation. Accordingly, the differential amplified reception data RXDT (+) and RXDT (-) applied through the reception transmission path 16-2 are received by the data receiver 44 through the relay unit 56 and the data receiver 44 receives the data. The data RXDT (+) and RXDT (-) are detected by the reception data RXDT of the bit string as shown in 3C, and output to the reception bit latch unit 46. The data receiver 44 may be implemented with an AM26LS32 chip.

Figure 3C shows the data DI transmitted in units of 16 words and, for example, holds data D15 of word # 15. An example of transmission data D15 is in the form of a bit string of transmission and reception data TXDT and RXDT shown in FIG. 3C when it is output from the duty converter 40 and when it is received by the data receiver 44. The bit string corresponding to the data D15 shows that the data value is 7800R (H: 16 digits) per day.

The reception bit latch section 46 latches the reception data RXDT as shown in the example of FIG. 3C output from the data reception section 44, and then outputs them to the serial / parallel conversion section 48 and the reception word detection section 50, respectively. do. The serial / parallel conversion unit 48 converts the serial data into 16-bit parallel data, that is, a bit string in word units, and outputs the serial data to the reception FIFO memory unit 52. The serial / parallel converter 48 is implemented with a 16-bit shift register. The reception word detection unit 50 is implemented as a counter. When the data output from the reception bit latch unit 46 is one word, the reception word detection unit 50 applies the reception write enable signal RXWE to the reception FIFO memory unit 52. Therefore, the reception FIFO memory 52 selects and stores the corresponding 16-bit parallel data DO output from the serial / parallel conversion unit 48 in response to the reception write enable signal RXWE. The reception FIFO memory unit 52 has a capacity of 16 bits x 16 (width), that is, 16 words of capacity, similarly to the transmission FIFO memory unit 30. As shown in FIG. 3C, the data value 7000H of D14 and the data value 7800H of D15, which are one of the data DOs of the serial / parallel conversion unit 48, are added to the reception data enable signal RXWE of the reception word detection unit 50. The data is written to the receiving FIFO memory section 52 by the receiver.

The reception word detection unit 50 not only detects every word of data output from the reception bit latch unit 46, but also counts the detected word and reaches 16 words. As shown in FIG. The reception completion interrupt signal IRQ is output to the CPU board 12 of the controller. The CPU board 12 outputs a control signal for reading the received data to the address decoder 32 in response to the received interrupt signal IRQ, and the address decoder 32 accordingly receives the FIFO memory unit 52 for reception. Output receive enable signal RXRE. Therefore, the CPU board 12 reads the 16-word reception data stored in the reception FIFO memory unit 52 via the data bus.

In the above description, data transmission processing such as the parallel / serial conversion unit 38, the timing control unit 36, the duty conversion unit 40, and the data transmission unit 42 is performed by the data receiving unit 44 and the receiving bit latch unit ( 46), the data processing can be performed at a higher speed since the data reception processing such as the serial / parallel conversion unit 48 and the reception word detection unit 50 is performed. In other words, the present invention performs fast asynchronous interfacing of data.

Finally, an operation for self-diagnosing the communication interface board 14 according to the present invention will be described.

The CPU board 12 of the communication device 10 transmits the control corresponding to the self-diagnosis mode to the address decoder 32 of the communication interface board 12 via the address bus and the control signal. The address decoder 32 decodes the control state corresponding to the self-diagnosis mode and outputs the loopback test signal TEST required for the self-diagnosis mode to the relay driver 54. In response to the loopback test signal TEST, the relay driver 54 outputs a relay drive signal DRV connected to the transmission transmission line 16-1 and the reception transmission line 16-2 to the relay unit 56. . The relay unit 56 forms a data path between the transmission transmission line 16-1 and the reception transmission line 16-2 in response to the relay drive signal DRV. Accordingly, the CPU board 12 transmits through the data bus. The failure of the board 14 can be known by applying the data to the communication interface board 14 and comparing the received data received by rope back from the communication interface board 14.

As described above, the interface device of the present invention writes the processing result of the main board into the transmission memory in word units, generates a transmission start signal, performs reading for transmission, and serially converts and duty converts the data into the information storage device. Receives the information output from the information storage device, converts it into a predetermined bit, converts it into a serial bit, writes it in word units in the receiving memory, and the received information reaches the predetermined number of received words regardless of the data transmission process. Sending an interrupt signal to the CPU board of the communication device causes the CPU board to receive the received information, thereby saving the data at high speed and reading the stored data at high speed.

In the present invention, the data to be transmitted and received is described in units of 16 words, but it is apparent to those skilled in the art that it can be described in units of 512 words in the spirit of the present invention.

Claims (9)

A serial interface apparatus for storing processing information of a communication system control unit in an information storage device and reading information stored in the information storage device, wherein the control signal corresponding to storage of the processing information, reading stored information, and self-diagnosis are decoded. Transmission memory means for storing parallel transmission data corresponding to the processing information in predetermined data units by control signal decoding means and processing information storage decoding of the control signal decoding means, and data transmission by storage and decoding of the control signal decoding means Timing control means for controlling predetermined timing generation for processing, data transmission processing means for converting the parallel transmission data into serial and predetermined duty ratio transmission data in response to the timing occurrence of the timing control means, and the converted transmission data. To the information author equipment through the transmission transmission path Data transmitting means for transmitting, receiving data corresponding to information stored in the information storage device via the receiving transmission path through a receiving transmission path, and receiving data of the data receiving means in predetermined data units. A data reception processing means for latching and converting the data into parallel and outputting the data; and a reception for outputting a write enable signal in response to detecting the received data in a first word unit, and outputting a reception completion signal in response to the detection in a second word unit. And storing the data word detection means and the parallel converted reception data in a predetermined data unit in response to the write enable signal, and storing the stored reception data by reading and decoding information of the decoding means in response to the reception completion signal. Characterized in that the receiving data storage means for outputting the control call of the communication system Interface Devices The interface apparatus according to claim 1, further comprising loopback test forming means for forming a loop between said data transmission means and said data receiving means in response to self-diagnosis of said control signal decoding means. The method of claim 2, wherein the loopback test forming means comprises: a relay driver for outputting a relay driving signal in response to the self-diagnostic decoding, and an output terminal of the data transmitting means and an input terminal of the data receiving means in response to the relay driving signal. Interface device characterized by consisting of a relay unit for connecting The interface apparatus according to claim 1, wherein the fraud transmission data storage means is a first-in, first-out memory having a capacity of 16 bits x 16 width. The interface apparatus according to claim 4, wherein the reception data storage means is a first-in, first-out memory having a capacity of 16 bits x 16 width. 6. The data transmission processing means according to claim 5, wherein the data transmission processing means converts the 16-bit parallel data of the first-in first-out memory into serial in response to a synchronization signal of the timing control means and outputs the serial / serial conversion unit and the timing control means. And an duty converter which converts the serially converted data into duty in a predetermined state in response to a conversion control signal. 7. The method of claim 6, wherein the timing control means divides, counts, and latches a predetermined clock signal in response to the transmission start signal according to the storage decoding of the control signal decoding means, thereby reading a read operation control signal into the transmission memory means. An interface device for outputting a synchronization signal to a serial converter and a duty conversion control signal to the duty converter; 6. The data receiving processing unit according to claim 5, wherein the data receiving processing unit comprises a latch unit for predetermined latching and outputting the reception data of the data receiving unit, and a serial / parallel conversion unit for converting serial data output from the latch unit into 16-bit parallel data. Interface device characterized in that The interface apparatus according to claim 1, wherein the reception data word detection means is a counter for counting the reception data in units of words.