KR100382437B1 - Method for driving plasma display panel - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel is provided to enhance relatively luminance of cells by performing repeatedly an addressing process, a discharge sustaining process, and a display erasing process. CONSTITUTION: A method for driving a plasma display panel includes an addressing process, a discharge sustaining process, and a display erasing process for display cells by applying a data pulse to an anode electrode group and applying a discharge start pulse and a discharge sustaining pulse to a cathode electrode group. The discharge sustaining process includes a process for applying simultaneously single discharge sustaining pulses having the relatively large pulse width to the cathode electrode group. The current due to the data pulse is limited by a predetermined current resistor.

Description

Driving Method of Plasma Display Element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display element, and more particularly to a memory driving method of a plasma display element.

In general, there are two methods of driving a plasma display device, a refresh driving method and a memory driving method. The refresh driving method is suitable for a small device, for example, a computer monitor, because the display brightness is relatively low, and the memory driving method is suitable for a larger device because the display brightness is relatively high. However, the above-described memory driving method also has a problem that the display brightness can be further increased so that it can be used for large devices such as large wall-mounted televisions.

1 is an exemplary view for explaining a conventional refresh driving method. FIG. 2 is a timing diagram for describing a driving waveform of FIG. 1. As shown in FIG. 1, the anode electrode groups A1, A2, A3, ..., Am-1, Am and the cathode electrode groups K1, K2, K3, ..., Kn-1, Kn has an XY matrix shape, and display cells C11, C12, C13, ..., Cnm are formed at each intersection. As shown in FIG. 2, each cathode electrode K1, K2, K3, ..., Kn-1, Kn is sequentially scanned with a predetermined frame period, for example, 16.67 mS (milli-second) period. Scan-On is performed, and at the same time, data pulses are applied to the corresponding anode electrodes A1, A2, A3, ..., Am-1, Am depending on the presence or absence of display data. As described above, a process of applying a data pulse to the corresponding anode electrode by the display data when the predetermined cathode electrode is scanned is called addressing. For example, when the data is applied only to the anode electrodes A1 and A3 when the cathode electrode K1 is scanned on, the display cells C11 and C13 cause display discharge. As shown in FIG. 2, when the voltage of the data pulse applied to the anode electrode is Vw volts (V) and the scan voltage applied to the cathode is −Vk volts (V), the display discharge voltage is Vw − (−Vk). ) = Vw + Vk. In the case where the discharge time is relatively long, the current limiting resistors R1, R2, R3, ..., Rm-1, Rm are required to protect the cells which are discharged. In the case of a plasma display element having a resolution of 640 x 480, the scan time per display cell, that is, the scan pulse width having a negative polarity, is a short time of about 33 microseconds. Where 640 is the number of anode electrodes (m) and 480 is the number of cathode electrodes (n). Accordingly, the refresh driving method is applied to a small device such as a computer monitor because the display brightness is relatively low.

3 is an exemplary diagram for describing a conventional memory driving method. 4 is a timing diagram for describing a driving waveform of FIG. 3. As shown in FIG. 3, the anode electrode groups A1, A2, A3, ..., Am-1, Am and the cathode electrode groups K1, K2, K3, ..., Kn-1, Kn has an XY matrix shape, and display cells C11, C12, C13, ..., Cnm are formed at each intersection. As shown in FIG. 4, each cathode electrode K1, K2, K3, ..., Kn-1, Kn starts discharge during a predetermined frame period, for example, 16.67 mS (milli-second) period. A series of pulses are applied, which are a writing pulse and a sustaining pulse. In addition, a predetermined data pulse is applied to each of the anode electrodes A1, A2, A3, ..., Am-1, Am. In Fig. 4, T1 denotes a period of the discharge start pulse, T2 denotes a period of the discharge sustain pulse, tw denotes the width of the discharge start pulse, and ts denotes the width of the discharge sustain pulse. Here, the period T1 of the discharge start pulse is tw + ts. In general, the period T1 of the discharge start pulse and the period T2 of the discharge sustain pulse are the same at 6 microseconds. That is, T1 = T2 = tw + ts = 6 ms. In the case where n cathode electrodes are provided, the discharge sustain time of each display cell is (Tf-n T1) · (ts / T2). Here, Tf is a frame period, which is 16.67 mS (milli-second) in this embodiment. In addition, n · T1 represents an addressing time (Addresing time) but overlaps the display erasing time (Erasing time) of the previous frame. Therefore, the time for which the discharge sustain pulse is applied to each cathode electrode per frame is (Tf-n T2). As a result, the discharge holding time of each display cell per frame becomes (Tf-n T2) · (ts / T2). In the present embodiment, since n = 480 and T1 = T2 = 6 microseconds, the time for which the discharge sustain pulse is applied to each cathode electrode per frame is 16.67-480 x 0.006 = 16.67-2.88 = 13.79 mS ( milli-second). Since the period T2 of the discharge sustain pulses is 6 microseconds, the number of discharge sustain pulses applied to each cathode electrode per frame is approximately 2,298 because the value is 13,790 / 6. Since the width ts of the discharge sustain pulse is 2 microseconds, the discharge sustain time of each display cell per frame is 2,298 x 2 = 4,596 microseconds = 4.596 milliseconds. have.

As shown in FIG. 4, the cells addressed by the discharge pulse and the data pulse initiate display discharge. Discharge is also maintained by an alternating discharge sustaining pulse. For example, if a data pulse is applied only to the anode electrodes A1 and A3 when the discharge pulse is applied to the cathode electrode K1, the display cells C11 and C13 start the display discharge, and the alternate discharge sustain pulse Discharge is maintained by (Sustaining pulse). As shown in FIG. 4, when the voltage of the data pulse applied to the anode electrode is Vw volts (V) and the scan voltage applied to the cathode is −Vk volts (V), the discharge start voltage is Vw − (−Vk). ) = Vw + Vk. The reason why the discharge can be maintained only by the scan voltage-Vk volts (V) is that the charged particles remain in the display cell for a short time after the start of the discharge. If the discharge start voltage or the discharge sustain voltage is continuously applied to the display cell, the display cell is destroyed due to the arc discharge inside the cell. In order to prevent this, current limiting resistors are used in the refresh driving method illustrated in FIG. 1, and a discharge pulse and a sustaining discharge having a relatively short pulse width are used in the conventional memory driving method illustrated in FIG. 3. Use a sustaining pulse. In particular, in the case of the memory driving method, as shown in FIG. 4, only a discharge sustaining pulse having a short pulse width is applied several times, thereby increasing the display luminance. On the other hand, in the erasing area in which the sustaining pulse does not occur, even if the data pulse Vw volt (V) is applied, the discharge sustain voltage-Vk volt (V) does not reach the display discharge. .

5 is a timing diagram according to the display cell operation state of FIG. 3. As shown in the drawing, in the conventional memory driving method, an addressing area, a discharge holding area, and a display erasing area are sequentially processed during one scan period. The addressing area has the same meaning as a discharge starting area. However, the sustaining area increases the display luminance by applying only an alternate discharge sustaining pulse having a short pulse width several times. There is a limit to this.

The driving method of the 2 gray scales which is the basis of the memory driving method described with reference to FIGS. 3, 4 and 5 is illustrated. Next, a memory driving method of 16 gray scales will be described.

6 is a timing diagram illustrating a memory driving method of 16 gray scales. In FIG. 6, reference numeral 1a denotes an addressing region of the first subfield, 1b denotes a discharge sustaining region of the first subfield, 1c denotes a display erasing region of the first subfield, 2a denotes an addressing region of the second subfield, 2b is a discharge holding area of the second subfield, 2c is a display erasing area of the first subfield, 3a is an addressing area of the third subfield, 3b is a discharge holding area of the third subfield, and 3c is a third subfield. A display erasing area, 4a represents an addressing area of the fourth subfield, 4b represents a discharge sustaining area of the fourth subfield, and 4c represents a display erasing area of the fourth subfield. As shown, one frame of 16.67 mS (milli-second), that is, one scan period is divided into four subfields, and the display luminance may be gradually controlled as the discharge holding time of each subfield is different. have. In Fig. 6, reference numeral T1 denotes a period of a discharge start pulse. Therefore, when the number of cathode electrodes is n, the time for the nth cathode electrode Kn to be addressed is n · T1. As shown, the addressing and display erase regions are implemented in an overlapped form and have the same time for each subfield. However, as the discharge sustain time is changed to 8T in the first subfield, 4T in the second subfield, 2T in the third subfield, and T in the fourth subfield, the display luminance may be gradually controlled. T is the discharge sustain time in the fourth subfield, that is, the last subfield.

To realize the memory driving method of the 16 gray scales as shown in Fig. 6, since one data is required for each subfield, 4 bits of data are used for one cell. When 4 bits of data per cell are (D3, D2, D1, D0), the first subfield is set by D3, which is the most significant bit, and the second subfield is set by D2, the third The subfields are addressed sequentially by D1 and the fourth subfield by D0. For example, if the data of the cell C11 is (1, 1, 0, 1), since there is data in the first subfield, the cell C11 is discharged and maintained for 8T. Next, since there is data in the second subfield, the cell C11 starts to discharge and is held for 4T. Next, since there is no data in the third subfield, the cell C11 is not discharged. Since there is data in the fourth subfield, the cell C11 starts to discharge and is maintained for the time of T. 7 is a table illustrating a discharge time of a cell according to 4-bit data of 16 gray scales.

6-bit data and six subfields are required to realize the 64 gray scales based on the above method. Therefore, compared with the case of realizing 16 gray scales, two addressing periods are further required, so that the total discharge holding time is shortened and the display luminance is lowered. As described above, in the memory driving method of the plasma display device, as the number of cathode electrodes increases or the number of gray scales, that is, the number of gray scales increases, the display luminance decreases relatively.

As described above, in the conventional memory driving method, as the discharge holding time is newly added as compared to the refresh driving method, the display luminance of the cell may be relatively increased. In the case of a plasma display device having 480 cathode electrodes, if the period T2 of the discharge sustain pulse is 6 microseconds, about 5.746 milli-seconds per scan cycle of 16.67 mS (milli-seconds). The discharge holding time of can be ensured. However, as illustrated in FIG. 4, there is a limit in increasing the display luminance by applying only a sustaining pulse having a short pulse width several times.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of driving a plasma display device capable of increasing display brightness for use in a large device.

1 is an exemplary view for explaining a conventional refresh driving method.

FIG. 2 is a timing diagram for describing a driving waveform of FIG. 1.

3 is an exemplary diagram for describing a conventional memory driving method.

4 is a timing diagram for describing a driving waveform of FIG. 3.

5 is a timing diagram according to the display cell operation state of FIG. 3.

6 is a timing diagram illustrating a memory driving method of 16 gray scales.

7 is a table illustrating a discharge time of a cell according to 4-bit data of 16 gray scales.

8 is an exemplary diagram for describing a memory driving method of the present invention.

9 is a timing diagram for describing a driving waveform of FIG. 8.

10 is a timing diagram according to the display cell operation state of FIG. 8.

* Explanation of symbols for main parts of the drawings

A1, A2, A3, ..., Am-1, Am: Anode electrode group

K1, K2, K3, ..., Kn-1, Kn: cathode electrode group,

C11, C12, C13, ..., Cnm: display cell

R1, R2, R3, ..., Rm-1, Rm: current limiting resistor

tss: unitary discharge holding time T1: period of discharge start pulse,

T2: period of alternate discharge sustain pulse tw: width of discharge start pulse,

ts: width of alternate discharge sustain pulse nT1: display erase and addressing time

n T2: Alternating discharge holding time.

In order to achieve the above technical problem, the driving method of the plasma display device according to the present invention includes a data pulse in the anode electrode group and a discharge pulse and a sustaining pulse in the cathode electrode group. In the memory driving method of the plasma display device in which addressing, sustaining, and erasing are sequentially performed on a display cell, the discharge sustaining process is relatively performed. A single discharge sustaining pulse having a large pulse width is simultaneously applied to the cathode electrode group, and the current by the data pulse is limited by a predetermined current limiting resistor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

8 is an exemplary diagram for describing a memory driving method of the present invention. 9 is a timing diagram for describing a driving waveform of FIG. 8. As shown in FIG. 8, the anode electrode groups A1, A2, A3, ..., Am-1, Am and the cathode electrode groups K1, K2, K3, ..., Kn-1, Kn has an XY matrix shape, and display cells C11, C12, C13, ..., Cnm are formed at each intersection. As shown in FIG. 9, each cathode electrode K1, K2, K3, ..., Kn-1, Kn is discharged during a predetermined frame period, for example, 16.67 mS (milli-second) period. A series of pulses consisting of a writing pulse and a sustaining pulse is applied. In addition, a predetermined data pulse is applied to each of the anode electrodes A1, A2, A3, ..., Am-1, Am. In Fig. 9, the symbol tss denotes the width of the single type discharge sustain pulse that is simultaneously applied to the cathode electrode groups K1, K2, K3, ..., Kn-1, Kn. Reference symbol T1 denotes the period of the discharge start pulse, T2 denotes the period of the alternate discharge sustain pulse, tw denotes the width of the discharge start pulse, and ts denotes the width of the alternate discharge sustain pulse. Here, the period T1 of the discharge start pulse is tw + ts. In general, the period T1 of the discharge start pulse and the period T2 of the discharge sustain pulse are the same at 6 microseconds. That is, T1 = T2 = tw + ts = 6 ms. As shown in Fig. 9, the discharge sustain pulse according to the present invention includes an alternate discharge sustain pulse applied successively to the discharge start pulse and a point in time at which addressing of one frame is completed, that is, addressing of the final cathode electrode Kn is completed. From this point of view, a single discharge sustain pulse having a relatively large pulse width tss is included. As shown in FIG. 8, current limiting resistors R1, R2, R3, ..., Rm-1, Rm are connected to each of the display cells C11, C12, C13, ..., Cnm. By limiting the current caused by this, it is possible to protect each display cell C11, ..., Cnm during relatively long discharge holding. As described above, instead of limiting the current caused by the data pulse, the discharge sustain time can be relatively long, so that the display brightness can be increased for use in a large device. As shown in Fig. 9, the generation time of the alternating discharge sustain pulse per frame is a value obtained by multiplying the number n of cathode electrodes by the period T2 of the discharge sustain pulse, that is, n · T2. Accordingly, the number of alternating discharge sustain pulses per frame is n · T2 / T2 = n. That is, the number of alternating discharge sustain pulses is equal to the number of cathode electrodes. In the present embodiment, since the number of cathode electrodes is 480, the number of alternating discharge sustain pulses is also 480. Since the width ts of the alternate discharge sustain pulse is 2 microseconds, the alternate discharge sustain time per frame becomes 480 x 2 = 960 microseconds. In FIG. 9, the addressing time per frame is n · T1, which is a value obtained by multiplying the number n of cathode electrodes by the period T1 of the discharge start pulse. The addressing time here is a concept overlapping with the display erasing time in the previous frame step. As described above, the generation time of the alternating discharge sustaining pulse per frame is n · T2, and generally T1 = T2 = 6 microseconds. Thus, one frame can be divided into an addressing time, an generation time of an alternate discharge sustain pulse, and a single discharge sustain time. Since the addressing time and the generation time of the alternating discharge sustain pulse are 6 n ㎲ (micro-second), the same, the single discharge sustain time tss becomes Tf-12n / 1,000 = 16.67-5.76 = 10.91 mS (milli-second). Where Tf is one frame period, typically 16.67 mS (milli-second). Therefore, the discharge holding time of each display cell per frame is the sum of the alternating discharge holding time n · ts and the single type discharge holding time tss, so that in the present embodiment, 0.96 + 10.91 = 11.87 mS (milli-second). In the conventional memory driving method as shown in FIG. 4, since the discharge holding time of each display cell is 4.596 mS (milli-second) per frame, the luminance can be improved by 11.87 / 4.596 times and 2.58 times compared with the conventional case.

As illustrated in FIG. 9, the cells addressed by the discharge pulse and the data pulse initiate display discharge. Discharge is also maintained by alternating and single sustaining pulses. For example, if a data pulse is applied only to the anode electrodes A1 and A3 when the discharge pulse is applied to the cathode electrode K1, the display cells C11 and C13 start the display discharge, and the alternate discharge sustain pulse Discharge is maintained by (Sustaining pulse). As shown in FIG. 9, when the voltage of the data pulse applied to the anode electrode is Vw volts (V) and the scan voltage applied to the cathode is −Vk volts (V), the discharge start voltage is Vw − (−Vk). ) = Vw + Vk. The reason why the discharge can be maintained only by the scan voltage-Vk volts (V) is that the charged particles remain in the display cell for a short time after the start of the discharge. If the discharge start voltage or the discharge sustain voltage is continuously applied to the display cell, the display cell is destroyed due to the arc discharge inside the cell. Even if the display cell is not destroyed, its life is shortened. To prevent this, as shown in Fig. 8, as each display cell C11, C12, C13, ..., Cnm is connected to the current limiting resistors R1, R2, R3, ..., Rm-1, Rm, By limiting the current caused by the data pulse, it is possible to protect each display cell C11, ..., Cnm during relatively long discharge sustaining. On the other hand, in the erasing area in which the sustaining pulse does not occur, even if the data pulse Vw volt (V) is applied, it does not reach the discharge sustain voltage-Vk volt (V), so that no display discharge occurs. .

10 is a timing diagram according to the display cell operation state of FIG. 8. As shown, the driving method according to the present invention may be roughly divided into a display erasing and addressing process and a discharge sustaining process. It can be seen that when the display erase area and the addressing area are overlapped with each other by connecting FIG. 10 with respect to one frame. In FIG. 10, the discharge sustaining region may be divided into an alternating discharge sustaining region sequentially generated for each cathode electrode and a single discharge sustaining region simultaneously generated in all of the cathode electrode groups. Therefore, one frame period Tf is divided into display erase and addressing time n · T1, alternating discharge sustain time n · T2, and single discharge sustain time tss. Where n is the number of cathode cathodes, T1 is the cycle of the discharge start pulse, and T2 is the cycle of the alternate discharge sustain pulse. In the present embodiment, one frame period Tf is 16.67 mS (milli-second), and the period T1 of the discharge start pulse and the period T2 of the alternate discharge sustain pulse are 6 microseconds equal to each other. Therefore, the display erase and addressing time n · T1 and the alternate discharge sustain time n · T2 become equal to each other.

The present invention is not limited to the above embodiment, and its use and improvement are possible at the level of those skilled in the art. For example, when 16 or 64 gray scales are applied, the driving method of the 2 gray scales described in FIGS. 8, 9 and 10 may be applied according to the application principle described in FIGS. 6 and 7.

As described above, according to the driving method of the plasma display device according to the present invention, the display brightness can be increased for use in a large-sized device.

Claims (12)

The data driving method is applied to the anode electrode group and the discharge start pulse and the discharge sustain pulse are applied to the cathode electrode group, thereby sequentially addressing, discharging sustaining, and erasing the display cells. The method of claim 1, wherein the discharge sustaining step includes applying a single discharge sustaining pulse having a relatively large pulse width to the cathode electrode group at the same time, and the current by the data pulse is limited by a predetermined current limiting resistor. A method of driving a plasma display element, characterized by the above-mentioned. The method of driving a plasma display device according to claim 1, wherein the discharge sustain pulse comprises an alternate discharge sustain pulse having a relatively short pulse width and the single discharge sustain pulse. The method of driving a plasma display element according to claim 1 or 2, wherein the period of the discharge start pulse is a sum of the width of the discharge start pulse and the width of the alternate discharge sustain pulse. 4. The method of driving a plasma display device according to claim 3, wherein the period of the discharge start pulse is a difference between a discharge start time of one cathode cathode and a discharge start time of the next cathode cathode. The plasma display device according to claim 2 or 4, wherein the generation time of the alternate discharge sustain pulse per frame is a value obtained by multiplying the number of the cathode electrodes by the period of the alternate discharge sustain pulse. Driving method. The method of driving a plasma display device according to claim 2, wherein the number of alternating discharge sustain pulses is equal to the number of cathode electrodes. The method of driving a plasma display device according to claim 6, wherein the alternate discharge sustain time is a value obtained by multiplying the number of the cathode electrodes by the pulse width of the alternate discharge sustain pulse. The plasma display device according to claim 1, wherein the method for driving the plasma display device comprises one frame divided into an addressing and display erasing time, an generation time of an alternating discharge sustaining pulse, and a single discharge sustaining time. Driving method. The method of driving a plasma display device according to claim 8, wherein the single type discharge sustain time is a pulse width of the single type discharge sustain pulse. The method of driving a plasma display device according to claim 4 or 8, wherein the addressing and display erasing time is a value obtained by multiplying the number of the cathode electrodes by the period of the discharge start pulse. 9. The method of driving a plasma display device according to claim 2 or 8, wherein the generation time of the alternate discharge sustain pulse is a value obtained by multiplying the number of the cathode electrodes by the period of the discharge sustain pulse. 9. The method of driving a plasma display element according to claim 8, wherein the addressing and display erasing time is the same as the generation time of the alternate discharge sustain pulse.