KR100378712B1 - 4 receiving clock selection circuit in time division switch of mobile terminal - Google Patents

Abstract

The present invention uses a time division switch of an electronic switch for a PCS to select a reception clock to use as an internal clock, and also time division of a mobile communication system capable of selecting a more stable one of four reception clocks among functions for transmitting to a peripheral device. A quadrature reception clock selection circuit in a switch, wherein the quadrature reception clock selection circuit in a time division switch of a mobile communication system according to the present invention is provided in a mobile communication system having a time division switch board (TSWA). A first multiplexer for selecting and outputting only one received clock signal according to a clock control signal; A receiving unit for masking a clock state signal VALID output from the time division switch board TSWA with a counter power alarm signal OPFL; A second multiplexer for multiplexing and outputting a plurality of clock state signals (VALID) output from the receiving unit; And a coder for transmitting the clock control signal obtained by encoding the output signal of the second multiplexer to the first multiplexer.

Description

Quad Receive Clock Selection Circuit in Time Division Switch of Mobile Communication System {4 RECEIVING CLOCK SELECTION CIRCUIT IN TIME DIVISION SWITCH OF MOBILE TERMINAL}

The present invention relates to a quadrature receive clock selection circuit in a time division switch of a mobile communication system. In particular, the quadrature reception clock selection circuit in a time division switch is adapted to prevent abnormal clock selection when the power board is turned on or off. It is about.

In general, the PCS time division switch has an active / standby redundancy structure and a planar redundancy structure. This allows two identical boards to behave identically at the same time but control the buffer with redundant signals at the input or output stage.

The time division switch board (TSWA) 20a shown in FIG. 1 receives the CP2 (16.384 MHz), the FP2 (8KHz) and the clock status signal VALID from the four data link boards LNKA 10a to 10d, respectively. A pair of CP2 and FP2 is selected according to the state of the clock state signal VALID.

FIG. 2 is a diagram illustrating a conventional quadrature clock signal selection procedure. Referring to FIG. 2, the four clocks and the clock state signals VALID received from the data link boards 10a to 10d are input to the time division switch board TSWA 20a. The time division switch board (TSWA) 20a selects four clock and clock status signals VALID received from the data link boards 10a to 10d using the logic shown in FIG.

The data link boards 10a to 10d basically transmit one of four clock state signal (VALID) signals in the 'low' state and the other three signals in the 'high' state.

In the prior art, the time division switchboard (TSWA) 20a selects the input clock only by the clock status signal VALID. This clock status signal (VALID) shakes abnormally when the power board is turned on or off. As shown in FIG. 2, the time division switch board (TSWA) 20a receives a clock and a clock state signal VALID from the data link boards 10a to 10d, and selects one of four signals according to the clock state signal VALID. Select clocks.

However, in the related art, one of four clock sources CP2 and FP2 is selected and distributed to internal and peripheral devices based on the clock state signal VALID. This is a problem that may select a bad clock that may occur when the clock state signal (VALID) signal that can occur when the power on / off abnormally shaken. That is, the prior art had a problem that can not properly cope with abnormal cases that may occur when operating the system.

An object of the present invention is to solve the problems of the prior art mentioned above, four of the functions of selecting the reception clock in the time division switch of the electronic switch for PCS to use as an internal clock, and also transmit to the peripheral device The present invention provides a quadrature receive clock selection circuit in a time division switch of a mobile communication system capable of selecting one of the more stable clocks.

1 is a block diagram of a typical time division switch board and a data link board.

2 is a diagram for explaining a conventional quadruple clock signal selection procedure.

3 is a view for explaining a quadratic received clock signal selection procedure according to the present invention.

* Description of the symbols for the main parts of the drawings *

50: multiplexer

60: receiver

61 ~ 64: Or gate

70: multiplexer

80: encoder

In order to achieve the above object, in the time division switch of the mobile communication system according to the present invention, the quadrature reception clock selection circuit is provided in the mobile communication system having a time division switch board (TSWA). A first multiplexer for selecting and outputting only one according to a clock control signal; A receiver configured to receive a clock state signal VALID output from the time division switch board TSWA; A second multiplexer for multiplexing and outputting a plurality of clock state signals (VALID) output from the receiving unit; And a coder for transmitting the clock control signal obtained by encoding the output signal of the second multiplexer to the first multiplexer.

According to the features of the present invention, the time division switch of the mobile communication system according to the present invention does not depend on the clock state signal (VALID), which is a problem of the conventional clock reception method in designing the quadrature clock selection circuit, It has the advantage of improving the stability and reliability of the system by designing the structure that ignores the clock status signal (VALID) when receiving an alarm signal.

Hereinafter, with reference to the accompanying drawings will be described the configuration and operation of the present invention.

3 is a diagram for describing a procedure for selecting a quad receive clock signal according to the present invention. Referring to FIG. 3, a quadrature reception clock selection circuit in a time division switch of a mobile communication system of the present invention includes: a first multiplexer 50 for selecting and outputting only one quadrature reception clock signal according to a clock control signal; A receiver 60 for masking the clock state signal VALID output from the time division switch board TSWA with the counter power alarm signal OPFL; A second multiplexer (70) for multiplexing and outputting a plurality of clock state signals (VALID) output from the receiver; And an encoder 80 which transmits a clock control signal obtained by encoding the output signal of the second multiplexer 70 to the first mux.

The operation of the quad receive clock selection circuit in the time division switch of the mobile communication system according to the present invention configured as described above will be described.

The clock state signal VALID received by the time division switch board TSWA is input to each of the order gates 61 to 64 of the receiver 60 of FIG. 3. The clock state signal VALID is first masked by the counterpart power alarm signal OPFL, and secondly, a plan is selected by the time division switchboard TSWA identification signal in the second multiplexer 70. That is, the state is 'low' for the A-plan and 'high' for the B-plan, and the 'A' or 'B' side input shown in FIG. 3 is selected. Next, four selected clock state signals VALID are encoded and used as input clock selection logic of the encoder 80.

At this time, if the power board of the A-plan is turned off, the A-plan board of the time division switch board (TSWA) is not powered, so the clock received from the data link board in the B-plan of the time division switch board (TSWA) And clock status signal (VALID) should be selected. Therefore, since the B-plan of the time division switch board TSWA has a high board identifier, the output of the clock state signal VALID1 in the second multiplexer 70 selects the 'B' plan. At this time, the input terminals VALID0A and VALID 1A of the 'B' plan are input at the 'high' level when they are input to the second multiplexer 70 by the OPFL ('high' in case of failure). The clock state signal VALID1 is again encoded by the encoder 80 and then selects an input clock of the first multiplexer 50.

Therefore, even if the power of the B-plan is turned off, there is no problem in selecting the reception clock, and since the OPFL signal is at the 'low' level even in the normal state, the influence of the input clock state signal VALID of the receiver 60 is not affected. Quad receive clock can be selected reliably without receiving.

The quadrature clock selection circuit in the time division switch of the mobile communication system according to the present invention described above has a problem in the conventional clock reception method when the quadrature clock is input from the PCS electronic time exchanger to the time division switch. It does not rely on the in-clock state signal VALID, and it is designed to receive a power alarm signal and ignore the clock state signal VALID when an alarm occurs, thereby improving the stability and reliability of the system.

Claims (1)

In a mobile communication system having a time division switchboard (TSWA), A first multiplexer for selecting and outputting only one input multiple reception clock signal according to a clock control signal; A receiving unit for masking a clock state signal VALID output from the time division switch board TSWA with a counter power alarm signal OPFL; A second multiplexer for multiplexing and outputting a plurality of clock state signals (VALID) output from the receiving unit; And a coder for transmitting a clock control signal encoding the output signal of the second multiplexer to the first multiplexer.