KR100377933B1 - Automatic clock switching circuit - Google Patents

Abstract

PURPOSE: An automatic clock switching circuit is provided to generate a switching control signal and stabilize an operation of a digital system by monitoring digitally a state of a remote clock. CONSTITUTION: An automatic clock switching circuit includes a clock switching portion, a frequency multiplication portion(32), and a clock switching control signal generation portion(30). The clock switching portion outputs selectively a remote clock as a system operating clock and switches a local clock to the system operating clock by selecting the local clock according to an active state of a clock switching signal. The frequency multiplication portion performs a frequency multiplication process for the local clock. The clock control signal generation portion performs a repeated counting operation during a predetermined time by sampling the remote clock and activates the clock switching signal when the counted value is less than the predetermined value.

Description

Clock automatic switching circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital clock switching circuit of a data communication system that processes signals in synchronization with a clock, and more particularly, to a circuit for detecting an error state of a remote clock transmitted from the outside and automatically switching to a local clock at a high speed.

In general, a digital data communication system using a network is configured to transmit and receive data to and from each other by synchronizing synchronism between a communication system and another communication system. One of the most important problems in communication systems.

The digital communication system as described above has a clock recovery circuit that recovers and extracts a network synchronization clock (hereinafter referred to as a "remote clock") from the data transmitted from the transmitter. In addition, the digital communication system as described above, in addition to the clock recovery circuit as described above, a body clock on the receiving side for enabling local communication when the remote clock is abnormal due to network loss or other reasons (hereinafter referred to as "local clock"). As a built-in clock switching circuit for automatic switching, it automatically switches to local clock when an external remote clock is abnormally input.

However, the majority of clock automatic switching circuits according to the prior art take a long time to transfer to the local clock after the loss of the remote clock by determining whether the clock is normal by using the analog method of the remote clock extracted from the received data. This causes problems that cause many difficulties in synchronizing the network. Such a problem will be obviously recognized by the configuration and its description shown in FIG. 1 below.

FIG. 1 is a diagram illustrating a conventional clock automatic switching circuit, and selectively outputs a local clock 12, a remote clock 14, and the remote clock 14 as an operation clock of a system, in response to activation of a clock switching signal. And a clock switching circuit 18 for selecting a local clock 12 to switch to a system operation clock, and a switching signal generating circuit 20 for detecting an abnormality of the remote clock 14 and activating a clock switching signal supplied to the clock switching circuit 16. At this time, the clock switching signal generation circuit 20 is composed of a rectifier circuit 22, a voltage multiplication circuit 24, a comparator 26. In the above configuration, reference numeral 16 denotes a dip switch, which is connected as a user option to selectively input the local clock 12 and the remote clock 14 into the system. In the description of the present invention, the dip switch 16 shows a state in which the local clock 12 and the remote clock 14 are selected and input to the three-state buffers 28 and 30 in the clock switching circuit 18.

First, referring to FIG. 1, the operation according to the related art is assumed to be low before the output of the comparator 26 in the clock switching signal generation circuit 20 is described.

Now, when the local clock 12 and the remote clock 14 shown in FIG. 1 are normally input, these clocks are supplied to the input terminals of the three-state buffers 28 and 30 in the clock switching circuit 18 through the dip switch 16. At this time, the output of the comparator 26 in the clock switching signal generation circuit 20 is output as "low", so that only the three-state buffer 30 is enabled to supply the remote clock 14 into the system so as to be synchronized with the clock from the outside.

In the above state, the rectifier circuit 22 inputting the remote clock 14 rectifies the remote clock 14 and supplies it to the voltage multiplication circuit 24. The rectifier circuit 22 is usually composed of elements such as a resistor and a capacitor to rectify the remote clock 14 by charging and discharging the RC time constant corresponding to the cycle of the input clock. At this time, if the remote clock 14 is normally input, the value of the element in the rectifier circuit 22 should be appropriately selected so that the level of the output voltage becomes stable.

The voltage output from the rectifier circuit 22 is supplied to a voltage multiplication circuit 24. The voltage multiplying circuit 24 multiplies and outputs the voltage of the voltage output from the rectifying circuit 22 as a signal having a level higher than that of the reference voltage Vref described later. That is, when the remote clock 14 is normally input, it is made higher than the level of the reference voltage Vref set in the comparator 26.

When the remote clock 14 is normally input by the above configuration, the multiplication voltage input to the comparator 26 becomes higher than the level of the reference voltage Vref supplied to the non-inverting terminal of the comparator 26. At this time, the comparator 26 compares the voltage input to the non-inverting terminal (+) and the multiplication voltage input to the inverting terminal (-) and outputs a "low" signal as a clock switching control signal when the level of the multiplication voltage is higher. do. Thus, the tri-state buffer 30 in the clock switching circuit 18 is enabled to supply the remote clock 14 into the system. At this time, the tri-state buffer 28 is disabled by the output " high "

On the other hand, if the remote clock 14 is not normally input due to a transmission path or other reasons, the output of the rectifying circuit 22 drops to almost ground level, which causes the level of the inverting terminal (-) of the comparator 26 to become the non-inverting terminal (+). ) Falls below the level of the reference voltage Vref. Therefore, if the remote clock 14 is not normally input, the output of the comparator 26 is output "high".

When the output of the comparator 26 is " high ", the 3-state buffer 28 in the clock switching circuit 18 is enabled by the output of the inverter 32 to supply the local clock 12 into the system, and the 3-state buffer 30 Is enabled. In other words, when the remote clock 14 from the outside is not normally input, the clock mode is automatically switched to the local clock which is the internal clock of the system.

However, in the conventional circuit having the configuration as shown in FIG. 1, the circuit which detects the normal input of the remote clock 14 uses an analog element, so that when the remote clock is abnormal, it takes a long time to automatically switch to the local clock. Problems caused Great problems in stabilizing the system. That is, since the structure of the rectifier circuit 22 uses elements such as capacitors and resistors, there has been a problem that reliability cannot be generated because the output of the rectifier circuit 22 does not generate an output in response to the change of the remote clock at high speed.

In addition, the voltage multiplication circuit also takes considerable time to raise the voltage to the desired level by multiplying the voltage of the analogue, and thus it is difficult to cope with the change of the remote clock quickly, which causes considerable difficulty in local communication due to the significant time delay of the clock switching time. do.

Accordingly, it is an object of the present invention to provide a clock automatic switching circuit for digitally detecting the presence or absence of an error of a remote clock to speed up automatic switching of remote and local clocks.

Another object of the present invention is to provide a clock automatic switching control signal generation circuit which detects an error state of a remote clock input from the outside at a high speed and automatically switches to a local clock.

In order to achieve the above object, the present invention provides a clock automatic switching circuit of a digital system having terminals for inputting a remote clock and a local clock, wherein the frequency of the local clock is multiplied by a multiple of the remote clock and output as a sampling clock. A frequency multiplier circuit, a sampling circuit for sampling and outputting the remote clock by the multiplied sampling clock, and a sample signal output from the sampling circuit repeatedly counting for a predetermined time, wherein the counted value is a preset value. A counting determination circuit which selects and outputs a first voltage in response to an abnormality and outputs a second voltage that is less than the first voltage when the counting value is less than or equal to a preset value, and a voltage and a preset voltage output from the counting determination circuit. Comparator that compares reference voltage and generates clock switching control signal Selective output in the operation clock of the remote keulreokreul system, characterized in that in response to the activation of the clock switching signal composed of a clock switching circuit for selecting and switching to the system operation clock of the local clock.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings of the embodiments of the present invention, those having substantially the same configuration and function as those in the above-described drawings will use the same reference numerals.

2 is a diagram illustrating a clock automatic switching circuit according to the technique of the present invention, which multiplies the frequency of the local clock 12 by a multiple of the remote clock and outputs the frequency multiplication circuit 32 and the remote clock 14. A sampling circuit 34 for sampling and outputting the multiplied sampling clock and a sample signal output from the sampling circuit 34 repeatedly counting for a predetermined time and responding when the counted value is equal to or greater than a preset value. A counting determination circuit 36 which selects and outputs a second voltage that is less than the first voltage when the counting value is less than or equal to a preset value, and compares the voltage output from the counting determination circuit 36 with a preset reference voltage. Clock switching control signal generation circuit 30 comprising a comparator 38 for generating a switching control signal Tri-state buffer of the first DIP switch 16 and clock switching circuits 18, 28 degrees and is configured is connected between the 30.

The clock automatic switching circuit configured as shown in FIG. 2 frequency-multiplies the local clock 12, samples the remote clock 14 using the multiplied frequency, repeatedly counts the number of sampled values in a predetermined period, and the counting value is constant. When it has a continuous value or more, the remote clock is determined to be normal to operate to control the generation of the clock switching control signal. Its detailed operation will be more clearly appreciated by the following description.

Now, when the local clock 12 and the remote clock 14 are input to the circuit constructed as shown in FIG. 2, the frequency multiplication circuit 32 multiplies the local clock 12 and supplies it to the sampling clock of the sampling circuit 34. FIG. At this time, the frequency multiplication multiplies the local clock such that the clock is several times the remote clock 14. That is, the local clock 12 is multiplied to a value that satisfies the Nyquist theorem so that the frequency at which the remote clock 14 can be normally sampled.

The sampling circuit 34 samples the remote clock 14 by the multiplied sampling clock, that is, the clock output from the frequency multiplication circuit 32, and supplies the remote clock 14 to the count determination circuit 36. The count determination circuit 36 repeatedly counts the sampled clock for a preset period. In response to the counting value being greater than or equal to the preset value, the controller selects and outputs a first voltage. When the counting value is less than or equal to the preset value, the controller outputs a second voltage lower than the first voltage.

For example, when the input of the remote clock 14 is normally input and the counter value in the counter discrimination circuit 36 always has a predetermined value or more, the comparator 38 is supplied with a first voltage which is always set higher than the value of the reference voltage Vref. However, when the input of the remote clock 14 is abnormally input due to the transmission line or other causes, the counter value constant value in the counter discrimination circuit 36 falls below, wherein the counter discrimination circuit 36 is set to be lower than the reference voltage Vref. The second voltage is output.

Accordingly, the comparator 38 compares the reference voltage Vref input to the non-inverting terminal (+) with the level input to the inverting terminal (−) and activates or deactivates the clock switching control signal as described above with reference to FIG. 1. That is, when the remote clock 14 is abnormally input, the reference voltage inputted to the non-inverting terminal (+) of the comparator 38 because the value counted for a predetermined period by the counter in the count discrimination circuit 36 falls below a preset value. The second voltage is lower than Vref. Thus, comparator 38 activates the clock transfer signal to a logic " high ".

At this time, the 3-state buffer 30 in the clock switching circuit 18 is disabled and the 3-state buffer 28 is enabled by the output of the inverter 32, so that the clock source supplied to the system is automatically controlled from the remote clock 14 to the local clock 12. Is switched to. Contrary to the above, when the remote clock 14 is normally input, the output of the counter discrimination circuit 36 outputs a first voltage higher than the reference voltage Vref set in the comparator 38 so that the comparator 38 outputs a logic " low " Enable 3-state buffer 30 in 18 is enabled.

Therefore, the clock automatic switching circuit of the present invention configured as shown in FIG. 2 digitally monitors whether the remote clock is normally present and generates a switching control signal, so that a loss state of the remote clock is detected even when the remote clock is used at a high frequency. Automatic switching to the local clock can stabilize the operation of the digital system in synchronization with the clock.

1 is a diagram showing a clock automatic switching circuit according to the prior art.

2 illustrates a clock automatic switching circuit according to the techniques of the present invention.

Claims (3)

A clock automatic switching circuit of a digital system having terminals for inputting a remote clock and a local clock, Clock switching means for selectively outputting the remote clock as an operation clock of a system and selecting the local clock and switching the system clock to a system operation clock in response to activation of a clock switching signal; Frequency multiplication means for frequency multiplying the local clock; And a clock switching control signal generating means for sampling the remote clock as the multiplied frequency and repeatedly counting the sampled signal for a predetermined time, and activating the clock switching signal in response to the counted value being less than or equal to a predetermined value. Clock automatic switching circuit comprising. The method of claim 1, wherein the clock switching means, Automatic switching of the clock, characterized in that each input terminal of the local clock terminal and the remote clock terminal comprises a three-state buffer for inputting the inverted signal of the clock transfer control signal and the clock transfer control signal to each control terminal. Circuit. A clock automatic switching circuit of a digital system having terminals for inputting a remote clock and a local clock, A frequency multiplication circuit that multiplies the frequency of the local clock by a multiple of the remote clock and outputs the sampling clock; A sampling circuit for sampling and outputting the remote clock by the multiplied sampling clock; The sample signal output from the sampling circuit is repeatedly counted for a preset time, and when the counted value is greater than or equal to the preset value, the first voltage is selected and outputted. The first voltage is output when the counting value is less than or equal to the preset value. A counting discrimination circuit for outputting a second voltage that is more familiar; A comparator for generating a clock switching control signal by comparing a voltage output from the counting determination circuit with a preset reference voltage; And a clock switching circuit for selecting and outputting the remote clock as an operation clock of the system and selecting the local clock and switching the system clock to a system operation clock in response to the activation of the clock switching signal.