KR100369277B1 - Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode - Google Patents

Abstract

In accordance with a preferred embodiment of the present invention, a device and method are provided that reduce power consumption by reducing unnecessary node-toggling. A preferred embodiment of the present invention utilizes a pull-up or pull-down transistor that pulls the input of the circuit to a state that minimizes power consumption while the circuit is inactive. Reduce unnecessary node toggling By keeping the circuit input high or low during inactivity, node toggling is removed or reduced in that circuit. In a preferred embodiment of the present invention, all inputs to the circuit are pulled after a predetermined inactivity time in which the leakage in the circuit is proportional to the leakage current of the transistor with the largest leakage. By timing input pulling in proportion to leakage current, power consumption is minimized without the excess power loss due to pooling itself.

Description

DEVICE AND METHOD TO REDUCE POWER CONSUMPTION IN INTEGRATED SEMICONDUCTOR DEVICES USING A LOW POWER GROGGY MODE}

Related Applications

This application is issued to U.S. Patent Application Serial No. 09 / 120,211 entitled "LOW POWERING APPARATUS FOR AUTOMATIC REDUCTION OF POWER IN ACTIVE AND STANDBY MODES" by Dean et al. US Patent Application No. 09 / 159,898 entitled "ASIC LOW POWER ACTIVITY DETECTOR TO CHANGE THRESHOLD VOLTAGE" by Dean et al. 97-204). These two related applications are assigned to this registered assignee and are incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to power savings in semiconductor devices.

The electronics industry is now prospering worldwide because of the large number of partially integrated circuit semiconductor devices. Integrated semiconductor devices are designed and used in almost all devices today. In many applications, power consumption is a very important topic for several reasons. For example, in portable devices such as cordless phones, battery life and battery size are major design concerns. Consumers want portable electronic devices that operate as long as possible with a single battery charge, and also want devices including batteries to be as small and portable as possible. Therefore, there is an urgent need to reduce the power consumption of the device so that battery life can be extended and / or the size of the battery small.

In other applications, power consumption is extremely important because it is directly related to the amount of heat generated by the device. Semiconductor devices that consume more power generate more heat. In applications where thermal sensitivity is extremely important, reducing power consumption reduces the heat generated by the device.

To achieve low power consumption, many portable systems have a sleep mode or standby mode that reduces power consumption while inactive. In this prior art sleep mode, some parts of the system are powered down while others operate at reduced clock frequencies. Power consumption during inactivity is reduced by turning off the non-core parts of the system and operating the rest of the system at a reduced clock frequency. Then, when a start input stimulus is detected, the clock frequency returns to full-speed again and power is reapplied to the previously off portion of the system.

Although these systems reduce power consumption during inactivity, these systems also have some disadvantages. One of these drawbacks is that there is a time delay for the system to recover full functionality from sleep function. Specifically, since some parts of the system are in a substantially off state during sleep mode, the system cannot respond immediately if normal function is required. Instead, the system's normal functioning is restored only after the system is turned on during sleep mode, and all required data is loaded into or unloaded from the previously turned off part of the system. Because of this delay time needed to recover from sleep function to normal function, sleep mode cannot be used in systems where immediate function is required upon activation of the start input.

Thus, there is a need to reduce power consumption by reducing power consumption during inactivity while maintaining the ability to be immediately activated to normal function.

According to the present invention, a device and method for reducing power consumption while maintaining normal function are provided. In a preferred embodiment of the present invention the power consumption is reduced by having the device or a portion of the device in a groggy mode. Preferred half-sleep modes include reducing the operating clock speed and then increasing the source-to-body voltage bias. Increasing the source-to-body voltage bias reduces the sub-threshold current of the integrated circuit device transistors, greatly reducing power consumption during inactivity while maintaining normal functionality at a reduced operating clock rate. Can be reduced. The device in half-sleep mode can react immediately to the start input at a reduced operating clock rate if needed again. In this case, the source-to-body voltage bias is reduced and the clock speed is increased to normal operating level. Thus, in a preferred embodiment of the present invention, the inactive device enters a half-sleep mode that consumes less power while maintaining normal function at a reduced rate. As a result, the device has the ability to react immediately when needed and can quickly return to normal operating speed.

The above and other features and advantages of the present invention will become apparent from the more detailed description of the preferred embodiments of the present invention as shown in the accompanying drawings.

1 is a schematic diagram of a logic circuit and mechanism for setting a logic circuit in a half-sleep mode or unsetting from a half-sleep mode in accordance with one preferred embodiment of the present invention;

2 is a schematic diagram of an example n and p channel transistor showing a source-to-body bias;

3 is a graph showing the drain current of an n-channel transistor against the gate voltage when the source-to-body bias is 0 mV and 300 mV;

4 is a cross-sectional view of an exemplary n-channel and p-channel transistor in accordance with a preferred embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

102: circuit 104: transition detector

106: active state input 108: OR gate

110: pulse stretcher 112, 126: latch

114, 122: Inverter 116, 124: Single short

118, 120: delay 128: voltage regulator

130: 2-speed clock

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements.

According to the present invention, an apparatus and method for reducing power consumption while maintaining normal function are provided. In a preferred embodiment of the present invention, power consumption is reduced by entering a groggy mode while the device or a portion of the device is in an inactive state. Preferred half-sleep modes include reducing the operating clock speed and then increasing the source-to-body voltage bias. Increasing the source-to-body voltage bias reduces the device transistor's sub-threshold current, significantly reducing standby power consumption while inactive while maintaining normal functionality at a reduced operating clock rate. Can be. When a device in half-sleep mode goes back to operating mode, it can immediately respond to an input stimulus at a reduced operating clock rate. In this case, the source-to-body voltage bias is reduced and the clock speed is increased to normal operating level.

Referring to FIG. 1, a system 100 in accordance with a preferred embodiment of the present invention is illustrated. System 100 includes a half dormant mode mechanism for putting circuit 102 and circuit 102 in or out of half dormant mode. The half-sleep mode mechanism includes a transition detector 104, an activity input 106, an OR gate 108, a pulse stretcher 110, inverters 114 and 122, a single shot 116. 124, delays 118 and 120, latches 112 and 126, voltage regulator 128, and two speed clock 130.

The overall operation of the system 100 is as follows. Transition detector 104, active state input 106, OR gate 108, pulse stretcher 110 sense the signal transition to active to cause the half-sleep mode of circuit 102 to be released and for a predetermined period of time. When inactive, provides a signal to return circuit 102 to half-sleep mode. Voltage regulator 128 changes the source-to-body bias of the transistors in circuit 102, increasing the bias during inactivity to reduce sub-threaded current loss. The two-speed clock 130 adjusts the clock speed of the circuit 102 to reduce the clock speed when the circuit 102 enters a half-sleep mode and to increase to a normal speed during periods of high activity. Inverters 114 and 122, single shots 116 and 124, delayers 118 and 120, and latches 112 and 126 control the sequence of operations. Specifically, when circuit 102 enters a half dormant mode, they cause the clock speed to lower first before the source-to-body bias is increased. Similarly, when the half-sleep mode of the circuit is released, they first reduce the source-to-body bias before the clock speed is increased to normal speed.

The circuit 102 may include any type of device for which power savings are desired while in the inactive state, while normal functionality should be readily available. As such, the circuit 102 may be a system chip, microprocessor, microcontroller, application specific integrated circuits (ASICs), digital signal processors (DSPs), or power consumption and immediate functionality. It can include any other circuitry used in the device. Thus, a preferred embodiment of the present invention is characterized by a long period of inactivity in which cellular phones, personal digital assistants (PDAs) and their interactions are normally interrupted by active active states where the user needs immediate normal function or desires. It is particularly applicable to battery-powered equipment like other devices.

In a preferred embodiment of the present invention, by adjusting the source-to-body voltage of the transistors in circuit 102 and adjusting the clock speed of circuit 102, circuit 102 enters or enters a half-sleep mode. Get out of it. Referring to FIG. 2, two exemplary p-channel transistors 202 and 204 and two exemplary n-channel transistors 206 and 208 are schematically illustrated. In most conventional CMOS circuits, the source-to-body voltage bias of n- and p-channel devices is zero. Typically, the body of every n-channel transistor is directly connected to its source and V _ss , while the body of every p-channel transistor is directly connected to its source and V _dd . This is illustrated for the p channel transistor 202 and the n channel transistor 206.

In a preferred embodiment of the present invention, the transistors in circuit 102 are in normal mode (ie, source-to-body bias (V _SB ) is zero) and half-sleep mode (ie, source-to-body bias (V). _SB ) is wired up so that it can operate in the In half-sleep mode, the source-to-body voltage (V _SB ) is increased to reduce power consumption during periods of inactivity. This is illustrated with p-channel transistor 204 and n-channel transistor 208. Instead of connecting the body and source together to V _dd in the p-channel transistor, the body is connected to V _{t_p so} that the body can be driven at a voltage higher than V _dd by a predetermined amount in the period of inactivity. In the example shown in FIG. 2, the body of the p-channel transistor 204 is driven at a voltage of 300 mV high that is greater than or equal to V _dd , thus V _SB becomes -300 mV. Similarly, instead of connecting the body and source together to V _SS in the n-channel transistor, the body is connected to V _{t_n} so that it can be driven at a predetermined amount lower than V _SS in the inactive period. In the example shown in FIG. 2, the body is driven at a voltage 300 mV lower than V _SS and thus V _SB becomes 300 mV. By increasing the bias between the body and the source, the transistor's sub-threshold current is greatly reduced in the period of inactivity.

During the active period, V _{t_p} can be set to V _dd so that V _SB becomes zero so that the p-channel transistors can operate at normal speed. Similarly, V _{t_n} can be set to V _SS so that V _SB becomes zero so that the n channel transistor can operate at normal speed.

The amount of bias (V _SB ) applied between the body and the source during the inactive period is preferably selected in consideration of various factors. Typically, it is desirable to increase V _SB taking into account the time taken when the half-sleep mode is released and the decrease in sub-threadhold current. As an example, a preferred V _SB of 300 mV will typically reduce the sub-threaded current by about one hundredth without excessively increasing the time it takes to exit from the half-sleep mode.

Referring to FIG. 3, the graph shows the n channel drain current I _D versus the gate voltage V _G in an example transistor with a source-to-body bias of 0 mV and 300 mV. This graph shows how the drain current decreases over the entire operating range as the source-to-body bias increases. The upper part of the curve (part where I _D is greater than 10 ⁻⁶ ) shows the drain current when the transistor is active or on. The lower part of the curve (the part where I _D is less than 10 ⁻⁶ ) shows the drain current when the transistor is inactive or off. The current flowing through the transistor in the off state is generally referred to as sub-threaded current. All transistors in an integrated circuit device have some amount of sub-threaded current flowing in the period of inactivity. The sub-threadhold current is typically several hundred times smaller than the current flowing when the transistor is on. The sub-threaded current is small enough not to be considered in many applications. However, in some applications, such as small cell powered devices, the accumulation of sub-threaded currents lost by each transistor results in significant power consumption during periods of inactivity.

As shown in FIG. 3, by increasing V _SB , the transistor enters half-sleep mode and the sub-threadhold current is greatly reduced in the inactive period. 3 shows the case where the n channel drain current is V _SB = 0 mV and V _SB = 300 mV. In this example, the drain current, in particular the sub-threshold current, for the transistor with V _SB = 300 mV is reduced by about 100 times. Accordingly, power consumption is greatly reduced in the inactive period.

Referring again to FIG. 1, the preferred half-sleep mode mechanism may cause circuit 102 to enter half-sleep mode by adjusting the source-to-body voltage of the transistors in circuit 102 and by adjusting the clock speed of circuit 102. It can also be used to get out of half-sleep mode. In the normal mode, V _SB = 0 mV and the two-speed clock 130 is set to operate the transistor at normal speed. In half dormant mode, V _SB in the n and p devices increases, consuming much lower sub-threaded current and the two-speed clock 130 is set to operate at lower speeds.

The transition detector 104 is connected to monitor a predetermined output of the circuit 102. Preferably, transition detector 104 is connected to an output having a signal transition indicative of an active state on circuit 102 where circuit 102 preferably exits half-sleep mode. The output of the transition detector 104 is connected to the pulse stretcher 110 via an OR gate 108. Accordingly, the pulse stretcher 110 receives the set input through the OR gate 108 when the signal transition is detected by any transition detector 104.

In addition to monitoring the output of the circuit 102 with the transition detector 104, one or more active state inputs 106 may also be connected to the pulse stretcher 110 through the OR gate 108. Active state input 106 may include any signal type that indicates an active state in which circuit 102 is desired to exit from half-sleep mode. As such, active state input 106 may include a memory access signal, a control signal, a data valid signal, or any other signal indicative of a future active state in a particular application.

Thus, if a transition occurs that represents an active state in the circuit 102 (from the output of the transition detector 104 or the active state input 106), the pulse stretcher 110 is set via the OR gate 108. Receive the input. In a preferred embodiment of the present invention, pulse stretcher 110 extends the width of the output pulse over a predetermined time period, starting from the leading end of the output pulse of OR gate 108. Thus, the output of pulse stretcher 110 will be active for a predetermined time whenever there is a signal transition indicative of an active state. The amount of time the pulse stretcher 110 extends the active signal will vary depending on the particular application. Specifically, the amount of extension time will be chosen to extend the signal long enough so that the circuit 102 does not enter the half-sleep mode during very short periods of inactivity (eg one inactivity clock cycle). Conversely, the amount of extension time is so great that the extension time will not be chosen to waste power by operating circuit 102 too long in normal mode. For example, it is generally desirable to extend the signal between 10 and 100 clock cycles by the pulse stretcher 110.

The output of pulse stretcher 110 controls whether circuit 102 is in half-sleep mode or normal mode. When the pulse stretcher 110 goes low in output, the clock speed of the circuit 102 is reduced to a lower speed by the two-speed clock 130 and then the circuit 102 by the voltage regulator 128. Increasing the source-to-body bias in c) causes circuit 102 to enter half-sleep mode. When the output of the pulse stretcher 110 becomes high, after the source-to-body bias of the transistors in the circuit 102 is reduced by the voltage regulator 128, the clock speed of the circuit 102 is 2- The speed clock 130 is changed to the normal operating speed.

Specifically, when the output of pulse stretcher 110 becomes high, voltage regulator 128 causes the source-to-body bias to decrease to zero for both n-channel and p-channel transistors in circuit 102. The latch 112 is set. This is preferably done by providing a voltage V _{t_p} equal to V _dd to the p channel device body and a voltage V _{t_n} equal to V _SS to the n channel device body. The pulse stretcher 110 output passes through a single short 124 and a delay 120 to set the latch 126 to change the two-speed clock to operate at normal high speed. This delay 120 is preferably provided to ensure that the two-speed clock 130 switches at high speed only after the source-to-body bias has stabilized to zero. This gives the transistor in circuit 102 the ability to operate at high speed before the high speed clock is activated. The single short 116 is preferably included in the delay path to provide the latch 112 with a well defined short reset pulse that will not interfere with subsequent pulses from the pulse stretcher 110. It should be noted that preferably the circuit 102 operation is slower only in the first few cycles, which typically will not be detectable by any user.

When circuit 102 is inactive for a predetermined time, pulse stretcher 110 output goes low. Inverter 122 reverses this transition and resets latch 126. This changes the two-speed clock to a lower half-sleep mode speed. The pulse stretcher 110 output is also inverted by the inverter 114 and applied to a single shot 116, which generates a short pulse. After passing through delay 118, a single short 116 pulse resets latch 112, causing voltage regulator 128 to increase the source-to-body bias voltage. This is preferably done by providing a voltage V _{t_p} to the body of the p-channel device by a predetermined amount greater than V _dd and a voltage V _{t_n} to a body of the n-channel device by a predetermined amount less than V _SS . For example, applying V _{t_p} , 300 mV higher than V _dd , to a p channel device produces V _SB of -300 mV. _Applying V _{t_n} , 300 mV lower than V _SS , to the n-channel device produces V _SB of 300 mV.

Delay 118 is preferably provided to ensure that the source-to-body bias is increased only after the two-speed clock 130 output has stabilized at a low rate. This is done because increasing the source-to-body bias increases the threadhold voltage and slows the device down. The source-to-body bias is increased only after the two-speed clock 130 has stabilized at low speeds, thereby eliminating the need for transistors with degraded performance to operate at high speed clocks. The single short 124 is preferably included in the delay path to provide the latch 126 with a well defined short set pulse that will not interfere with subsequent pulses from the pulse stretcher 110.

Thus, if an active state is detected within circuit 102, circuit 102 exits the half-sleep mode by changing the source-to-body bias to zero and then changing the operating clock speed to a normal normal speed. If the circuit 102 is inactive for a predetermined time, the source-to-body bias is increased after the operating clock speed is lowered to reduce the sub-threaded current.

Referring to FIG. 4, cross-sectional views of an n-channel transistor 404 and a p-channel transistor 406 formed in a semiconductor substrate 402 are shown. In a preferred embodiment of the invention, the source-to-body bias of the transistor is increased using body contacts. Specifically, the source-to-body bias of the n channel transistor is increased by applying a voltage V _{t_n} to the body of the n channel device using a contact such as contact 410. As mentioned above, this is preferably done by applying a voltage V _{t_n} lower than V _SS applied to the n-channel source contact, such as contact 412, to the body contact. Similarly, the source-to-body bias of the p channel transistor is increased by applying a voltage V _{t_p} to the body of the p channel device using a body contact such as contact 420. As mentioned above, this is preferably done by applying a voltage V _{t_p} higher than V _dd applied to the p-channel source contact, such as contact 422, to the body contact.

When the transistor is operating in normal mode, V _{t_n} applied to contact 410 is set to V _SS and V _{t_p} applied to contact 420 is set to V _dd , resulting in a source-to-body bias of zero. .

It will be appreciated that the preferred embodiment of the present invention has the advantage of being easily implemented in standard CMOS technology. Specifically, in most conventional CMOS technologies, all n-channel transistor sources and bodies are connected to Vss together. Likewise, all p-channel transistor sources and bodies are connected together at V _dd . To implement a preferred embodiment of the present invention, all n channel sources remain connected to V _SS together and all n channel bodies can be connected together to V _{t_n} . Likewise, all of the p channel sources remain connected to V _dd together and all p channel bodies can be connected together to V _{t_p} . Thus, the bias of all n-channel transistor bodies is adjusted together and the bias of all p-channel transistor bodies is adjusted together. This requires the use of standard CMOS techniques as opposed to other techniques that require separate transistor threshold adjustments and require isolated body structures such as those found in silicon-on-insulator (SOI) techniques. It will be possible to implement a preferred embodiment of the present invention.

Of course, in other embodiments, it may be desirable to adjust the source-to-body bias for only a portion of the multiple devices on the chip. In this case, a mechanism will be needed to isolate the portion that will enter half-sleep mode from the rest of the chip. This can be implemented using any type of SOI technique. In addition, this may be accomplished using bulk CMOS formed in multiple wells. An example of such an implementation is disclosed in US patent application Ser. No. 08 / 866,674, entitled "Method of Forming Self-Aligned Halo-Isolated Wells," filed May 30, 1997, which is incorporated by IBM in International Business Machines Corporation, which is hereby incorporated by reference. This patent application discloses a method for forming a self-aligned double well structure, which can be used to implement the present invention when only a portion of the device needs to enter a half dormant mode. Typically, CMOS techniques could not be used in substrate-divided applications because of the difficulty of isolating transistors that would share a common substrate voltage if the substrates were not separated. However, using the solutions provided in the aforementioned patent applications, implementations of the novel invention can be made.

While the invention has been described and described in detail with reference to specific embodiments thereof, those skilled in the art will recognize that various modifications may be made to form and detail within the spirit and scope of the invention. Also, although various conductors are shown in the figures as a single line, they are not so shown in a limited sense, and it will also be understood that these conductors may include multiple conductors as would be apparent to one skilled in the art. Those skilled in the art will also appreciate that the present invention can be applied to other isolation techniques (e.g. LOCOS, recessed oxide (ROX), etc.), well and substrate techniques, dopant types, energy and species. There will be. It will also be appreciated that the spirit of the present invention is applicable to other semiconductor technologies (eg BiCMOS, bipolar, SOI, silicon germanium (SiGe)).

According to the present invention, in a semiconductor device, during a period of inactivity, the device or part of the device enters a half-sleep mode, thereby reducing power consumption while maintaining normal functioning, but having the ability to react immediately if necessary, to quickly operate at a normal operating speed. An apparatus and method for reducing power consumption are provided.

Claims (34)

An apparatus for reducing power consumption in a circuit having an operating clock speed and a plurality of transistors, the apparatus comprising: A clock rate adjustment mechanism that reduces the operating clock speed of the circuit and maintains the operation of the circuit at a reduced clock rate when the circuit is inactive for a predetermined time; A source-to-body voltage regulation mechanism that increases the source-to-body voltage of the plurality of transistors after the operating clock speed is reduced Power consumption reduction device comprising a. The method of claim 1, And when the circuit is active, the source-to-body voltage regulation mechanism reduces the source-to-body voltage of the plurality of transistors. The method of claim 2, And when the circuit is active, the source-to-body voltage regulation mechanism reduces the source-to-body voltage and then the clock rate adjustment mechanism increases the operating clock speed. The method of claim 1, And the source-to-body voltage regulation mechanism further comprises a voltage regulator providing a first voltage to the n-channel transistor body and a second voltage to the p-channel transistor body. The method of claim 3, wherein The source-to-body voltage regulation mechanism is configured to supply a voltage equal to the source voltage of the n channel transistor body to the n channel transistor body and a voltage equal to the source voltage of the p channel transistor body to the p channel transistor body. Power consumption reduction device to reduce source-to-body voltage. The method of claim 1, The clock rate adjustment mechanism includes a clock capable of providing a clock signal at a first clock rate and the reduced clock rate, the first clock rate being set when the source-to-body voltage of the transistor is zero; And a faster clock speed for operating the circuit, wherein the reduced clock speed includes a slower clock speed for operating the circuit when the source-to-body voltage of the transistor is increased. The method of claim 1, And an active state sensing mechanism coupled to the circuit for sensing when the circuit is active. The method of claim 7, wherein The active state detection mechanism provides an active state signal when the circuit is active, and continuously provides the active state signal for a predetermined time after the circuit is no longer active. The method of claim 7, wherein The active state detection mechanism includes a plurality of transition detectors and pulse stretchers, the plurality of transition detectors coupled to a plurality of outputs of the circuit to detect when the circuit is active, and the plurality of transition detectors A power consumption reduction device coupled to the pulse stretcher and providing a signal when the pulse stretcher detects that it is active by the transition detector and provides a signal for a predetermined time thereafter. The method of claim 9, A first latch having a set input and a reset input, the first latch receiving a pulse expander output as the set input and receiving a complement of a delayed pulse expander output as the reset input; And a power consumption reduction device for outputting a signal to the source-to-body voltage regulation mechanism. The method of claim 10, A second latch having a set input and a reset input, wherein the second latch receives an inverted value of a pulse stretcher output as the reset input, receives a delayed pulse expander output as the set input, the clock Power consumption reduction device that outputs a signal with a speed regulation mechanism. delete delete A device for reducing power consumption in a circuit having an operating clock speed and a plurality of transistors, A clock rate adjustment that reduces the operating clock speed of the circuit and maintains the operation of the circuit at a reduced clock rate when the circuit is inactive for a predetermined time, and increases the operating clock speed when the circuit is active Mechanism, If the circuit is inactive for a predetermined time, the operating clock speed is decreased and then the source-to-body voltage of the plurality of transistors is increased, and if the circuit is active before the operating clock speed is increased. And a source-to-body voltage regulation mechanism that reduces the source-to-body voltage of the plurality of transistors. The method of claim 14, The source-to-body voltage regulation mechanism further includes a voltage regulator, the voltage regulator providing a first voltage to the n-channel transistor body and a second voltage to the p-channel transistor body, wherein the source-to-body When the voltage decreases, the first voltage is substantially equal to the source voltage of the n-channel transistor, and the second voltage is substantially equal to the source voltage of the p-channel transistor, and when the source-to-body voltage is increased, And a first voltage is higher than said source voltage of said n-channel transistor and said second voltage is lower than said source voltage of said p-channel transistor. The method of claim 15, When the source-to-body voltage is increased, the first voltage is about 200 to 500 mV higher than the source voltage of the n-channel transistor, and the second voltage is about 200 to 500 higher than the source voltage of the p-channel transistor. Power saving device as low as mV. The method of claim 15, When the source-to-body voltage is increased, the first voltage is higher than the source voltage of the n-channel transistor by an amount selected to reduce the sub-thread current to less than about one hundredth, and the source-to-body The second voltage is lower than the source voltage of the p-channel transistor by an amount selected to reduce the sub-thread current to less than about one hundredth as the body voltage increases. The method of claim 14, An active state sensing mechanism for sensing when the circuit is active, wherein the active state sensing mechanism is active for a predetermined time when the circuit is active and after the circuit is no longer active Power consumption reduction device that provides a signal. The method of claim 18, The active state detection mechanism includes a plurality of transition detectors and pulse stretchers, the plurality of transition detectors coupled to a plurality of outputs of the circuit to detect when the circuit is active, and the plurality of transition detectors And coupled to the pulse stretcher to provide a signal when an active state is detected by the transition detector and for a predetermined time thereafter. The method of claim 19, A first latch having a set input and a reset input and a second latch having a set input and a reset input, The first latch receives a pulse expander output as the set input, receives an inverted value of the delayed pulse expander output as the reset input, outputs a signal to control the source-to-body voltage regulation mechanism, And the second latch receives a pulse expander output inverted value as the reset input, receives a delayed pulse expander output as the set input, and outputs a signal to the clock speed adjustment mechanism. delete delete A method of reducing power consumption during an inactive state in a circuit having an operating clock speed and a plurality of transistors, Reducing the operating clock speed of the circuit and maintaining the operation of the circuit at a reduced clock speed when the circuit is inactive for a predetermined time; Increasing the source-to-body voltage of the plurality of transistors after the operating clock speed is reduced Power consumption reduction method comprising a. The method of claim 23, Reducing the source-to-body voltage of the plurality of transistors when the circuit is active again. The method of claim 24, Increasing the operating clock speed after reducing the source-to-body voltage of the plurality of transistors when the circuit is active again. The method of claim 23, Increasing the source-to-body voltage of the plurality of transistors comprises providing a first voltage to an n-channel transistor body and providing a second voltage to a p-channel transistor body. The method of claim 26, Wherein the first voltage comprises a voltage higher than the source voltage of the n-channel transistor, and wherein the second voltage comprises a voltage lower than the source voltage of the p-channel transistor body. The method of claim 24, The step of reducing the source-to-body voltage of the plurality of transistors provides a voltage to the n-channel transistor body that is substantially equal to the source voltage of the n-channel transistor, and is substantially equal to the source voltage of the p-channel transistor. Providing a p-channel transistor body. The method of claim 23, The step of reducing the operating clock speed of the circuit when the circuit is inactive for a predetermined time includes monitoring the output of the circuit for transition and the output of the circuit is inactive for a predetermined time. Providing an inactive signal if The method of claim 29, Providing an inactive signal comprises inputting a signal to a pulse stretcher when a transition is detected at the output of the circuit. The method of claim 30, Setting a first latch by the output of the pulse stretcher and resetting by a delayed pulse stretcher output inversion value; Setting a second latch by the delayed output of the pulse stretcher and resetting by a pulse stretcher output inversion value Power consumption reduction method further comprising. The method of claim 23, Reducing the clock rate comprises providing a clock capable of providing a clock signal at a first clock rate and the reduced clock rate, the first clock rate being the source-to-count of the transistor. A faster clock speed for operating the circuit when the body voltage is zero, and the reduced clock speed includes a slower clock speed for operating the circuit when the source-to-body voltage of the transistor is increased. How to reduce power consumption. A method for reducing power consumption while maintaining full functionality in an inactive period in a circuit having an operating clock speed, a plurality of n channel transistors, and a plurality of p channel transistors, the method comprising: Reducing the operating clock speed of the circuit and maintaining the operation of the circuit at a reduced clock speed when the circuit is inactive for a predetermined time; Increasing the body voltage of the n-channel transistor and decreasing the body voltage of the p-channel transistor after the operating clock speed is reduced; When the circuit becomes active again, the body voltage of the n channel transistor is reduced to be substantially equal to the source voltage of the n channel transistor and the body voltage of the p channel transistor is substantially equal to the source voltage of the p channel transistor. Increasing to be equal to, Increasing the operating clock speed after the body voltage of the n-channel transistor is decreased and the body voltage of the p-channel transistor is increased when the circuit becomes active again. Power consumption reduction method comprising a. The method of claim 33, wherein The step of reducing the operating clock speed of the circuit when the circuit is inactive for a predetermined time includes monitoring the output of the circuit for a transition and an inactive state signal when the circuit is inactive for a predetermined time. Providing a step of reducing power consumption.