KR100367778B1 - Processor module redundancy - Google Patents

Abstract

The present invention relates to a processor module redundancy apparatus.

The present invention makes it possible to directly access the system memory when the input / output processor on the system bus side accesses the processor module side system memory in the operation mode, thereby improving the efficiency of use of the processor bus inside the processor module in the operation mode. In addition, the microprocessor of the processor module in the operation mode does not have to participate in the system memory access of the input / output processor of the system bus, thereby reducing the load on the microprocessor of the processor module in the operation mode. In addition, since the processor bus monitoring unit monitors the data writing and reading operations of the microprocessor and duplicates the data on the standby processor module side, the processor bus monitoring unit must be changed and designed when the type of the microprocessor is changed. Although there are disadvantages, the present invention performs the data redundancy function by monitoring data input and output to the system memory by the memory monitoring unit, and thus the data duplication function can be performed regardless of the type of microprocessor included in the processor module. There is also.

Description

Processor module redundancy

The present invention relates to a processor module redundancy apparatus, and more particularly, when an input / output processor on the system bus side accesses the processor module side system memory in an operation mode, the system memory is directly accessed to the processor bus inside the processor module in the operation mode. The present invention relates to a processor module redundancy device for increasing the efficiency of use and reducing the load on the microprocessor of the processor module in the operating mode.

In general, in a system requiring continuous operation such as an exchange system, various processor modules are duplicated to prevent operation interruption. In such a processor module redundancy device, one processor module is operated in an operation mode and the other processor module is operated in a standby mode to perform a redundancy operation. If an abnormality occurs in the processor module in the operation mode while performing the operation of storing simultaneously, the processor module in the standby mode is switched to the operation mode and continuously processes the data to prevent duplication of the system.

The conventional processor module redundancy apparatus is constructed as shown in FIG. That is, the processor module redundancy device is composed of two processor modules having the same configuration, one is operated in the operation mode and the other is in the standby mode, Figure 1 is an operation mode processor module and standby mode processor module Shown separately. In Figure 1, the processor module in the operation mode includes a microprocessor 10, a processor bus monitor 11, a FIFO controller 12, FIFOs 13 and 14, a memory controller 15, a system memory 16 and a system bus. The interface unit 17 is provided. The microprocessor 10 executes application programs based on an operating system to perform arithmetic processing, and the system memory 16 stores an operating system and application programs and stores data necessary for arithmetic processing of the microprocessor 10. . The memory controller 15 manages the access of the system memory 16 according to the access request from the microprocessor 10, and the system interface unit 17 is an input / output processor (not shown in the drawing) connected to the system bus. ) And the processor bus. In addition, the processor bus monitoring unit 11 monitors the processor bus and latches the data and address at this time if the microprocessor 10 needs to duplicate the data when the system memory 16 approaches the system memory to record the data. To the FIFOs 13 and 14. The FIFO control unit 12 requests the use of the processor bus to the bus arbitration unit 20 side of the standby mode processor module according to the status information of the FIFOs 13 and 14 and controls the FIFOs 13 and 14 when the use is permitted. The redundant data is stored in the system memory 22 of the standby processor module. In the processor module in the standby mode, the system memory 22 maintains the data identity by storing data applied from the operation mode processor, and the memory controller 21 controls the data writing operation to the system memory 22. The bus arbitration unit 20 arbitrates the microprocessor of the standby processor module and the processor bus usage of the FIFO control unit 12.

The operation of the processor module duplexing device configured as described above is as follows.

When the microprocessor 10 performs a data write operation to the system memory 16 through the memory control unit 15, the processor bus monitor 11 outputs signals necessary for the data, address, and memory write operation generated at this time. 13, 14). The FIFOs 13 and 14 inform the FIFO control unit 12 of the current state of the real time in real time, and the FIFO control unit 12 displays the bus intermediation unit of the standby mode processor module when the FIFOs 13 and 14 are not empty. 20) requires the processor bus of the standby processor module to be used. At that time, the bus arbitration unit 20 arbitrates the use of the processor bus in accordance with the processor bus license request of the standby processor module side microprocessor and the operation mode processor module side FIFO control unit 12, by the bus arbitration unit 20. If the use of the processor bus on the standby mode processor module side is permitted, the FIFO control unit 12 performs a data write operation to the system memory 22 through the memory control unit 21 on the standby mode processor module side. In this way, the system memory 16 on the operation mode processor module side and the system memory 22 on the standby mode processor module maintain the sameness of data in real time to prepare for redundancy switching.

However, in the above-described conventional processor module duplication apparatus, the input / output processor connected to the system bus does not have direct access to the system memory 16, but has its own input / output temporary storage device, causing the microprocessor 10 to input / output for By reading the temporary storage device and writing data to the system memory 16 or having the microprocessor write the data read from the system memory 16 into the temporary memory for input / output, the system memory 16 can be read through the temporary memory for input / output. In this case, the microprocessor 10 is always involved in accessing the system memory 16 of the system bus-side input / output processor, thereby increasing the load of the microprocessor 10 to lower the data processing speed of the microprocessor 10, Microprocessor (10) is the system bus side input and output processor As involved in the system memory 16 access, there is a problem that the microprocessor 10 has been used frequently to the processor bus for a purpose other than the data processing necessary for the operation performed in its lowered use efficiency of the processor bus.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and when the input / output processor on the system bus side accesses the processor module side system memory in the operation mode, the processor module directly accesses the system memory in the operation mode. The purpose of the present invention is to increase the usage efficiency of the processor bus and reduce the load on the microprocessor of the processor module in the operating mode.

In order to achieve the above object, a feature of the present invention is to provide a processor module redundancy apparatus, wherein a system memory access request is applied through a processor bus from a microprocessor included in an operation mode processor module, and a system is accessed from a system bus side input / output processor. A memory controller configured to control an access operation to the system memory according to a system memory access request applied through the bus interface unit; A memory monitoring unit for monitoring an access operation to the system memory and outputting an address, a plurality of control signals, and a FIFO input control signal corresponding to data to be redundant; An address FIFO for receiving and storing an address and a plurality of control signals applied from the memory monitoring unit according to the FIFO input control signal from the memory monitoring unit; A data FIFO for receiving and storing data recorded in the system memory according to a FIFO input control signal from the memory monitoring unit; And a FIFO controller for controlling the data FIFO and the address FIFO to output the contents of the data FIFO and the address FIFO to the standby mode processor module.

1 is a block diagram of a conventional processor module redundancy apparatus.

2 is a block diagram of a processor module duplication apparatus according to the present invention;

3 is a configuration diagram of a memory monitoring unit shown in FIG. 2;

4 is a timing diagram illustrating single-bit and multi-bit access in the present invention.

Explanation of symbols on the main parts of the drawings

30: microprocessor 31: FIFO control unit

32: data FIFO 33: address FIFO

34: memory controller 35: system memory

36: memory monitoring unit 37: system bus interface unit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The processor module duplication apparatus according to the present invention is configured as shown in FIG. In other words, the processor module duplexing device is composed of two processor modules having the same configuration, one is operated in the operation mode and the other is in the standby mode, Figure 2 is an operation mode processor module and standby mode processor module Shown separately. In FIG. 2, the processor module in the operation mode includes a microprocessor 30, a FIFO control unit 31, a data FIFO 32, an address FIFO 33, a memory control unit 34, a system memory 35, and a memory monitoring unit 36. ) And a system bus interface unit 37. The microprocessor 30 executes application programs based on an operating system to perform arithmetic processing, and the system memory 35 stores an operating system and application programs and stores data necessary for arithmetic processing of the microprocessor 30. . The memory control unit 34 controls the system memory 35 according to an access request applied from the microprocessor 30 and an access request applied from the system bus side input / output processor (not shown) through the system bus interface 37. In order to control access to the system bus interface unit 37, the I / O processor connected to the system bus and the processor bus interface. In addition, the memory monitoring unit 36 monitors data write operations of the microprocessor 30 and the system bus interface unit 37 with respect to the system memory 35 and stores data, addresses, and other information to be duplicated. The data is stored in the data FIFO 32 and the address and other information are stored in the address FIFO 33. The FIFO control unit 31 requests the use of the processor bus to the bus arbitration unit 40 side of the standby mode processor module according to the status information of the data FIFO 32 and the address FIFO 33, and when the use is permitted, the data FIFO 32 ) And the address FIFO 33 are stored to store the data to be duplicated in the system memory 42 of the standby mode processor module. In the processor module in the standby mode, the system memory 42 maintains the sameness of data by storing data applied from the operation mode processor, and the memory controller 41 controls the data write operation to the system memory 42. The bus arbitration unit 40 arbitrates the processor bus usage of the standby mode processor module side microprocessor and the operation mode processor module side FIFO control unit 31.

On the other hand, the memory monitoring unit 36, as shown in Figure 3, the upper address reproducing means (a), the middle address reproducing means (b), the lower address reproducing means (c), the access size reproducing means (d), multi-bit Detecting means (e) and FIFO input control means (f). The upper address reproducing means (a) applies the upper address reproduced by encoding the row address strobe signal (RAS; Row Address Strobe) applied from the memory control unit 34 to the system memory 35 to the address FIFO 33 side. The median address reproducing means b applies the median address reproduced by demultiplexing the multiplexed address applied from the memory control section 34 to the system memory 35 to the address FIFO 33 side. The lower address reproducing means c applies the lower address reproduced by encoding the column address strobe signal (CAS) applied from the memory control unit 34 to the system memory 35 to the address FIFO 33 side. The access size reproducing means d encodes an access size signal indicating a recording byte unit reproduced by encoding and processing the column address strobe signal CAS applied from the memory control unit 34 to the system memory 35. Is applied to the side. The multi-bit detection means (e) analyzes the row address strobe signal (RAS) and the column address strobe signal (CAS) applied from the memory controller 34 to the system memory 35 side, and records data on the system memory 35. Whether the single-bit write or multi-bit write is distinguished, the corresponding write discrimination signal is applied to the address FIFO 33 side, and the FIFO input control means f is applied from the memory control unit 34 to the system memory 35 side. The input control signal generated according to the row address strobe signal RAS, the column address strobe signal CAS, and the write enable signal WREN is applied to the data FIFO 32 and the address FIFO 33 side, and the data FIFO 32 is applied. And information input of the address FIFO 33.

The present invention configured to have the above functions operates as follows.

The memory controller 34 of the operation mode processor module receives a system memory access request from the microprocessor 30 and a system memory access request applied through the system bus interface 37 from a system bus side input / output processor. The processor 30 requests access to the memory controller 34 through the processor bus to write and read data to and from the system memory 35. The system bus input / output processor controls the memory controller through the system bus interface 37. An access request is made to the (34) side, and data is written to and read from the system memory 35.

When the data write and read operation is performed on the system memory 35 by the memory control unit 34 as described above, the memory monitoring unit 36 receives an address and control information applied from the memory control unit 34 to the system memory 35. The data, address, and other information to be reproduced and duplicated are stored in the data FIFO 32 and the address FIFO 33. The row address strobe signal RAS and the column applied from the memory control unit 34 to the system memory 35 side are stored. In response to the address strobe signal CAS and the write enable signal WREN, the input control signal generated by the FIFO input control means f is applied to the data FIFO 32 and the address FIFO 33 side, and the data FIFO 32 is applied. And the information input to the address FIFO 33, the upper address reproduced by the upper address reproducing means (a), the middle address reproduced by the middle address reproducing means (b), and the lower address regeneration number. The lower address reproduced by step (c), the access size signal reproduced by the access size reproducing means (d), and the write classification signal detected by the multi-bit detecting means (e) are stored in the address FIFO 33; The data applied to the system memory 35 from the memory control unit 34 is stored in the data FIFO 32.

At this time, the FIFO control unit 31 requests the use of the processor bus to the bus arbitration unit 40 side of the standby mode processor module with the state information of the data FIFO 32 and the address FIFO 33. Accordingly, when the bus arbitration unit 40 arbitrates the processor bus license request of the microprocessor of the standby mode processor module and the FIFO control unit 31 of the operation mode processor module, and grants the bus license to the FIFO control unit 31, the operation mode The processor module side FIFO control unit 31 controls the data FIFO 32 and the address FIFO 33 to output data, addresses and other information to perform a data write operation to the system memory 42 through the memory control unit 41. To perform.

On the other hand, the memory control unit 34 writes the data in the system memory 35 in a single bit or multi-bit. Accordingly, the memory monitoring unit 36 outputs the storage information of the data FIFO 32 and the address FIFO 33 by the FIFO control unit 31 occupying the processor bus of the standby mode module. When performing the data write operation to 42), the single bit and the multi bit are detected in order to be able to write in a single bit or multi bit correspondingly, and the multi bit detecting means (e) of the memory monitoring unit 36 The operation of detecting single bit and multi bit is performed as shown in FIG. That is, when the multi-bit detecting means (e) detects a single bit, as shown in Fig. 4A, the single-bit column address strobe signal CAS is applied while the row address strobe signal RAS is valid. When outputting a low-level signal MB indicating that it is not multi-bit, and the multi-bit detecting means e detects the multi-bit, as shown in Fig. 4B, the row address straw signal RAS When the multi-bit column address strobe signal CAS is applied in a valid state, the high-level signal MB indicating multi-bit is output, thereby storing the corresponding signal MB in the address FIFO 33 to standby mode processor module. When performing the data write operation to the side system memory 42, it is possible to write in single-bit or multi-bit correspondingly.

As described above, the present invention directly accesses the system memory when the input / output processor on the system bus side accesses the processor module side system memory in the operation mode, and thus the efficiency of use of the processor bus inside the processor module in the operation mode. In this case, the microprocessor of the processor module in the operating mode does not have to participate in the system memory access of the input / output processor of the system bus, thereby reducing the load on the microprocessor of the processor module in the operating mode. In addition, since the processor bus monitoring unit monitors the data writing and reading operations of the microprocessor and duplicates the data on the standby processor module side, the processor bus monitoring unit must be changed and designed when the type of the microprocessor is changed. Although there are disadvantages, the present invention performs the data redundancy function by monitoring data input and output to the system memory by the memory monitoring unit, and thus the data duplication function can be performed regardless of the type of microprocessor included in the processor module. There is also.

Claims (2)

A processor module redundancy device, Operation mode The access operation to the system memory is performed according to the system memory access request applied from the microprocessor included in the processor module through the processor bus and the system memory access request applied from the system bus input / output processor through the system bus interface unit. A memory controller for controlling; A memory monitoring unit for monitoring an access operation to the system memory and outputting an address, a plurality of control signals, and a FIFO input control signal corresponding to data to be redundant; An address FIFO for receiving and storing an address and a plurality of control signals applied from the memory monitoring unit according to the FIFO input control signal from the memory monitoring unit; A data FIFO for receiving and storing data recorded in the system memory according to a FIFO input control signal from the memory monitoring unit; And a FIFO controller for controlling the data FIFO and the address FIFO to output the contents of the data FIFO and the address FIFO to a standby mode processor module. The method of claim 1, The memory monitoring unit comprises: upper address reproducing means for outputting, to the address FIFO side, an upper address that is encoded and reproduced by a row address strobe signal applied from a memory controller to a system memory; Median address reproducing means for outputting the median address reproduced by demultiplexing the multiplexed address applied from the memory controller to the system memory to the address FIFO side; Lower address reproducing means for outputting, to the address FIFO side, a lower address reproduced by encoding a column address strobe signal applied from the memory control unit to a system memory; Access size reproducing means for outputting, to the address FIFO side, an access size signal indicating a recording byte unit encoded by the column address strobe signal applied to the system memory from the memory control unit; Analyzing the row address strobe signal and the column address strobe signal applied from the memory controller to the system memory side to distinguish whether the data write to the system memory is a single bit write or a multi bit write, and write the corresponding write distinguishing signal to the address FIFO side. Multi-bit detection means for outputting; A FIFO input control means for outputting a FIFO input control signal generated according to a row address strobe signal, a column address strobe signal, and a write enable signal from the memory controller to the system memory side to the data FIFO and the address FIFO side; Processor module redundancy device, characterized in that.