KR100366946B1 - Plasma Display Panel - Google Patents

Abstract

An object of the present invention is to provide a plasma display panel capable of suppressing an increase in voltage applied to an address electrode in a plasma display panel having a high partition wall.

According to the present invention, a plasma display panel includes: a plurality of address electrodes formed on a lower substrate corresponding to an upper substrate in a direction intersecting a scan / sustain electrode, a common sustain electrode, and a trigger electrode pair; A lower dielectric layer formed on the address electrode; A phosphor layer is formed on the lower dielectric layer so that a portion of the lower dielectric layer is exposed so that the voltage supplied to the address electrode is lowered.

The present invention can suppress an increase in address voltage generated by exposing the address electrode to the discharge space to increase the height of the barrier rib formed on the lower substrate.

Description

Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel capable of suppressing an increase in voltage applied to an address electrode in a plasma display panel having a high partition wall.

Plasma Display Panel (hereinafter referred to as "PDP") and Liquid Crystal Display Device (hereinafter referred to as "LCD") are spotlighted as next generation display devices having the highest practicality among flat panel display devices. In particular, PDP has higher brightness and wider reagent angle than LCD, and its application is wide as a thin, large display such as an outdoor advertising tower, wall-mounted TV, or theater display.

The plasma display panel emits phosphors by 147 nm ultraviolet rays generated when the He + Xe or Ne + Xe gas is discharged to display images including characters or graphics. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. These PDPs are largely classified into a DC drive method and an AC drive method. Unlike the DC driving method, the PDP of the AC driving method is attracting more attention as a display device because of the advantages of low voltage driving and long life by using a dielectric. The PDP is driven by a plurality of discharge cells arranged in a matrix, and one discharge cell forms one pixel of the screen.

1 is a view showing a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 1, a discharge cell of a three-electrode PDP includes a scan / sustain electrode 5 and a common sustain electrode 8 formed on the upper substrate 2, and an address electrode formed on the lower substrate 4. 16). The scan / sustain electrode 5 and the common sustain electrode 8 are composed of transparent electrodes 4,7 and bus electrodes 3,6. The upper dielectric layer 10 and the protective layer 12 are stacked on the upper substrate 2 having the scan / sustain electrode 5 and the common sustain electrode 8 side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 10. The protective layer 12 prevents damage to the upper dielectric layer 10 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective layer 12, magnesium oxide (MgO) is usually used. The lower dielectric layer 18 and the partition wall 20 are formed on the lower substrate 14 on which the address electrode 16 is formed, and the phosphor layers (red, green, blue) 22 are formed on the lower dielectric layer 18 and the partition wall 20. ) Is applied. The address electrode 16 is formed in a direction crossing the scan / sustain electrode 5 and the common sustain electrode 8. The partition wall 20 is formed in parallel with the address electrode 16 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 22 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space 24 provided between the upper and lower plates 15 and 17 and the partition wall.

Briefly describing the light emission process, in order to initialize all the discharge cells of the panel, a reset pulse is supplied to the scan / sustain electrode 5 of all the discharge cells so that reset discharge occurs. In the reset discharge, wall charges are generated for each discharge cell, thereby lowering the discharge voltage required for the subsequent address discharge. Then, a scan pulse is supplied to the scan / sustain electrode 5, and a data pulse is applied to the address electrode 16 in synchronization with the scan / sustain electrode 5 so that an address discharge occurs between the two electrodes, so that wall charges are applied to the upper and lower dielectric layers 10 and 18. Is formed. In the cells selected by the address discharge, a sustain discharge occurs between the two electrodes by an alternating current signal alternately supplied to the scan / sustain electrode 5 and the common sustain electrode 8. At this time, in the discharge space 24, vacuum ultraviolet rays are generated in the process of transition after the discharge gas is excited. The generated vacuum ultraviolet rays excite the mold 22 to generate visible light, thereby realizing an image of the PDP.

However, in the conventional three-electrode PDP, since the sustain discharge between the scan / sustain electrode 5 and the common sustain electrode 8 causing the sustain discharge occurs only at the center of the discharge cell, the space of the discharge cell was not sufficiently utilized. Accordingly, there is a problem that the luminance of the discharge cells is lowered and the luminous efficiency is lowered. In order to solve this problem, the scan / sustain electrode 5 and the common sustain electrode 8 which cause a sustain discharge are provided at both edges of the discharge cell or the width of the discharge electrode is widened. However, when the distance between the scan / sustain electrode 5 and the common sustain electrode 8 increases, the discharge voltage increases, and when the width of the discharge electrode is widened, the discharge current increases and power consumption increases.

In order to solve this problem, a 5-electrode AC surface discharge type PDP has been developed and commercialized as shown in FIG. 2.

2 is a perspective view showing a 5-electrode AC surface discharge type PDP.

Referring to FIG. 2, the discharge cell of the 5-electrode PDP includes a scan / sustain electrode 5, a common sustain electrode 8, and trigger electrode pairs 30 and 36 on the upper substrate 2 and a lower substrate. On the 14, an address electrode 16 is provided. The trigger electrode pairs 30 and 36 are composed of transparent electrodes 4, 7, 28, 34 and bus electrodes 3, 6, 26, 32. The upper substrate having the trigger electrode pairs 30 and 36 arranged in parallel at a narrow interval between the scan / sustain electrode 5 and the common sustain electrode 8, and having the electrodes 5, 8, 30, and 36 formed therein. 2) an upper dielectric layer 10 and a protective layer 12 are stacked. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 10. The protective layer 12 prevents damage to the upper dielectric layer 10 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective layer 12, magnesium oxide (MgO) is usually used. The lower dielectric layer 18 and the partition wall 20 are formed on the lower substrate 14 on which the address electrode 16 is formed, and the phosphor layer 22 is coated on the surfaces of the lower dielectric layer 18 and the partition wall 20. The address electrode 16 is formed in a direction crossing the scan / sustain electrode 5, the common sustain electrode 8, and the trigger electrode pairs 30 and 36. The partition wall 20 is formed in parallel with the address electrode 16 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 22 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space 24 provided between the upper and lower plates 1 and 13 and the partition wall 20.

Briefly describing the light emission process, a reset pulse is applied to one of the scan / sustain electrode 5 or the trigger electrode pairs 30 and 36 disposed inside all the discharge cells in order to initialize all the discharge cells of the panel. Supplied, a reset discharge occurs. During the reset discharge, wall charges are generated for each discharge cell to lower the discharge voltage required for the subsequent address discharge. Then, a scan pulse is supplied to the scan / sustain electrode 5, and a data pulse is applied to the address electrode 16 in synchronization with the scan / sustain electrode 5 so that an address discharge occurs between the two electrodes, so that wall charges are applied to the upper and lower dielectric layers 10 and 18. Is formed. In the discharge cells selected by the address discharge, the trigger electrode pairs 30 and 36 provided between the scan / sustain electrode 5 and the common sustain electrode 8 respond to an auxiliary discharge in response to the trigger pulse voltage, which is an AC pulse voltage, during the sustain period. Causes Immediately after the auxiliary discharge occurs, sustain pulses are supplied to the scan / sustain electrode 5 and the common sustain electrode 8. Then, the scan / sustain electrode 5 and the common sustain electrode 8 can generate a discharge in the center part of the cell by the wall charge accumulated in the discharge cell by the auxiliary discharge and the voltage difference due to the sustain pulse. Such sustain discharge is continuously generated by the sustain pulse and the trigger pulse.

As described above, the 5-electrode AC surface discharge type PDP can obtain a higher discharge efficiency than the 3-electrode AC surface discharge type PDP. On the other hand, as a method of increasing the discharge efficiency, there is a method of increasing the height of the partition wall formed on the lower plate and increasing the discharge area by increasing the phosphor coating area. However, when the height of the barrier rib formed on the lower plate is increased, the gap between the address electrode and the scan / sustain electrode is widened, which causes a problem of increasing the address voltage applied to the address electrode.

Accordingly, an object of the present invention is to provide a plasma display panel capable of suppressing an increase in voltage applied to an address electrode in a plasma display panel in which a partition wall is set high.

1 is a perspective view showing a conventional three-electrode plasma display panel.

2 is a perspective view showing a five-electrode plasma display panel;

3 is a cross-sectional view showing a discharge cell structure of a five-electrode plasma display panel according to a first embodiment of the present invention;

4 is a cross-sectional view showing a discharge cell structure of a five-electrode plasma display panel according to a second embodiment of the present invention;

5 is a cross-sectional view illustrating a discharge cell structure of a 5-electrode plasma display panel according to a third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1, 15: top plate 2: upper board

3, 6, 26, 32, 38, 46, 52, 58: metal bus electrode

4, 7, 28, 34, 40, 42, 48, 54, 60, 62: transparent electrode

5, 44: scan / sustain electrode 30, 36, 50, 56: trigger electrode

8, 64: common sustain electrode 12: protective layer

10: upper dielectric layer 13, 17: lower plate

14: lower substrate 16: address electrode

18: lower dielectric layer 20: partition wall

22, 40, 41, 42: phosphor 24: discharge space

In order to achieve the above object, a plasma display panel includes a plurality of address electrodes formed on a lower substrate corresponding to an upper substrate in a direction intersecting a scan / sustain electrode, a common sustain electrode, and a trigger electrode pair; A lower dielectric layer formed on the address electrode; A phosphor layer is formed on the lower dielectric layer so that a portion of the lower dielectric layer is exposed so that the voltage supplied to the address electrode is lowered.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 4.

3 is a cross-sectional view of a five-electrode plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 3, first, a five-electrode plasma display panel according to the present invention includes scan / sustain electrodes 5, common sustain electrodes 8, and trigger electrode pairs 30 and 36 on an upper substrate 2. In addition, an address electrode 16 is provided on the lower substrate 1. The trigger electrode pairs 30 and 36 are composed of a transparent electrode 9 and a bus electrode 11. The upper substrate having the trigger electrode pairs 30 and 36 arranged in parallel at a narrow interval between the scan / sustain electrode 5 and the common sustain electrode 8, and having the electrodes 5, 8, 30, and 36 formed therein. 2) an upper dielectric layer 10 and a protective layer 12 are stacked. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 10. The protective layer 12 prevents damage to the upper dielectric layer 10 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective layer 12, magnesium oxide (MgO) is usually used. The lower dielectric layer 18 and the partition wall 20 are formed on the lower substrate 1 on which the address electrode 16 is formed, and the red, blue, or green phosphor layer 40 is formed on the lower dielectric layer 18 and the partition wall 20. Is applied. In this case, the phosphor layer 40 is not coated on a portion of the lower dielectric layer 18 overlapping the address electrode 16, such as a portion "A". That is, the red, blue, or green phosphor layer 40 is formed between the scan / sustain electrode 5, the common sustain electrode 8, and the trigger electrode pairs 30 and 36 on the upper substrate 2 and the lower substrate 1; Is formed to expose the lower dielectric layer 18 at the intersection with the address electrode 16. In other words, a portion of the lower dielectric layer 18 is formed with a groove A in which the phosphor layer 40 is not formed. That is, part of the lower dielectric layer 18 is exposed by the groove A. By doing so, it is possible to minimize the influence of the resistance that the charges emitted from the address electrode 16 during the driving are present in the phosphor layer 40. The address electrode 16 is formed in a direction crossing the scan / sustain electrode 5, the common sustain electrode 8, and the trigger electrode pairs 30 and 36. The partition wall 20 is formed in parallel with the address electrode 16 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 40 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space 24 provided between the upper and lower substrates 2 and 1 and the partition wall 20.

4 is a cross-sectional view of a five-electrode plasma display panel according to a second embodiment of the present invention.

Referring to FIG. 4, first, a five-electrode plasma display panel according to the present invention includes a scan / sustain electrode 5, a common sustain electrode 8, and trigger electrode pairs 30 and 36 on an upper substrate 2. In addition, an address electrode 16 is provided on the lower substrate 1. The trigger electrode pairs 30 and 36 are composed of a transparent electrode 9 and a bus electrode 11. The upper substrate having the trigger electrode pairs 30 and 36 arranged in parallel at a narrow interval between the scan / sustain electrode 5 and the common sustain electrode 8, and having the electrodes 5, 8, 30, and 36 formed therein. 2) an upper dielectric layer 10 and a protective layer 12 are stacked. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 10. The protective layer 12 prevents damage to the upper dielectric layer 10 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective layer 12, magnesium oxide (MgO) is usually used. The lower dielectric layer 18 and the partition wall 20 are formed on the lower substrate 1 on which the address electrode 16 is formed, and the red, blue, or green phosphor layer 40 is formed on the lower dielectric layer 18 and the partition wall 20. Is applied. In this case, the phosphor layer 40 and the lower dielectric layer 18 are not coated to expose a portion of the region overlapping the address electrode 16, such as a portion “B”. In other words, the red, blue, or green phosphor layer 40 and the lower dielectric layer 18 are interposed between the scan / sustain electrode 5, the common sustain electrode 8, and the trigger electrode pairs 30 and 36 on the upper substrate 2. The intersection region between the region of and the address electrode 16 on the lower substrate 1 is exposed. That is, a portion of the address electrode 16 is formed with a groove B in which the phosphor layer 40 and the lower dielectric layer 18 are not formed. That is, part of the address electrode 16 is exposed by the groove B. By doing so, it is possible to minimize the influence of the electric charges emitted from the address electrode 16 during the driving in the phosphor layer 40 and the lower dielectric layer 18. The address electrode 16 is formed in a direction crossing the scan / sustain electrode 5, the common sustain electrode 8, and the trigger electrode pairs 30 and 36. The partition wall 20 is formed in parallel with the address electrode 16 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 40 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space 24 provided between the upper and lower substrates 2 and 1 and the partition wall 20.

In addition, the discharge cells of the conventional PDP in which the phosphor layer covers the entirety of the address electrode have a phenomenon in which the discharge voltage applied to the discharge region between the lower electrode and the upper electrode is lowered by the capacitance included in the phosphor layer. At this time, the capacitance of the phosphor layer is determined by the dielectric constant inherent to the phosphor material and the thickness of the phosphor layer. Therefore, if the thicknesses of the phosphor layers applied to the PDP discharge cells are all the same, the capacitance of each discharge cell is changed by the dielectric constant inherent to each phosphor material (red, blue, green). However, since the intrinsic dielectric constant of each phosphor material (red, blue, green) is a fixed constant, the discharge voltage applied to the discharge region can be reduced by controlling the thickness of the phosphor layer on which the discharge cells are applied. In other words, as shown in FIG. 5, the thickness W of each phosphor layer applied to face the address electrode may be adjusted to decrease the discharge voltage applied to the discharge region.

As described above, the plasma display panel according to the present invention can suppress the increase in the address voltage caused by increasing the height of the partition wall formed on the lower substrate by exposing the address electrode to the discharge space.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

A plasma display panel comprising: a plurality of scan / sustain electrodes and common sustain electrodes formed on an upper substrate, and a plurality of trigger electrode pairs formed between the scan / sustain electrodes and a common sustain electrode; A plurality of address electrodes formed on the lower substrate corresponding to the upper substrate in a direction crossing the scan / sustain electrode, the common sustain electrode, and the trigger electrode pair; A lower dielectric layer formed on the address electrode; And a phosphor layer formed on the lower dielectric layer to expose a portion of the lower dielectric layer so that the voltage supplied to the address electrode is lowered. The method of claim 1, And the lower dielectric layer is formed to expose a portion of the lower dielectric layer so that the voltage supplied to the address electrode is lowered. The method of claim 2, And the lower dielectric layer is formed to expose an area between the scan / sustain electrode, the common sustain electrode and the trigger electrode and an overlapping area with the address electrode. The method of claim 1, And the phosphor layer is formed such that an area between the scan / sustain electrode, the common sustain electrode and the trigger electrode and an overlapping area with the address electrode are exposed.