KR100363674B1 - Apparatus and Method Of Driving Plasma Display Panel In High Speed - Google Patents

Abstract

The present invention relates to a plasma display panel which is suitable for high speed driving while reducing the number of electrodes.

The plasma display panel according to the present invention is connected to the discharge cells in common, and before selecting the discharge cell, a common priming electrode for generating an auxiliary discharge with any one of the sustain electrode pairs, and one of the common priming electrode and the sustain electrode pairs. And a visible light blocking layer for blocking visible light generated in a discharge space therebetween.

Plasma display panel according to the present invention is suitable for high-resolution panel because it can be driven at a high speed while reducing the number of electrodes compared to the conventional plasma display panel in which the auxiliary electrode pair for generating an auxiliary discharge is installed.

Description

Apparatus and Method Of Driving Plasma Display Panel In High Speed}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel which is suitable for high speed driving while reducing the number of electrodes. The present invention also relates to a driving apparatus and a method for driving a plasma display panel at high speed.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP is formed on a scan / sustain electrode 30Y and a common sustain electrode 30Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. Each of the scan / sustain electrode 30Y and the common sustain electrode 30Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and is formed on one edge of the transparent electrode. (13Y, 13Z). The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 30Y and the common sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 30Y and the common sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

Such a driving method of the PDP is roughly classified into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted by the address discharge in the address period.

The selective write method supplies a reset pulse having a very high voltage level in the reset period to all the discharge cells in order to make all the discharge cells 1 the same discharge condition before supplying the data pulse and the scan pulse at the same time. This will cause a reset discharge. At this time, the decay time of the space charge generated in the discharge cells does not exceed 30-40 μs, as experimentally found, and thus does not contribute significantly to the address discharge. Therefore, in the selective write method, since the address discharge does not occur uniformly within a short time, the pulse width of the scan pulse for scanning each scan line should be 3 μs or more. Because of this long scan time, the selective writing method lacks or does not have time that can be allocated to the sustain period at high resolutions, where there are many scan lines.

In contrast, in the selective erasing method, writing discharge is caused to the discharge cells of all scan lines before generating the address discharge. Therefore, since a large amount of wall charges are accumulated in the discharge cell, address discharge can occur even by a short address pulse. In practice, in the selective erasing method, the data pulse and the scan pulse for generating the address discharge are only about 1 s. However, the selective erasing method has a disadvantage in that light emission occurs for the discharge cells of the entire scan lines before the address period of every subfield, so that light emission occurs several times even in the non-display period. This has been pointed out as a cause of suppressing the contrast by increasing the black level of the image.

The applicant of the present application has proposed a PDP that can be driven at high speed and minimize the contrast through the previously-applied Korean patent application "99-42121". In this PDP, the display discharge cell 43 and the auxiliary discharge cell 42 are provided in the discharge cell 44. The auxiliary discharge cells 41 are disposed between the display discharge cells 43. The auxiliary discharge cells 41 are formed with a black matrix 42. This auxiliary discharge cells 41 is provided with the scan / sustain electrode lines (Y _N-1, Y _N) of the secondary to the scan electrode line (AY _N, AY _{N + 1)} connected to, and the common sustain electrode lines (Z) And common auxiliary electrode lines AZ disposed between the auxiliary scan electrode lines A Y _N and A Y _{N +1} . The auxiliary scan electrode lines A Y _N and A Y _{N + 1} and the common auxiliary electrode lines AZ cause a reset discharge in the reset period, and the auxiliary discharge cells 41 together with the address discharge of the previous scan line in the address period. By generating a secondary discharge within the), space charge is supplied to the display discharge cells 43 of the next scanning line. Since space charges are supplied in advance from the auxiliary discharge cells 41 included in the previous scan line, sufficient space charges are provided in the display discharge cells 1, so that the pulse widths of the scan pulse and the data pulse during the address discharge are 1 μs or less. Can be reduced. In addition, since visible light generated in the auxiliary discharge cells 41 due to the reset discharge and the auxiliary discharge in the address period is absorbed by the black matrix 42, the contrast can be increased.

However, the discharged cells 44 are inevitably large because the four PDPs have to be formed on the upper substrate 10 for each scan line. As a result, in a high-resolution panel in which the size of the discharge cells is reduced and the pitch between the discharge cells is narrowed, the space for forming four electrode lines in the discharge cells is restricted. That is, since four electrode lines should be formed only on the upper substrate 10, a space for forming electrodes is insufficient in the high resolution panel.

Accordingly, it is an object of the present invention to provide a PDP that is suitable for high speed driving while reducing the number of electrodes.

Another object of the present invention is to provide an apparatus and method for driving a PDP suitable for high speed driving.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a plan view showing an electrode structure of another conventional plasma display panel.

3 is a diagram illustrating a plasma display panel and its driving units according to an exemplary embodiment of the present invention.

4 is a plan view showing in detail the electrode structure of the plasma display panel shown in FIG.

5 is a driving waveform diagram of a plasma display panel according to an embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor 30Y: scan / sustain electrode

30Z: common sustain electrode 41: auxiliary discharge cell

42,62: Black matrix 43: display discharge cell

44,51: discharge cell 52: scan / sustain drive unit

54: common sustain driver 56A, 56B: address driver

In order to achieve the above objects, the PDP according to the present invention is commonly connected to the discharge cells and common priming electrode, common priming electrode and sustain for causing auxiliary discharge with any one of the sustain electrode pairs before selecting the discharge cell. And a visible light blocking layer for blocking visible light generated in a discharge space between any one of the electrode pairs.

According to an aspect of the present invention, there is provided a driving apparatus of a PDP, including: a display panel including an address electrode to which data is supplied, a sustain electrode pair crossing the address electrode, and a common priming electrode connected to the discharge cells; A priming electrode driver for supplying a predetermined level of DC voltage to the common priming electrode during the address period; While the scan driver is supplied to any one of the sustain electrode pairs and the scan driver for supplying scan pulses of opposite polarity to one of the sustain electrode pairs while the voltage level on the priming electrode is maintained at a predetermined level. An address driver is provided to supply a data pulse of opposite polarity to the scan pulse.

A method of driving a PDP according to the present invention includes supplying a predetermined level of DC voltage to a common priming electrode commonly connected to discharge cells during an address period, and a sustain electrode for a period in which a voltage level on the common priming electrode is maintained at a predetermined level. Supplying a scan pulse having a DC voltage and a reverse polarity to any one of the pairs, and supplying a scan pulse and a data having a reverse polarity to the address electrode while the scan pulse is supplied to any one of the sustain electrode pairs. .

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 5.

Referring to FIG. 3, a PDP according to the present invention crosses a common priming electrode Pcom, address electrode lines X1 to Xn, scan / sustain electrode lines Y1 to Ym, and a common sustain electrode line Z. M x n discharge cells 51 arranged in a matrix form. The common priming electrode line Pcom is formed between the common sustain electrode line Z and the scan / sustain electrode lines Y1 to Ym included in adjacent scan lines. The common priming electrode line Pcom generates auxiliary discharge together with the scan / sustain electrode lines Y1 to Ym. The space charge generated by the auxiliary discharge increases the internal voltage in the discharge cells 51 during the address discharge, thereby lowering the voltage levels of external voltages (data pulses and scan pulses) supplied from the outside during the address discharge. The black matrix 62 is formed in the auxiliary discharge space between the common priming electrode line Pcom and the scan / sustain electrode lines Y1 to Ym. The black matrix 62 serves to absorb visible light generated by the secondary discharge. The address electrode lines X1 to Xn are divided into odd and even numbers, and data pulses are supplied from the first and second address drivers 56A and 56B. The scan / sustain electrode lines Y1 to Ym cause auxiliary discharges to the common priming electrode lines Pcom and address discharges to the address electrode lines X1 to Xn. To this end, scan pulses are sequentially supplied from the scan / sustain driver 52 to the scan / sustain electrode lines Y1 to Ym. The scan / sustain electrode lines Y1 to Ym generate sustain discharge along with the common sustain electrode line Z according to the sustain pulses from the scan / sustain driver 52. The common sustain electrode line Z is supplied from the common sustain driver 54 with a sustain pulse alternated with the sustain pulse supplied to the scan / sustain electrode lines Y1 to Ym.

5 is a driving waveform diagram illustrating a high speed driving method of a PDP according to the present invention.

Referring to FIG. 5, a common level DC voltage is supplied to the common priming electrode line Pcom in an address period. Scan pulses are supplied to the scan / sustain electrode lines Y1 to Ym- _1N-1 , and sustain pulses are supplied during the sustain period.

First, the reset pulse RSTP is supplied to the common priming electrode line Pcom at a point in time of the reset period. Then, the discharge cells 51 included in all scan lines are reset and discharged by the voltage difference between the common priming electrode line Pcom and the scan / sustain electrode lines Y1 to Ym. At this time, visible light generated in the discharge space between the common priming electrode line Pcom and the scan / sustain electrode lines Y1 to Ym is absorbed by the black matrix 62. Then, at time point b, the stabilization pulse STP is supplied to the scan / sustain electrode lines Y1 to Ym. As the micro discharges occur in the discharge cells 51 by the stabilization pulse STP, wall charges and space charges are formed. At time c, the positive ramp wave RAMP is supplied to the scan / sustain electrode lines Y1 to Ym, and the negative ramp wave -RAMP is supplied to the common priming electrode line Pcom. By the ramp waves RAMP and -RAMP, wall charges and space charges are accumulated in a discharge space between the scan / sustain electrode lines Y1 to Ym and the common priming electrode line Pcom. When the stabilization pulse STP and the ramp waves RAMP and -RAMP are supplied to the common priming electrode line Pcom and the scan / sustain electrode lines Y1 to Ym, a uniform amount of walls are applied to all the discharge cells 51. Charges and space charges accumulate to facilitate secondary discharge in the address period.

At the point d at which the address period begins, a predetermined level of the DC voltage DC is supplied to the common priming electrode line Pcom, and a negative scan pulse (−) is applied to the first scan / sustain electrode line Y1. SCP1) is supplied. At this time, an auxiliary discharge occurs between these electrodes Pcom and Y1 due to the voltage difference between the common priming electrode line Pcom and the first scan / sustain electrode line Y1. The secondary discharge generates wall charges and space charges in all of the discharge cells 51 included in the first scan line. Subsequently, the data pulse DP is supplied to the address electrode lines X1 to Xn at the time e at which the voltage on the first scan / sustain electrode line Y1 maintains the negative scan pulse (-SCP) level. At this time, the address discharge is caused by the internal voltage of the discharge cell 51 caused by the wall charge and the space charge generated by the auxiliary discharge and by the data pulse DP and scan pulse (-SCP1) supplied from the outside. 51 is selected. The wall charges and the space charges generated by the auxiliary discharges reduce the scanning time of the first scan line to 1 μs or less. In other words, the secondary discharge provides a priming effect on the address discharge. Subsequently, a negative scan pulse (-SCP) is supplied to the second scan / sustain electrode line Y2 at time f, and the voltage on the address electrode lines X1 to Xn is changed to the ground level. Accordingly, an auxiliary discharge occurs between these electrodes Pcom and Y2 due to the voltage difference between the common priming electrode line Pcom and the second scan / sustain electrode line Y2. When the voltage on the second scan / sustain electrode line Y2 maintains the negative scan pulse (-SCP2) level, the data pulse DP is supplied to the address electrode lines X1 to Xn to generate an address discharge. . As such, address discharge is sequentially generated for all scan lines by using an auxiliary discharge generated by a voltage difference between the common priming electrode line Pcom and the scan / sustain electrode lines Y1 to Ym during the data non-application period. The scan pulses (-SCP1 to -SCPm) sequentially supplied to the scan / sustain electrode lines (Y1 to Ym) convert the voltage on the scan / sustain electrode lines (Y1 to Ym) at a negative polarity during auxiliary discharge and address discharge. It has a pulse width larger than the data pulse DP to maintain the level. Therefore, since the address discharge occurs during the period in which the data pulse is supplied using the auxiliary discharge, scanning of one scan line is completed in a period shorter than the pulse width of the scan pulse (-SCP to -SCPm).

In the sustain period, the voltage on the common priming electrode line Pcom maintains the ground level GND. In this sustain period, the sustain pulse SSUS is supplied to the scan / sustain electrode lines Y1 to Ym and the common sustain electrode line Z. Then, the discharge cells 51 selected by the address discharge are caused by the sustain pulse SSUS alternately supplied to the scan / sustain electrode lines Y1 to Ym and the common sustain electrode line Z. At the time when the sustain period is completed, the erase pulse EP is supplied to the common sustain electrode line Z to erase the sustain discharge.

On the other hand, the common priming electrode line (Pcom) may be driven only by a switch element for switching the DC voltage without being driven by an integrated circuit (IC).

As described above, the PDP according to the present invention is provided with a common priming electrode line in the discharge cell in order to cause an auxiliary discharge to facilitate the address discharge prior to the address discharge, and reduces the address period by using the auxiliary discharge. Accordingly, the PDP according to the present invention is suitable for a high resolution panel because the number of electrodes can be reduced and the high-speed driving can be performed in comparison with a conventional PDP in which an auxiliary electrode pair for generating an auxiliary discharge is installed. The driving apparatus and method of the PDP according to the present invention can drive the PDP at high speed by reducing the address period by accumulating wall charges and space charges in the discharge cells prior to the address discharge to provide a priming effect on the address discharge. In addition, the driving apparatus and method of the PDP according to the present invention can prevent contrast suppression due to light emission occurring in a non-display period by installing a black matrix on the auxiliary discharge space to block visible light generated in the auxiliary space.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A plasma display panel in which discharge cells are arranged in a matrix at an intersection of an address electrode to which data is supplied and a sustain electrode pair intersecting the address electrode. A common priming electrode connected to the discharge cells in common and for generating an auxiliary discharge together with any one of the sustain electrode pairs before selecting the discharge cell; And a visible light blocking layer for blocking visible light generated in a discharge space between any one of the common priming electrode and the sustain electrode pair. The method of claim 1, And the common priming electrode causes the auxiliary discharge together with a scan / sustain electrode to which scan pulses are supplied from the sustain electrode pairs. An apparatus for driving a plasma display panel divided into a reset period for initializing discharge cells, an address period for selecting the discharge cells, and a sustain period for displaying the selected discharge cells, the apparatus comprising: A display panel having an address electrode to which data is supplied, a sustain electrode pair crossing the address electrode, and a common priming electrode connected to the discharge cells in common; A priming electrode driver for supplying a DC voltage of a predetermined level to the common priming electrode during the address period; A scan driver for supplying a scan pulse of opposite polarity to the DC voltage to any one of the sustain electrode pairs while the voltage level on the priming electrode is maintained at the predetermined level; And an address driver for supplying data pulses having a polarity opposite to that of the scan pulse to the address electrode while the scan pulse is supplied to any one of the sustain electrode pairs. The method of claim 3, wherein And the data pulse is supplied to the address electrode to be delayed by a predetermined delay value with respect to the scan pulse. A reset period for initializing the discharge cells, a reset period for initializing the discharge cells, and a plasma display panel having a discharge electrode provided at an intersection of the address electrode to which data is supplied, the sustain electrode pair crossing the address electrode, and the sustain electrode pair; A method for driving by dividing into an address period and a sustain period for displaying the selected discharge cells, Supplying a DC voltage of a predetermined level to a common priming electrode commonly connected to the discharge cells during the address period; Supplying a scan pulse of opposite polarity to the DC voltage to any one of the sustain electrode pairs while the voltage level on the common priming electrode maintains the predetermined level; And supplying a data pulse having a polarity opposite to that of the scan pulse to the address electrode while the scan pulse is supplied to any one of the sustain electrode pairs. The method of claim 5, And the data pulse is supplied to the address electrode to be delayed by a predetermined delay value with respect to the scan pulse. The method of claim 5, And a data non-application period exists for a predetermined time between the data pulses. The method of claim 5, And the pulse width of said data pulse is shorter than that of said scan pulse. delete delete delete delete delete