KR100363480B1 - Auto precharge control circuit - Google Patents

Abstract

The auto precharge control circuit of the present invention is an external control signal in a semiconductor memory device composed of a plurality of banks that perform auto precharge in order to ensure the specification of the pulse width parameter tRAS of a lath signal during auto precharge. Oscillation means controlled by; A delay control circuit comprising a plurality of shift means controlled by an output signal of the oscillation means; And an auto precharge control means controlled by an output signal of the delay control circuit and an external control signal to output an auto precharge control signal for controlling the auto precharge operation, which is stable at any cascade and burst length. You can perform the operation.

Description

Auto precharge control circuit

The present invention relates to an auto precharge control circuit, and more particularly, to an auto precharge control circuit capable of stably operating a memory chip by determining a precharge period suitable for CAS latency and burst length. It is about.

In general, when a semiconductor memory device terminates a burst operation of a read operation or a write operation, the semiconductor memory device immediately precharges an active bank. This precharge operation is performed by an auto precharge command. The automatic precharging of a bank that was active during a read or write operation is called auto precharge.

When the CAS latency and burst length is "1" during auto precharge (CL1, BL1) When auto precharge is performed by the auto precharge command, the pulse width of the RAS signal (RAS) The specification of the parameter tRAS cannot be met.

Therefore, in the related art, a delay circuit is used to adjust the pulse width parameter tRAS of the lath signal.

However, this method has a problem that a malfunction may occur because the operation speed of the semiconductor memory device is slow and the precharge timing suitable for the cascade and burst length cannot be accurately set.

An object of the present invention for solving such a problem is to provide an auto precharge for controlling the semiconductor memory device to operate stably by securing the pulse width parameter of the lath signal to suit the cascade latency and burst length during auto precharge. It is to provide a control circuit.

1 is a block diagram showing an auto precharge control circuit of the present invention.

FIG. 2 is a detailed block diagram of the auto precharge delay unit in the block diagram of FIG. 1; FIG.

3 is a detailed circuit diagram of an auto precharge oscillator in the block diagram of FIG. 2;

4 is a detailed circuit diagram of an auto delay unit in the block diagram of FIG. 2;

5 is a detailed circuit diagram of an auto precharge control unit in the block diagram of FIG. 1;

FIG. 6 is a detailed circuit diagram showing another embodiment of the auto precharge oscillator in the block diagram of FIG. 2; FIG.

<Explanation of Signs of Major Parts of Drawings>

100: auto precharge delay unit

200: auto precharge control unit

110: auto precharge oscillator

121-124: Auto delay unit

111: Lars active signal combination unit

112: delay control signal combination unit

113: oscillation control unit

OSC: Oscillator

DEL, DEL11, DEL21: Delay

LAT, LAT1, LAT2, LAT11, LAT21: Latch

The auto precharge control circuit of the present invention for achieving the above object,

In a semiconductor memory device composed of a plurality of banks to perform auto precharge,

Oscillation means controlled by an external control signal;

A delay control circuit comprising a plurality of shift means controlled by an output signal of the oscillation means; And

And an auto precharge control means for outputting an auto precharge control signal controlled by the output signal of the delay control circuit and an external control signal to control the auto precharge operation.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of an auto precharge control circuit of the present invention. Here, an example of a semiconductor memory device composed of four banks will be described. As shown in FIG. 2, a pulse signal generated when a bank active command is input, and a low level pulse is input when a ras active signal (RASATV <0: 3>) used for each bank and a precharge command or an auto precharge command are input. An auto precharge delay unit 100 that receives a lath precharge control signal RASPCG <0: 3> used for each bank and outputs a delay control signal DELAY <0: 3>, where The delay control signal DELAY <0: 3> is a level signal that is enabled after being delayed by the pulse width tRAS of the lath signal after the bank active command is input. Delay control signal DELAY <0: 3> of the auto precharge delay unit 100, an auto precharge control signal (AUTOPCG <0: 3>) generated by an auto precharge command, and used for each bank, and Including a pre-charge control signal (RASPCG <0: 3>), and outputs the auto precharge start signal (AUTOPCGST <0: 3>) to the auto precharge control unit 200 for controlling to perform auto precharge; It is composed.

FIG. 2 is a detailed block diagram of the auto precharge delay unit 100 in the block diagram of FIG. 1, and as shown therein, an active signal (the output signal of the first to fourth auto delay units 121-124). ACTB <0: 3>) and delay control signals DELAY <0: 3> are fed back, and the first to fourth auto delay units 121 to 124 are inputted with the ras active signal RRASTV <0: 3>. Auto precharge oscillator 110 for outputting shift control signals (SHIFT, SHIFTB), shift control signals (SHIFT, SHIFTB) and lath precharge control signals (RASPCG) of the auto precharge oscillator 110 <0: 3> and the first to second outputting the active signal ACTB <0: 3> and the delay control signal DELAY <0: 3> by receiving the ras active signal RRASTV <0: 3> Four auto delay parts 121-124 are comprised.

FIG. 3 is a detailed circuit diagram of the auto precharge oscillator 110 in the block diagram of FIG. 2, and as shown therein, a noah gate NOR that noarses each ras active signal RRASTV <0: 3>. A rath active signal combination unit 111 including an inverter INV which outputs the combined rath active signal RASATVSUM by inverting the output of the NOR gate NOR; First to fourth NOR gates NOR1 to NOR4 that Noarize the active signal ACTB <0: 3> and the delay control signal DELAY <0: 3>, respectively, and the first to fourth NOR gates Delay comprising a fifth NOR gate (NOR5) for renormalizing the output signals of NOR1-NOR4 and an inverter (INV1) for outputting the combined delay control signal (DELAYBNOR) by inverting the output signal of the fifth NOR gate. Control signal combination unit 112; And a PMOS transistor (PM) and an NMOS transistor (NM) connected in series between a power supply voltage and a ground voltage, to which the combined ras active signal (RASATVSUM) and the combined delay control signal (DELAYBNOR) are applied, respectively, to a gate. A latch portion composed of a first inverter INV11 and a second inverter INV12 interconnected with an input and an output to latch a node potential of a common connected drain of the PMOS transistor PM and the NMOS transistor NM. An oscillation control section 113 composed of LAT and an oscillation section OSC oscillating in accordance with the oscillation enable signal OSCEN of the oscillation control section 113 to output shift control signals SHIFT and SHIFTB. Here, the oscillator OSC non-inverts the NAND gate ND to which the oscillation enable signal OSCEN and the shift control signal SHIFTB are fed back to NAND and outputs the NAND gate ND. The delay unit DEL including the third to eighth inverters INV13 to INV18 outputting the shift control signal SHIFTB, and the output signal SHIFTB of the delay unit DEL are inverted to shift the shift control signal SHIFT. It is configured to include a ninth inverter (INV19) for outputting.

The combined ras active signal RRASTVSUM is used as an enable signal of the oscillator 113, and the combined delay control signal DELAYBNOR is used as a disable signal of the oscillator 113.

4 is a detailed circuit diagram of each auto precharge delay unit 121-124 in the block diagram of FIG. 2, as shown in FIG. 4, in which a lath precharge control signal is connected to a gate in series between a power supply voltage and a ground voltage. Output from PMOS transistor PM1 and NMOS transistor NM1 to which RASPCG and Ras active signal RASATV are applied, and a common connected drain of PMOS transistor PM1 and NMOS transistor NM1, respectively. To latch the active signal ACTB, a latch portion LAT1 composed of first and second inverters INV21 and INV22 interconnected with an input and an output, and a signal latched by the latch portion LAT1 The precharge control signal RASPCG is reset by the signal INIT inverted by the third inverter INV23, controlled by the shift control signals SHIFT and SHIFTB, and sequentially shifted to thereby delay the delay control signal DELAY. Outputting the first to seventh shift units ST1-ST7 It is configured to hereinafter. Here, each of the shift units ST1 to ST7 transmits a data input signal selectively controlled by the transfer gate TG, which is controlled by the shift control signals SHIFT and SHIFTB, and selectively transmitted. A latch part LAT2 composed of fourth and fifth inverters INV24 and INV25 interconnected with an input and an output for latching the received signal, and a signal output by inverting the signal latched by the latch part LAT2. The sixth inverter INV26 outputs a signal, a drain is connected to an input terminal of the latch portion LAT2, a source is connected to a ground voltage, and the lath precharge control signal RASPCG is connected to a gate of the third inverter INV23. Is configured to include a second NMOS transistor NM2 that is applied by the inverted signal INIT and is controlled to reset the shift unit.

FIG. 5 is a detailed circuit diagram of the auto precharge control unit 200 in the block diagram of FIG. 1, as shown in FIG. 1, in which a Lars precharge control signal (RASPCG) and an auto are connected to a gate in series between a supply voltage and a ground voltage. The first PMOS transistor PM11 and the first NMOS transistor NM11 to which the precharge control signal AUTOTOPG is applied, and the first PMOS transistor PM11 and the first NMOS transistor NM11 are common to each other. In order to latch the potential of the connected drain, a latch part LAT11 composed of the first and second inverters INV31 and INV32 having a common input and an output connected thereto, and a gate connected in common between the power supply voltage and the ground voltage. And a third NMOS transistor PM12 to which a signal latched by the latch unit LAT11 is input, a second NMOS transistor PM12, a second NMOS transistor NM12, and a delay control signal DELAY to a gate thereof. NM13) and its second PMOS The third inverter INV33 for inverting the potential of the common connected drain of the transistor PM12 and the second NMOS transistor NM12 and the output of the third inverter INV33 are fed back to the gate to input the first inverter. The third PMOS transistor PM13 sets the input terminal of the third inverter INV33 to the power supply voltage, and the fourth to sixth inverters INV34-INV36 to delay the inversion of the output of the third inverter INV33. The inverted section DEL11, the output signal of the third inverter INV33 and the output signal of the delay section DEL11 are inverted, and the output signal of the NAND gate ND1 is inverted. And a seventh inverter INV37 for outputting the auto precharge start signal AUTOTOPGST.

The operation of the auto precharge control circuit of the present invention configured as described above is as follows.

FIG. 1 is a block diagram showing the start of auto precharge, and FIG. 2 is a detailed block diagram of the auto precharge delay unit 100, which actually guarantees the pulse width parameter tRAS of the Lars signal RAS. It consists of circuits for

The present invention consists of an auto delay unit 120 composed of an auto precharge oscillator 110 and a shift unit ST1-ST7, which are oscillators for detecting a clock, in order to ensure a pulse width parameter tRAS of a lath signal.

FIG. 3 is a detailed circuit diagram of the auto precharge oscillator 110 of the auto precharge delay unit 100 of FIG. 2. The ras active signal RRASTV <0: 3 used in each bank in the las active signal combination unit 111 is shown in FIG. > Is used as a signal for enabling the oscillator 113 by being combined by the NOR gate NOR, and the active signal ACTB and the delay control signal used in each bank in the delay control signal combination unit 112. Each of DELAY is combined by NOR gates NOR1-NOR4, and then the combined signals are combined by NOR gate NOR5 and used as a signal for disabling the oscillator 113. FIG. That is, when only one signal of the ras active signals RRASTV <0: 3> becomes a logic high pulse in the ras active signal combination unit 111, the combined ras active signals RRASTVSUM generate a high pulse. The oscillation unit 113 is operated by setting the oscillation enable signal OSCEN to a logic high level.

The ras active signal RRASTV is a pulse signal generated when a bank active command is input.

The delay control signal DELAY is a level signal enabled after the bank active command is input and after the pulse width parameter tRAS of the lath signal is sufficiently secured.

The active signal ACTB is a signal in which the ras active signal RasATV, which is a pulse signal, is changed to a level signal, and has a low level when the ras active signal RasATV is a high pulse.

In addition, in the case of the semiconductor memory device including the four banks BANK, the lath active signal RSATV, the delay control signal DELAY, and the active signal ACTB are generated for each bank. Signal is used.

On the other hand, when disabled, if the first bank is active, the first delay control signal DELAY <0> is enabled to a logic high level after the pulse width tRAS of the erase signal.

At this time, the active signal ACTB <0> activates the first bank and therefore has a logic low level. Here, since the second to fourth banks are not active, the active signals ACTB <1>, ACTB <2>, and ACTB <3> become logic high levels, and the delay control signals DELAY <1> and DELAY < 2> and DELAY <3> are at the logic low level, and all the input signals of the fifth NOR gate NOR5 of the delay control signal combination unit 112 are at the low level.

Accordingly, since the output of the fifth NOR gate NOR5 is at a logic high level, and the combined delay control signal DELAYBNOR is at a low level, the enable signal OSCEN of the oscillator 113 is at a low level. The oscillation operation of the 113 is stopped.

Here, if the time equal to the pulse width parameter tRAS of the lath signal has not passed in the first bank, the active signal ACTB <0> is at a low level, and the delay control signal DELAY <0> is also at a low level, thereby delaying. Since the output of the second NOR gate NOR2 of the control signal combination unit 112 becomes a high level, the combined delay control signal DELAYBNOR becomes a high level, so that the enable signal OSCEN of the oscillator 113 is low. Since the level cannot be reached, the oscillator 113 stops the oscillation operation after the pulse width parameter tRAS of the lath signal passes after the bank is activated.

On the other hand, when the multi-bank rather than the single bank is activated, the combined delay control signal DELAYBNOR only when the outputs of the first to fourth NOR gates NOR1 to NOR4 of the auto precharge oscillator 110 are all at a low level. Since the low level becomes high, when any one of the outputs of the first to fourth NOR gates NOR1 to NOR4 becomes a high level, the combined delay control signal DELAYBNOR may not transition to the low level. That is, when all banks are active, all active signals ACTB <0: 3> are at a low level, and all delay control signals DELAY <0: 3> are at a low level.

First, even if the first delay control signal DELAY <0> is at a high level, since the remaining delay control signals DELAY <1>, DELAY <2>, and DELAY <3> are at a low level, the fifth NOR gate ( Since only one signal of the input value of NOR5) is low level and the remaining signals are high level, the combined delay control signal DELAYBNOR keeps the high level.

Therefore, when all of the delay control signals DELAY of the activated banks transition to the high level, the combined delay control signals DELAYBNOR transition to the low level, and the oscillator 113 does not oscillate.

Subsequently, when the active signal ACTB is auto precharged to reach a high level, the combined delay control signal DELAYBNOR also becomes a high level.

When the shift control signals SHIFT and SHIFTB are generated by the auto precharge oscillator 110, the delay control signals DELAY are generated by the auto precharge delay units 121 to 124 according to the shift control signals SHIFT and SHIFTB. ) Will occur.

The auto precharge delay units 121-124 are used for each bank.

The las precharge control signals RASPCG <0: 3> are applied to the auto precharge delay units 121-124, respectively. The las precharge control signals RASPCG are low pulsed when a precharge or auto precharge command is input. It is a signal having.

When a low pulse of the las precharge control signal RASPCG is input, the active signal ACTB becomes a high level and the reset signal INIT has a high pulse. Therefore, the output of the shift units ST1-ST4 is low. Make it a level and reset it.

When the last active signal RSATV becomes a high pulse, the active signal ACTB becomes a low level. Then, a high level is input to the data input of the first shifter ST1.

The data value input at the high level to the first shifter ST1 passes through one shifter whenever the shift control signals SHIFT and SHIFTB toggle.

When the data value passes all the shift parts, the delay control signal DELAY changes from the low level to the high level.

Since the shift control signals SHIFT and SHIFTB are each passed at the high level, the shift control signals SHIFT and SHIFTB are shifted once in half of the cycle of the auto precharge oscillator 110 described above.

In this case, since the shift portion is composed of seven, the delay control signal DELAY becomes a high level in only 3.5 clocks of the oscillation period.

Therefore, it is possible to infer the relationship between the oscillation period and the pulse width parameter tRAS of the lath signal. That is, oscillation cycle (T)

= (tRAS-time when the ras active signal (RASATV) is active (t)) / (number of shift parts / 2)

= ((tRAS-time when the ras active signal (RASATV) is active (t)) * 2) / number of shift parts

The oscillation period T is determined by the above formula.

When the auto precharge control signal AUTOTOPG is input to the auto precharge command, the auto precharge control signal AUTOTOPG is input to the auto precharge control unit 200.

Therefore, the output signal of the latch part LAT11 becomes high level, and turns on the 2nd NMOS transistor NM12. However, since the delay control signal DELAY is enabled at the high level after the pulse width tRAS of the lath signal after the bank is activated, the auto precharge control unit 200 when the delay control signal DELAY reaches the high level. The auto precharge start signal (AUTOPCGST), which is an output signal of the N1, becomes a high pulse to perform the actual autocharge operation. Here, the auto precharge start signal AUTOPCGST makes the las precharge signal RASPCG low.

As another embodiment of the auto precharge control circuit of the present invention, an auto precharge oscillator can be used for each bank.

In this case, the auto precharge oscillator is configured separately to operate when each bank is activated.

FIG. 6 is a circuit diagram showing an auto precharge oscillator used in another embodiment of the auto precharge control circuit of the present invention. As shown in FIG. PMOS transistors PM21 and NMOS transistors 21 to which the delay control signal DELAY is inverted by the first inverter INV41 and the ras active signal RASATV are applied, and the PMOS transistor PM21. ) And a latch portion LAT21 composed of a second inverter INV42 and a third inverter INV43 interconnected with an input and an output for inverting and latching a potential of a common connected drain of the NMOS transistor NM21, and the latch thereof. The oscillation unit OSC oscillates according to the oscillation enable signal OSCEN, which is an output signal of the unit LAT21, and outputs shift control signals SHIFT and SHIFTB. Here, the oscillator OSC feeds the oscillation enable signal OSCEN and the shift control signal SHIFTB to non-invert the NAND gate ND11 and the output of the NAND gate ND11. The delay unit DEL21 including the fourth to ninth inverters INV44-INV49 for outputting the shift control signal SHIFTB, and the output signal SHIFTB of the delay unit DEL21 are inverted to shift the shift control signal SHIFT. It is configured to include a tenth inverter (INV410) for outputting.

Therefore, when only the ras active signal (RASATV) of the corresponding bank is enabled, the auto precharge oscillator used in the corresponding bank is unconditionally operated, and the delay control signal is generated after the pulse width tRAS of the ras signal by the auto precharge delay unit. When enabled, the oscillator will stop oscillating.

As described above, the present invention can satisfy the pulse width parameter tRAS of the lath signal set in the specification of the semiconductor memory device at any cascade and burst length, so that the semiconductor memory device can operate stably. have.

Claims (10)

In a semiconductor memory device composed of a plurality of banks to perform auto precharge, Oscillation means controlled by an external control signal; A delay control circuit comprising a plurality of shift means controlled by an output signal of the oscillation means; And And an auto precharge control means for outputting an auto precharge control signal controlled by an output signal of the delay control circuit and an external control signal to control an auto precharge operation. The method of claim 1, The oscillation means, First logical combining means for logically combining first external control signals corresponding to each bank having a low pulse by a precharge command and an auto precharge command; The second external control signals corresponding to each bank in which the pulse signal generated when the bank active command is input into the level signal and the level signal being enabled after being delayed by the pulse width of the lath signal after the bank active command is input. Second logical combining means for logically combining third external control signals corresponding to the bank; Oscillation control means for controlling the oscillation operation by receiving the output signals of the first logic combining means and the second logic combining means; And And a shift control means controlled by an output signal of the oscillation control means and selectively driven to output an oscillation signal. The method of claim 2, The first logical combining means, A NOR gate for negative logic sum of the first external control signals; And And an inverter for inverting the output of the NOR gate. The method of claim 2, The second logic combining means, A plurality of NOR gates each negative logic sum of a second external control signal and a third external control signal corresponding to each bank; A NOR gate for negative logic sum of the outputs of the plurality of NOR gates; And And an inverter for inverting the output of the NOR gate. The method of claim 2, The oscillation control means, A PMOS transistor and an NMOS transistor connected in series between a power supply voltage and a ground voltage to which output signals of the first logic combining means and the second logic combining means are respectively applied to a gate; And And latch means for inverting and latching the potentials of the common connected drains of the PMOS transistors and the NMOS transistors. The method of claim 2, The shift control means, A NAND gate receiving a feedback input of an output signal of the oscillation control means and an inverted oscillation output signal and performing a negative logic multiplication on the output signal; Delay means for outputting an inverted oscillation output signal by non-inverting delay of the output of the NAND gate; And And an inverter outputting the oscillation output signal by inverting the output of the delay means. The method of claim 1, Each delay control means, A fourth external control signal corresponding to each bank having a low pulse by a precharge command and an auto precharge command on a gate connected in series between a power supply voltage and a ground voltage, and a bank signal generated by a bank active command. A PMOS transistor and an NMOS transistor to which corresponding second external control signals are respectively applied; Latch means for inverting the potential of the common connected drain of the PMOS transistor and the NMOS transistor; And And a plurality of shift means for applying the inverted signal of the fourth external control signal to a reset input terminal to be reset and controlled by an output signal of the oscillation means to shift the signal latched by the latch means. An auto precharge control circuit. The method of claim 7, wherein Each said shift means, Selective transmission means controlled by an output signal of said oscillation means for selectively transmitting data input; Latch means for inverting latching a data input selectively transmitted by the selective transfer means; An inverter for inverting the signal latched by the latching means and outputting a third external control signal corresponding to each bank, the level signal being enabled after being delayed by the pulse width of the lath signal after the bank active command is input; And And resetting means controlled by the inverted signal of the fourth external control signal to reset the input terminal of the latch means. The method of claim 1, The auto precharge control means, A fifth external control generated by an auto precharge command and a fourth external control signal corresponding to each bank connected in series between a power supply voltage and a ground voltage and having a low pulse by a precharge command and an auto precharge command to a gate; A first PMOS transistor and a first NMOS transistor to which signals are respectively applied; Latch means for inverting and latching potentials of a common connected drain of the first PMOS transistor and the first NMOS transistor; After the bank active command is input to the second PMOS transistor, the second NMOS transistor, and the gate, which are connected in series between a power supply voltage and a ground voltage, and whose gates are connected in common, and the signal latched by the latching means is applied, a las signal. A third NMOS transistor configured to receive a third external control signal corresponding to each bank, the level signal being enabled after being delayed by a pulse width of? A first inverter for inverting a potential of a common connected drain of the second PMOS transistor and the second NMOS transistor; Floating prevention means for receiving an output signal of the first inverter from the feedback and preventing the input terminal of the first inverter from being floated; Delay means for inverting and delaying the output signal of the first inverter; A NAND gate which negatively multiplies the output signal of the first inverter and the output signal of the delay means; And And a second inverter for inverting the output signal of the NAND gate. The method of claim 1, The oscillation means, Signal and bank in which the third external control signal corresponding to each bank, which is a level signal connected in series between the power supply voltage and the ground voltage, is a level signal enabled after being delayed by the pulse width of the lath signal after the bank active command is input to the gate A PMOS transistor and an NMOS transistor to which a sixth external control signal corresponding to each bank, which is a pulse signal generated by an active command, is applied, respectively; Latch means for inverting the potential of the common connected drain of the PMOS transistor and the NMOS transistor; A NAND gate that negatively multiplies the signal latched by the latch means and the inverted shift control signal; Delay means for outputting an inverted shift control signal by non-inverting delay of the output signal of the NAND gate; And And an inverter for outputting a shift control signal by inverting the output signal of the delay means.