KR100359811B1 - Apparatus for controlling memory - Google Patents

Abstract

In particular, the present invention relates to a memory control device that reads and writes data in a memory in a digital TV, and more particularly, a write buffer for temporarily storing data output from an external host when the external host wants to write data to the memory, A read buffer for reading and temporarily storing data of the memory through a memory arbiter and outputting the data to the external host when the external host wants to read data from the memory, and write and read operations of the write buffer and the read buffer. By including a control register for storing the information for controlling the host interface unit to further access the external memory, any host can be applied to any external interface.

Description

Apparatus for controlling memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital televisions (DTVs), and more particularly to a memory control device that reads and writes data in a memory.

In a general case, a host (eg, a CPU) has a timing diagram as shown in FIG. 1 and accesses peripheral peripherals.

Alternatively, in FIG. 1, there is a host in which a cycle ready signal is missing and supports only fixed length cycle time.

That is, the external host addresses the peripheral device (hereinafter referred to as peri) to which the external host wants to access along with the chip select signal (hereinafter referred to as CS) as shown in FIGS. 1A and 1B. , Read / write signal, data (data to write if you want to write, data to be read if you want to read as well as peri). The selected external peri then informs the host that it is ready, one of the methods informing the host by enabling the cycle ready signal as shown in FIG. The host then ends the cycle by releasing CS.

Here, the cycle preparation signal of FIG. 1C becomes a high impedance state when CS is in an inactive state. In addition, although the polarity of the ready signal is set to Active High in FIG. 1, this can be adjusted to Active Low.

At this time, some hosts can adjust the timing of recognizing the cycle ready signal, but some are fixed or have a very short length (for example, about 128 host clocks).

Hosts that can arbitrarily adjust the length of the ready signal have no problem accessing very slow Peri, but if this is specified, there is a problem accessing the Slow peri.

In particular, as shown in FIG. 2, a plurality of peri 202-1, 202-2, 202-3 are connected to the memory 203 through a memory arbitor 205-5 in parallel, and the external host 201 is connected to the host. In the case of the chip 202 having the structure connected to the memory 203 through the interface unit 202-4 and the memory arbiter 202-5, the host 201 has a large amount of access to the memory 203. Problems may occur such that the memory 203 may not be accessed.

That is, in the structure of FIG. 2, each of the peripheral peri 202-1, 202-2, and 202-3 and the host interface unit 202-4 access the memory 203 which is at the same time or separately. In each of the blocks 202-1 to 202-4, a request is sent to the memory arbiter 202-5 to access the memory 203, and the memory arbiter 202-5 After checking the request from the block, it decides which block to process first. Then, the determined block is allowed to access the memory 203.

In this case, the memory arbiter 202-5 may process the request from each block with priority, or may process the request from the first one, or a mixture of the two methods. It may be.

Whatever method is used, it is clear that the time for which a block accesses the memory 203 is not constant.

Therefore, even when the external host 201 attempts to access the memory 203, it may occur that a proper access (write or read operation) cannot be performed using an existing method.

This is because, in the structure shown in FIG. 2, when the external host 201 wants to access the memory 203, the external host 201 first floats a CS. Then, the host interface unit 202-4 accesses the memory 203 and gives a ready signal to the external host 201 again, thereby ending one cycle. The problem is that the host interface unit 202-4 performs the memory. The time for accessing 203 is not constant. This time can be very long due to the influence of other blocks and vice versa.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a memory control apparatus that allows an external host to stably access an external memory.

1A to 1C are general host interface timing diagrams

2 is a block diagram of a conventional memory control apparatus;

3 is a configuration block diagram of a memory control apparatus according to the present invention;

Explanation of symbols for main parts of the drawings

301: host 400: chip

401: host interface 401-1: write buffer

401-2: read buffer 401-3: control register

402: memory arbiter 500: memory

The memory control apparatus according to the present invention for achieving the above object comprises a write buffer for temporarily storing data output from the external host when the external host is to write data to the memory and then writing to the memory through the memory arbiter; A read buffer for reading and temporarily storing data of the memory through a memory arbiter and outputting the data to the external host when the external host wants to read data from the memory, and write and read operations of the write buffer and the read buffer. And a control register to store information for controlling the host interface.

The present invention reads data from a memory regardless of whether the ready signal length is very short when an external host has a predetermined length of write and read operation time or receives a data ready signal. Or write data to memory.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating the configuration of a memory control apparatus according to the present invention, which includes a write buffer 401-1, a read buffer 401-2, and a control register 401-in the host interface 401 in the chip 400. 3) is further provided.

At this time, the following information is stored in the control register 401-3.

. Memory address to write

. Number of data to write

. Command to start writing

. Bit indicating write operation

. Memory address to read

. Number of data to read

. The number of valid data remaining in the read buffer

. Bit interrupt enable bit indicating whether data remaining in the read buffer is valid

Here, the information stored in the control register 401-3 is an example, which may be changed by a designer.

According to the present invention, when the following information is stored in the control register 401-3, the host 301 writes data to the memory 500 in the following process.

First, a memory address to be written, the number of data to be written, and an instruction to start now are written to the control register 401-3.

In this case, the host interface unit 401 stores data related to a write operation to the memory 500 coming from the next time in the internal write buffer 401-1 without directly sending the data to the memory 500.

When the external host 301 finishes the write operation, the host interface 401 compares the number of data pre-set by the host 301 with the number of data actually written by the host, and determines that the host has run out of data. A request is made to the arbiter 402.

At this time, the host interface unit 401 marks the control register 401-3 as writing to the memory 500 at this time.

The host interface 401 then writes all data stored in the write buffer 401-1 to the memory 500 through the interface of the memory arbiter 402. When all the write operations are completed, the host interface unit 402 clears a bit indicating that the write operation of the control register 401-3 is in progress and generates an interrupt to the host 301 (interrupt enable bit). Is '1') or is waiting.

At this time, the external host 301 always polls the control register 401-3 or waits for an interrupt to be input, and when it is determined that the write operation is completed, the next write operation can be started. do.

This will end one cycle within a certain time, allowing the host 301 to write safely.

On the other hand, when the host 301 wants to read some data from the memory 500, it goes through the following process.

First, a memory address to be read, the number of data to be read, and the like are written into the control register 401-3, and a command bit to read is set.

The host interface 401 then sets a bit in the control register 401-3 indicating '0' that the data in the read buffer 401-2 is valid.

The host interface 401 interfaces with the memory arbiter 402 to read data of a desired address from the memory 500 and write the data of the desired address into the internal read buffer 401-2.

Then, a bit indicating that data in the read buffer in the control register 401-3 is valid is set to '1', and an interrupt is generated to an external host 301 (the interrupt enable bit is' 1 ').

At this time, the external host 301 continuously polls the control register 401-3 or waits for an interrupt, and when an interrupt occurs, it can be known that data has entered the current read buffer 401-2. . Accordingly, the external host 301 can read data from the memory 500 by accessing the read buffer 401-2. At this time, the external host 301 may check whether the data in the read buffer 401-2 is valid, and also check the number of valid data.

By using the above write and read method, all the memory write and read operations can be processed within the same time. Also, the processing time can be compared with the host interface accessing the memory each time the host accesses the memory. There is a significant savings.

In particular, in the present invention, when multiple blocks inside the chip use one common memory through a memory arbiter, an external host (e.g., a CPU) can effectively access a fixed length cycle time only. Allow the host to access memory.

As described above, according to the memory control apparatus according to the present invention, when the external memory is accessed, there is an advantage that all the interfaces can be applied to any host. In particular, the present invention provides a significant help in the development of a set or a program by allowing an external host to access the memory when each block in the chip, such as a high-definition (HD) chip, shares and writes a memory. Can give

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (5)

A memory control apparatus including a plurality of peripheral devices accessing an external memory through a memory arbiter, a host interface unit, and an external host accessing the external memory through the host interface unit. A control register for storing information necessary for writing data when the external host wants to write data to the memory, and for storing information necessary for reading data when the external host wants to read data from the memory; A write buffer storing data output from an external host according to write information stored in the control register and outputting the data to the memory through a memory arbiter when the external host wants to write data to the memory; When the external host wants to read data from the memory, a read buffer which reads and stores the data of the memory through a memory arbiter according to the read information stored in the control register and outputs the data to the external host further includes a read buffer. Memory control device, characterized in that it is included. The method of claim 1, wherein the host interface unit When the external host wants to write data to the memory, it stores a memory address to write to the control register, the number of data to write, and a command to start now, and then stores the data output from the host in a write buffer. When the operation is completed, the memory control device comprising requesting the memory arbiter to write data to the memory only when the number of data previously set by the host and the number of data actually written by the host are the same. The method of claim 2, wherein the host interface unit When the memory arbiter wants to write data stored in the write buffer to the memory, the control register is marked as writing to the memory, and then all data stored in the write buffer through the interface of the memory arbiter are stored in the memory. Writing and clearing a bit indicating that a write operation of the control register is completed after all write operations are completed. The method of claim 1, wherein the host interface unit When the external host wants to read data from the memory, it sets the memory address to read in the control register, the command bit to store and read the number of data to read, and then interfaces with the memory arbiter to set the desired address from the memory. A memory control device which reads data and stores it in a read buffer. The method of claim 4, wherein the host interface unit Before storing the data in the read buffer, the control register resets a bit indicating whether the data in the read buffer is valid or not, and indicates that the data in the read buffer is valid when the data is stored in the read buffer. A memory control device, characterized in that for setting the bit.