KR100348951B1 - 조건부레지스터쌍으로부터의메모리저장 - Google Patents
조건부레지스터쌍으로부터의메모리저장 Download PDFInfo
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- KR100348951B1 KR100348951B1 KR1019940032080A KR19940032080A KR100348951B1 KR 100348951 B1 KR100348951 B1 KR 100348951B1 KR 1019940032080 A KR1019940032080 A KR 1019940032080A KR 19940032080 A KR19940032080 A KR 19940032080A KR 100348951 B1 KR100348951 B1 KR 100348951B1
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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Landscapes
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- General Engineering & Computer Science (AREA)
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- Executing Machine-Instructions (AREA)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/160,118 US6058473A (en) | 1993-11-30 | 1993-11-30 | Memory store from a register pair conditional upon a selected status bit |
| US08/160118 | 1993-11-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950015071A KR950015071A (ko) | 1995-06-16 |
| KR100348951B1 true KR100348951B1 (ko) | 2003-01-24 |
Family
ID=22575589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940032080A KR100348951B1 (ko) | 1993-11-30 | 1994-11-30 | 조건부레지스터쌍으로부터의메모리저장 |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US6058473A (fr) |
| EP (1) | EP0656584B1 (fr) |
| JP (1) | JPH07271969A (fr) |
| KR (1) | KR100348951B1 (fr) |
| DE (1) | DE69428499T2 (fr) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100549705B1 (ko) * | 1996-08-23 | 2006-04-28 | 마쯔시다덴기산교 가부시키가이샤 | 신호처리장치 |
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Also Published As
| Publication number | Publication date |
|---|---|
| EP0656584B1 (fr) | 2001-10-04 |
| DE69428499D1 (de) | 2001-11-08 |
| US6173394B1 (en) | 2001-01-09 |
| KR950015071A (ko) | 1995-06-16 |
| JPH07271969A (ja) | 1995-10-20 |
| EP0656584A1 (fr) | 1995-06-07 |
| US5696959A (en) | 1997-12-09 |
| US6058473A (en) | 2000-05-02 |
| DE69428499T2 (de) | 2002-05-16 |
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