KR100348217B1 - Redundancy circuit - Google Patents

Abstract

PURPOSE: A redundancy circuit is provided to prevent the generation of a reverse current by determining whether a cell address signal is a normal signal or a redundancy signal. CONSTITUTION: Each source terminal of two or more address signal applying MOS(Metal Oxide Semiconductor) transistors(N41,N42) is connected to a ground voltage supplying unit. An address signal is inputted to a gate terminal of the address signal applying MOS transistors(N41,N42). Two or more first fuses(F41) are respectively connected to a first output terminal and the address signal applying MOS transistors(N41,N42) and control a voltage precharged to the first output terminal, which is discharged to the ground voltage supplying unit through the address signal applying MOS transistors(N41,N42). Each source terminal of two or more address applying MOS transistors(N43,N44) is connected to the ground voltage supplying unit. An address signal is inputted to a gate terminal of the address applying MOS transistors(N43,N44). Two or more second fuses are connected between the pair of address applying MOS transistors(N43,N44) and a central node. An address signal switching unit connected between the first output terminal and the central node controls a supplying voltage according to a level-type address signal, which is inputted through the address applying MOS transistors(N43,N44) and the second fuses, to be transferred to the first output terminal.

Description

Redundancy Circuit

The present invention relates to a redundancy circuit, and more particularly, to a redundancy sensing circuit for detecting whether a cell select address signal is a normal signal or a redundancy signal when a cell select address signal, part of which is a pulse signal and part of a level signal, is input.

Redundancy means that when a semiconductor device has a defect, an extra memory cell is made in advance and the defective cell is replaced by a spare cell.

The memory device is composed of a cell that stores data and peripheral circuits for selecting and operating the cell. The cells are called a core.

Since the core circuit is manufactured in a microstructure in the process, when impurities such as dust adhere to the core region during the process, the cell is destroyed and incorrect data is output for a specific address.

In this case, in order to prevent the entire device from being used, a spare cell is prepared in advance, and then inspected and replaced with a spare cell.

In order to make such an operation possible, a device for detecting whether an input address signal is an address signal for a normal cell or an address signal in which a failure occurs is required. When a redundancy address is input, a cell corresponding to the address is not accessed. There is a need for an apparatus that accesses redundancy cells without.

Such a non-repaired conventional redundancy circuit will be described in detail below.

In FIG. 1, the conventional redundancy circuit, which is not repaired, is connected between the power supply voltage supply Vdd and the first output terminal N1 and controlled according to the signal pcg for precharging the circuit to supply the power supply voltage Vdd. A PMOS transistor P1 for precharging the first output terminal N1 to a high level by a power supply voltage supplied from the PMOS transistor, and a source terminal thereof is connected to the ground voltage supply unit Vss, and a pulse type cell selection address signal is provided as a gate terminal. (a1, / a1, a2, / a2) are respectively applied, and the precharged high level voltage of the first output terminal N1 is applied to the ground voltage supply unit Vss according to the application of the pulsed cell selection address signal. Four NMOS transistors (N11, N12, N13, N14) for discharging, and four fuses connected between the first output terminal (N1) and NMOS transistors (N11, N12, N13, N14) and programming an address, respectively. (F1, F2, F3, F4) and the low and low The NAND gate 11 includes a signal s1 for enabling a column operation and a signal of the first output terminal N1.

The operation of the conventional unrepaired redundancy circuit will be described below.

When the precharge signal pcg is input to the PMOS transistor P1 through the gate terminal of the PMOS transistor P1, that is, as shown in FIG. 1B, the precharge signal pcg, which was high in the standby state, is low. When transitioned to the level, the first output terminal N1 is precharged to the high level Vcc.

For example, if one address signal selected from the pulsed cell selection address signals a1, / a1, a2, and / a2 is input to one of the four NMOS transistors N11, N12, N13, and N14, for example, the selected first pulse When the type cell select address signal a1 is input to the gate of the first NMOS transistor N11, the first NMOS transistor N11 is turned on to be conductive.

As the first NMOS transistor N11 is turned on, a high level voltage precharged to the first output terminal N1 is connected to the ground voltage supply unit Vss through the first fuse F11 and the first NMOS transistor N11. Discharged.

Accordingly, the first output terminal N1 has a low level.

After that, when the signal s1 for enabling row or column operation is input to the NAND gate 11, the second output terminal () may be combined with the low level output of the first output terminal N1. OUT) has a high level to achieve normal operation.

2 is an example of a repaired conventional redundancy circuit, in which a conventional repaired redundancy circuit is connected between a power supply voltage supply Vdd and a first output terminal N1 and controlled according to a signal pcg for precharging the circuit. PMOS transistor P1 for precharging the first output terminal N1 to a high level by a power supply voltage supplied from the power supply voltage supply unit Vdd, and a source terminal of which is connected to a ground voltage supply unit Vss, respectively. The first and fourth pulsed cell selection address signals a1 and / a2 are respectively applied to the terminals, and the first output terminal (a1 and / a2) is applied according to the application of the first and fourth pulsed cell selection address signals a1 and / a2. First and fourth NMOS transistors N21 and N24 for discharging the precharged high level voltage of N1 to the ground voltage supply unit Vss, and the first output terminal N1 and the first and fourth NNOS, respectively. Is connected between transistors N21 and N24 and the Ramming the first and fourth fuses F21 and F24, the source terminal of which is connected to the ground voltage supply unit Vss, the drain terminal of which fuse is blown, and the gate terminal of the second and third pulse type cell selection addresses. The second and third NMOS transistors N22 and N23 to which the signals / a1 and a2 are applied, the signal s1 enabling the row or column operation of the device, and the signal of the first output terminal N1, respectively. And a NAND gate 11 to be combined.

The level state of the cell selection address signals a1, / a1, a2, / a2 can be set to (1,1) (0,1) (1,0) (0,0), where a1 is a low level ("0 &Quot;), / a1 is a high level (" 1 "), a2 is a high level (" l ") and / a2 is a low level (" 0 ") process to detect as a redundancy address.

First, when a normal address is input, a1 and a2 are selected as high level ("1") and / a1 and / a2 are selected as low level ("0").

When the precharge signal pcg is input to the PMOS transistor P1 through the gate terminal of the PMOS transistor P1, that is, as shown in the timing diagram of FIG. 2B, the precharge signal pcg that was at a high level in the standby state. Transitions to the low level at the first timing t1, the first output terminal N1 is precharged to the high level Vcc.

In the second timing t2, the first pulse type cell selection address signal a1 of high level, the second pulse type cell selection address signal / a1 of low level, and the third pulse type cell selection address signal of high level ( a2) and the low-level fourth pulse type cell selection address signal / a2 are respectively applied to the first NMOS transistor N21, the second NMOS transistor N22, the third NMOS transistor N23, and the fourth NMOS. It is input to the transistor N24.

Accordingly, the second NMOS transistor N22 and the fourth NMOS transistor N24 are turned off, and the third NMOS transistor N23 is turned on but the fuse is blown, so that the first output terminal N1 is not affected. The first NMOS transistor N21 is conductive.

As the first NMOS transistor N21 is turned on, the high level voltage precharged to the first output terminal N1 is connected to the ground voltage supply unit Vss through the first fuse F21 and the first NMOS transistor N21. Discharged.

Accordingly, the first output terminal N1 has a low level.

After that, when the signal s1 for enabling low or column operation is input to the NAND gate 11, the combination with the low level output of the first output terminal N1, that is, the third At the timing t3, since the first output terminal N1 is at a low level and the above or column operation enable signal s1 is at a high level, the second output terminal OUT has a high level to achieve normal operation.

On the other hand, cell selection address signals a1 and / a2, which are cases of detecting a redundancy state, will be described as being input at high level ("1") and / a1 and a2 at low level ("0").

When the precharge signal pcg is input to the PMOS transistor P1 through the gate terminal of the PMOS transistor P1, that is, as shown in FIG. When the transition to the low level occurs at the first timing t1, the first output terminal N1 is precharged to the high level Vcc.

At the second timing t2, the low level first pulsed cell selection address signal a1, the high level second pulsed cell selection address signal / a1, and the high level third pulsed cell selection address signal A a2) and a low level fourth pulse type cell selection address signal / a2 are respectively applied to the first NMOS transistor N21, the second NMOS transistor N22, the third NMOS transistor N23, and the fourth NMOS. It is input to the transistor N24.

Accordingly, the first NMOS transistor N21 and the fourth NMOS transistor N24 are turned off, and the second NMOS transistor N22 and the third NMOS transistor N23 are turned on but the fuse is blown, so the first output terminal ( N1) has no effect. That is, the address signals a1, / a1, a2, and / a2 do not affect the first output terminal N1, and the first output terminal N1 maintains the precharged high level state.

Thereafter, when the signal s1 for enabling the low or column operation is input to the NAND gate 11, the combination of the high level output signal of the first output terminal N1, that is, at the third timing t3, is applied. Since the first output terminal N1 is at a high level and the low or column operation enable signal s1 is at a high level, the second output terminal OUT is output at a low level to have a redundancy state.

In the repaired redundancy circuit, when the signal s1 for enabling low or column operation is high, the output terminal is in a high state when the output stage is high level, and when the signal s1 for enabling low or column operation is low. If the output stage is at low level, it detects as redundancy.

In the conventional redundancy circuit shown in FIG. 2, the input addresses are all pulse signals.

Meanwhile, a case in which the cell selection address signal is partly a level signal and partly a pulse signal in the related art will be described with reference to FIG.

FIG. 3A is a conventional redundancy circuit diagram when the cell select address signals are pulsed and leveled, FIG. 3B is a timing diagram of the redundancy circuit shown in FIG. 3A, and FIG. 3C is a precharged timing diagram shown in FIG. 3B. 3D is a timing diagram when the precharging time is delayed in the timing diagram shown in FIG. 3B.

In the case of two level signals and two pulse signals, the conventional redundancy circuit is connected between the power supply voltage supply Vdd and the first output terminal N1 and is controlled according to the signal pcg for precharging the circuit to supply the power supply voltage ( PMOS transistor P1 for precharging the first output terminal N1 to a high level by a power supply voltage supplied from Vdd), and a source terminal thereof is connected to the ground voltage supply unit Vss, and the first pulse type cell is connected to the gate terminal. The selection address signal a1 is applied and discharges the precharged high level voltage of the first output terminal N1 to the ground voltage supply unit Vss according to the application of the first pulsed cell selection address signal a1. The first NMOS transistor N31 and the source terminal are connected to the ground voltage supply unit Vss, the fuse is blown to the drain terminal, and the second pulse type cell selection address signal / A1 is applied to the gate terminal. 2nd N A third NMOS transistor (N32), a source terminal of which is connected to the ground voltage supply unit (Vss), a fuse is blown to the drain terminal, and a third NMOS transistor (1) of which the first level cell selection address signal (A2) is applied to the gate terminal. N33, a fourth NMOS transistor N34 to which a source terminal is connected to a ground voltage supply unit Vss, and a second level cell selection address signal / A2 is applied as a gate terminal, and the first output terminal N1, respectively. ) And first and fourth fuses F21 and F24 connected between the first and fourth NMOS transistors N21 and N24 and programming an address, and a signal s1 for enabling the row or column operation of the device. And a NAND gate 11 combining the signal of the first output terminal N1.

In the following, a part of the cell selection address signal is a level signal and a part is a pulse signal, that is, A1 and / A1 are pulse address signals, and A2 and / A2 are operations of the level type conventional redundancy circuit.

When the precharge signal pcg is input to the PMOS transistor P1 through the gate terminal of the PMOS transistor P1, that is, as shown in FIG. 2B of FIG. When transitioned to the low level at the first timing t1, the first output terminal N1 is precharged to the high level Vcc.

At the second timing t2, the low-level first pulsed cell selection address signal a1, the high-level third pulsed cell selection address signal / a1, and the high-level third pulsed cell selection address signal (a2), the low-level fourth pulse type cell selection address signal / a2 is respectively applied to the first NMOS transistor N31, the second NMOS transistor N32, the third NMOS transistor N33, and the fourth It is input to the NMOS transistor N34.

Accordingly, the first NMOS transistor N31 is turned off and the second NMOS transistor N22 and the third NMOS transistor N23 are turned on, but the fuse is blown so that the first output terminal N1 is not affected. However, since the fourth MOS transistor N34 is turned on by applying the previous level cell select address signal, the PMOS transistor P1 and the fourth NMOS transistor N34 are turned on at the same time to cause reverse current. There was a problem.

In order to solve this problem, as shown in FIG. 3C, when the precharging time is extended from (t11 to t12) to (t11 to t13), a reverse current occurs. The problem still remains.

Accordingly, an object of the present invention is to provide a redundancy circuit which is simple in precharging operation and can prevent the occurrence of reverse current when the cell select address signal is composed of a pulse type signal and a level type signal. have.

In order to achieve the above object, the present invention includes a precharging MOS transistor for precharging a first output terminal to a high level voltage, and the cell select address signal when the cell select address signal includes a pulse type signal and a level signal. In a redundancy circuit for detecting whether is a normal address signal or a redundancy address signal, a source terminal is connected to a power supply voltage supply and is controlled by a precharge signal so that the first output terminal is supplied with a high level voltage supplied from the power supply voltage supply. A precharging morph transistor for precharging, two or more pulse type address signal applying MOS transistors each having a source terminal connected to a ground voltage supply and a pulse type address signal being input to a gate terminal, and the first output terminal and a pulse type respectively Most transistors for address signal application Two or more cut-out first fuses connected to each other to control the discharge of the voltage precharged to the first output terminal to the ground voltage supply unit through a pulse type address applying morph transistor, and a source terminal respectively; Is connected to the ground voltage supply and the two or more level type address transistors are applied to the gate terminal, and the pair of level transistors for applying the level address signal and the intermediate node can be cut off from the outside. At least two second cut-off fuses connected between the first fuse and the first output terminal and the intermediate node, and a second supply voltage according to the level address signal input through the level fuse and the second fuse for applying the level address signal; Level address signal for controlling transfer to one output stage And a logic gate that combines a low or column operation enable signal of the device and a signal of the first output terminal, and is previously applied by the level type address signal switching means according to the application of the level type address signal. Voltage controlled from the two or more level type address applying MOS transistors turned on by the address signal held at a high level to the first output terminal, thereby controlling the transfer of the level type addressing MOS transistor and precharging. It provides a redundancy detection circuit, characterized in that the morph transistor is prevented from being turned on at the same time.

Hereinafter, the redundancy circuit of the present invention will be described in detail with reference to the accompanying drawings.

4A is a redundancy circuit diagram according to an embodiment of the present invention, and FIG. 4B is a timing diagram of the redundancy circuit shown in FIG. 4A.

In the redundancy circuit of the present invention, the source terminal is connected to the power supply voltage supply unit Vdd and controlled by the precharge signal pcg to supply the first output terminal N1 to the high level voltage supplied from the power supply supply voltage unit Vdd. Precharging PMOS transistor P1 for precharging, and two or more pulse type address signal applying NMOS transistors N41, in which a source terminal is connected to a ground voltage supply unit Vss and a pulse type address signal is input to a gate terminal. N42) and a voltage connected to the first output terminal N1 and the NMOS transistors N41 and N42 for applying a pulse type address signal, respectively, which can be cut externally, and thus the precharged voltage at the first output terminal N1 is pulsed. Two or more cut-off first fuses F41 and F42 for controlling discharge from the ground voltage supply unit Vss through the address application NMOS transistors N41 and N42, and the source terminal to the ground voltage supply Vss, respectively.Two or more level address application NMOS transistors N43 and N44 to which the level address signal is input to the gate terminal, and externally cutable NMOS transistors N43 and N44 that can be cut off from each other. ) And two or more cut-off second fuses F3 and F4 connected between the intermediate node N2 and the first output terminal 1 and the intermediate node N2 and the NMOS for applying the level address signal. Level type address signal switching means for controlling the transfer of the supply voltage to the first output terminal according to the level type address signal inputted through the transistors N43 and N44 and the second fuses F3 and F4; And a NAND gate 11 combining the column operation enable signal and the signal of the first output terminal.

The level address signal switching means includes a NOR gate 41 for combining two pulsed address signals, and an NMOS transistor N45 which is switched and controlled by the combination signal of the NOR gate 41.

Hereinafter, the operation of the present invention will be described in detail.

When the precharge signal pcg is input to the PMOS transistor P1 through the gate terminal of the PMOS transistor P1, that is, as shown in FIG. When the transition to the low level occurs at the first timing t1, the first output terminal N1 is precharged to the high level Vcc.

In the normal operation at the second timing t2, one pulse type cell selection address signal of two or more pulsed cell selection address signals is at a high level, and one pulse type address signal application is applied among two NMOS transistors. To the NMOS transistor and to all other pulsed cell select address signals at the low level, respectively, to all the corresponding pulsed address signal application NMOS transistors, for example, the first pulsed cell select address signal A1 is at the high level. The pulsed address signal application NMOS transistor N41 and the low level second pulse type cell selection address signal / A1 are input to the second pulsed address signal application NMOS transistor N42.

As a result, the second pulsed address signal applying NMOS transistor N42 is turned off, and the first pulsed address signal applying MOS transistor N41 is turned on and is a high level precharged to the first output terminal N1. Is discharged to the ground voltage supply unit Vss through the first fuse F41 and the first NMOS transistor N41.

In the redundancy operation at the second timing t2, one pulse type cell selection address signal of two or more pulsed cell selection address signals is set at a high level, and all pulse type cell selection address signals are selected at a low level, and the selected one pulse type is selected. If the fuse connected to the drain terminal of the one pulse type address signal applying NMOS transistor among two or more pulse type address signal applying NMOS transistors selected by application of the cell selection address signal is blown from the outside, for example, When the first pulsed address signal A1 is at a high level and the second pulsed address signal / A1 is at a low level, the first pulsed address signal A1 is applied to the NMOS transistors N41 and N42 for applying the first and second pulsed address signals, respectively. The first fuse F41 connected to the pulsed address signal applying NMOS transistor N41 is blown and the second pulsed address signal applying NMO Since the S transistor N42 is turned off, the pulsed address signals A1 and / A1 have no effect on the first output terminal N1, and the first output terminal N1 maintains the precharged high level state. .

Meanwhile, at the second timing t2, one of the two or more level cell selection address signals is at a high level, and among the two or more level address signal application NMOS transistors, the NMOS transistor for the level address signal application is applied. For example, the first level cell selection address signal A2 is input to the NMOS transistor N43 for applying the first level address signal at a high level.

At this time, in accordance with the application of the combination signal s2 of the first and second pulsed address signals A1 and / A1 by the NOR gate 41, the precharging NMOS transistor N45 is controlled to operate and the previous address signal. As a result, the voltages of the first or second level type address signal applying NMOS transistors N43 and N44 are blocked from being transferred to the first output terminal N1 through the fuses F43 and F44. That is, the PMOS transistor P1 and the NMOS transistor for applying the level type address signal are turned on at the same time to prevent the reverse current from being generated.

Thereafter, when the signal s1 for enabling the low or column operation is input to the NAND gate 11, the combination of the high level output signal of the first output terminal N1, that is, at the third timing t3, is applied. Since the first output terminal N1 is at a high level and the low or column operation enable signal s1 is at a high level, the second output terminal OUT is output at a low level to have a redundancy state.

In the above-described embodiment of the present invention, the case where only two pulse type and level cell selection address signals are provided has been described as an example. For example, three or more pulse type and level type cells such as 3, 4 ... Even if the selection address signal is used, many modifications can be easily made by those skilled in the art without departing from the basic spirit of the present invention.

According to the above, the present invention has an effect that the precharging operation is simple and the problem of reverse current generated when a part of the cell select address signal is a pulse signal and a part is a level signal can be solved.

1 is a conventional unrepaired redundancy circuit.

2A is a conventional repaired redundancy circuit.

2B is a steady state timing diagram of the redundancy circuit shown in FIG. 2A,

FIG. 2C is a redundancy state timing diagram of the redundancy circuit shown in FIG. 2A,

3A is a conventional redundancy circuit diagram when a cell and a selection address signal are pulsed and leveled.

Fig. 3B or timing diagram of the redundancy circuit shown in Fig. 3A.

FIG. 3C or a timing chart when the precharging time is delayed in the timing chart shown in FIG. 3B,

FIG. 3D or a timing diagram when the precharging time is delayed in the timing diagram shown in FIG. 3B,

4A is a redundancy circuit diagram according to an embodiment of the present invention.

4B or timing diagram of the redundancy circuit shown in FIG. 4A.

※ Explanation of code for main part of drawing

11: NAND gate 41: NOR gate (NOR)

N1, OUT: Output stage F11 ~ F44: Fuse

N11 ~ N44: N-type MOS transistor

P1: Deformed Most Transistor

Claims (2)

A precharging MOS transistor for precharging the output stage to a high level voltage and detecting whether the cell select address signal is a normal address or a redundancy address signal when the cell select address signal comprises a pulse signal and a level signal. In the redundancy circuit, Two or more pulsed address signal applying MOS transistors, each of which has a source terminal connected to a ground voltage supply and a pulsed address signal input to a gate terminal; Respectively connected to the first output terminal and the MOS transistor for applying the pulse type address signal, and can be cut from the outside so that the voltage precharged to the first output terminal is discharged to the ground voltage supply unit through the pulse type address applying MOS transistor. At least two cutable first fuses for Two or more level address applying MOS transistors, each of which has a source terminal connected to a ground voltage supply and a level address signal input to a gate terminal; At least two second cut fuses which are externally cut and are connected between the pair of level transistors for applying a level address signal and an intermediate node, respectively; A level address signal connected between the first output terminal and an intermediate node for controlling a transfer of a supply voltage to a first output terminal according to a level type address signal input through the level transistor for applying the level type address signal and a second fuse; Switching means, A logic gate that combines a low or column operation enable signal of the device and a signal of the first output terminal, A first from two or more level type address applying morph transistors which are turned on by an address signal previously applied by the level type address signal switching means and held at a high level according to the application of the level type address signal; Redundancy circuit, characterized in that the voltage transfer to the output terminal is cut-off controlled to prevent the level type address transistor and the precharging morph transistor to be turned on at the same time. The method of claim 1, The level address signal switching means includes a NOR gate for combining two pulsed address signals; Redundancy circuit comprising a morph transistor which is switched controlled by the combination signal of the no gate.