KR100347546B1 - Precharge circuit - Google Patents

Abstract

The present invention relates to a precharge circuit, comprising: a PMOS transistor for adjusting a potential of a first node according to a first control signal and for supplying a power supply voltage to a second node according to the potential of the first node; A capacitor for occupying the power supply voltage supplied through the battery, and discharging it to maintain the second node above a predetermined voltage; and for supplying the power supply voltage to the third node according to a potential of the second node that is higher than the power supply voltage. An NMOS transistor and a capacitor for occupying the power supply voltage supplied to the third node through the NMOS transistor, and discharging the same, to hold the third node at a potential higher than the power supply voltage, greatly reducing the size of the PMOS transistor. And a precharge circuit capable of raising the potential of the third node without dropping the threshold voltage.

Description

Precharge Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a precharge circuit, and in particular, it is possible to significantly reduce the size of a PMOS transistor applying a power supply voltage to occupy a capacitor, and to boost a voltage over a predetermined voltage without a drop in threshold voltage by using an NMOS transistor driven by a high voltage. It relates to a precharge circuit capable of generating a voltage.

When driving a flash memory device, a high voltage must be applied to the gate of the cell in order to select and read an advanced cell of a word line. To this end, a boosting voltage of more than a predetermined voltage must be applied, and a precharge circuit is used for this purpose.

1 is a circuit diagram of a conventional precharge circuit, which is configured as follows.

A first PMOS transistor P11, which is a high voltage transistor driven according to the potential of the first node Q11, is connected between the power supply terminal and the second node Q12. A first NMOS transistor N11 driven according to the first control signal KICK is connected between the first node Q11 and the ground terminal Vss. A second PMOS transistor P12 driven according to the first control signal KICK is connected between the first node Q11 and the second node Q12. The first inverter I11 inverts the control signal KICKb, and the first capacitor C11 is connected between the first inverter I11 and the second node Q12. A third PMOS transistor P13 driven according to the switching bar signal SWb is connected between the second node Q12 and the third node Q13. The first resistor R11 is connected between the third node Q13 and the output terminal OUT. A second NMOS transistor N12 driven in accordance with the second capacitor C12 and the second control signal KICKb is connected in parallel between the output terminal OUT and the ground terminal Vss. Here, the first control signal KICK is a kick signal KICK for instantaneously applying a high voltage, and the second control signal KICKb is its inverted signal.

The driving method of the conventional precharge circuit configured as described above is as follows.

When the first control signal KICK is applied in a high state, the first NMOS transistor N11 is turned on and the second PMOS transistor P12 is turned off. The potential of the first node Q11 is turned low by the turned-on first NMOS transistor N11. The first PMOS transistor P11 is turned on by the potential of the first node Q11 that maintains the low state. The power supply voltage Vcc is supplied to the second node Q12 by the turned-on first PMOS transistor P11. The first capacitor C11 is occupied by the power supply voltage Vcc supplied to the second node Q12. Meanwhile, the second control signal KICKb applied in the low state is inverted to the high state through the first inverter I11 and applied to the first capacitor C11. Accordingly, the second node Q12 maintains a potential of about 2 Vcc by discharging the electric charges charged in the first capacitor C11. In this state, when the switching signal is applied after the first control signal KICK is inverted to the high state, the third PMOS transistor P13 is turned on by the inversion signal SWb, and the potential of the second node Q12 is reset to zero. It is output to the output terminal OUT through the three nodes Q13.

When the first control signal KICK is applied in the low state, the second control signal KICKb is applied in the low state to turn on the second NMOS transistor N12 to initialize the output terminal OUT. The first NMOS transistor N11 is turned off and the second PMOS transistor P12 is turned on by the first control signal KICK applied in the low state. The potential of the first node Q11 through the turned on second PMOS transistor P12 also maintains a high potential of about 2 Vcc equal to that of the second node Q12. Accordingly, since the first node Q11 maintains the potential of the high state, the first node Q11 turns off the first PMOS transistor P11, and the second node Q12 maintains the potential of 2Vcc. On the other hand, the second control signal KICKb in the high state is inverted to the low state through the first inverter I11 and applied to the first capacitor C11, but does not affect the operation of the first capacitor C11. Accordingly, the second node Q12 continuously maintains a potential of 2 Vcc. In this state, if the switching signal is not applied, the third PMOS transistor P13 is not operated and thus the potential of the second node Q12 is not output to the output terminal OUT.

As described above, in the conventional precharge circuit, when the first control signal KICK is applied in a high state, the first PMOS transistor P11 is turned on to supply the power voltage Vcc to the second node Q12. Charge is charged in the first capacitor C11 and the charge in the first capacitor C11 is also discharged, so that the second node Q12 maintains a potential of about 2 Vcc. On the other hand, when the first control signal KICK is applied in the low state, the first PMOS transistor P11 is turned off to cut off the supply of the power supply voltage Vcc, but the potential of the second node Q12 is about 2 Vcc. Will continue to be maintained.

Simulation results of each node of the conventional precharge circuit driven as described above are shown in FIG. 2, and individual results are shown in FIG. 3.

However, due to the characteristics of the PMOS transistor, before the potential of the second node Q12 maintaining about 2 Vcc is supplied to the first node Q11 through the turned on second PMOS transistor P12, the charge of the second node Q12 is applied. There is a problem that is lost. Simulation results for this are shown in FIG. 4. To solve this problem, the n well loading of the PMOS transistor must be increased.

Accordingly, an object of the present invention is to provide a precharge circuit capable of simultaneously solving the problem of charge loss while reducing the n-well loading of a PMOS transistor for supplying a power supply voltage.

The present invention for achieving the above object is a first switching means for adjusting the potential of the first node in accordance with the first control signal, and a first for supplying a power supply voltage to the second node in accordance with the potential of the first node Second switching means, first charge storage means for charging the power supply voltage supplied to the second node, discharging the charged charge in accordance with a second control signal to raise the potential of the second node to a predetermined potential; And third switching means for supplying a power supply voltage to a third node according to the potential of the second node raised to the predetermined potential, a power supply voltage supplied to the third node, and inverting the second control signal. And second charge storage means for discharging the charged charge according to the signal to raise the potential of the third node to a predetermined potential.

1 is a conventional precharge circuit diagram.

FIG. 2 is a graph showing a simulation result of each node of FIG. 1.

3 is a graph showing the simulation results of each node of FIG. 1 individually;

4 is a current graph of a first PMOS transistor in which the charge loss of FIG. 1 is generated.

5 is a precharge circuit diagram according to the present invention.

FIG. 6 is a graph showing a simulation result of each node of FIG. 5.

FIG. 7 is a graph showing simulation results of each node of FIG. 5 individually. FIG.

8 is a current graph of a first PMOS transistor in which the charge loss of FIG. 5 does not occur.

The present invention will be described in detail with reference to the accompanying drawings.

5 is a circuit diagram of a precharge circuit according to the present invention, and is configured as follows.

A first PMOS transistor P21 driven according to the potential of the first node Q21 is connected between the power supply terminal Vcc and the fourth node Q24. A first NMOS transistor N21 driven according to the first control signal KICK is connected between the first node Q21 and the ground terminal Vss. The second PMOS transistor P22 driven according to the first control signal KICK is connected between the first node Q21 and the fourth node Q24. The first capacitor C11 is connected between the second control signal KICKb input terminal and the fourth node Q24. A second NMOS transistor N22 driven according to the potential of the fourth node Q24 is connected between the power supply terminal and the second node Q22. The first inverter I21 inverts the second control signal KICKb, and the second capacitor C22 is connected between the second node Q22 and the first inverter I21. A third PMOS transistor P23 driven according to the switching bar signal SWb is connected between the second node Q22 and the third node Q23. The first resistor R21 is connected between the third node Q23 and the output terminal OUT. A third NMOS transistor N23 driven in accordance with the third capacitor C23 and the second control signal KICKb is connected in parallel between the output terminal OUT and the ground terminal Vss. Here, the first control signal KICK is a kick signal for instantaneously applying a high voltage, and the second control signal KICKb is an inverted signal of the first control signal KICK.

The driving method of the precharge circuit according to the present invention configured as described above is as follows.

When the first control signal KICK is applied in a high state, the first NMOS transistor N21 is turned on and the second PMOS transistor P22 is turned off. Since the potential of the first node Q21 drops to the ground potential through the turned-on first NMOS transistor N21, the first PMOS transistor P21 is turned on. The power supply voltage Vcc is supplied to the fourth node Q24 through the turned on first PMOS transistor P11. The first capacitor C24 is occupied by the power supply voltage Vcc supplied to the fourth node Q24. On the other hand, the charges charged in the first capacitor C11 are discharged to the fourth node Q24 by the second control signal KICKb applied in the low state. Therefore, the fourth node Q24 maintains a potential of 2 Vcc. The second NMOS transistor N22 is turned on by the potential of the fourth node Q24 that maintains a high voltage of 2 Vcc. The power supply voltage Vcc is supplied to the second node Q22 through the turned-on second NMOS transistor N22 and occupies a charge in the second capacitor C22. On the other hand, the second control signal KICKb applied in the low state is inverted to the high state through the first inverter I21, and this signal transfers the charges occupied by the second capacitor C22 to the second node Q22. By discharge, the second node Q22 maintains a potential of 2 Vcc. When the switching signal is applied while the second node Q12 maintains a potential of about 2 Vcc, the third PMOS transistor P13 is turned on by the switching bar signal SWb, and the potential of the second node Q12 is changed to third. It is output to the output terminal OUT through the node Q23.

When the first control signal KICK is applied in a low state, the first NMOS transistor N21 is turned off and the second PMOS transistor P22 is turned on. The potential of the fourth node Q24 that maintains the high potential through the turned on second PMOS transistor P22 becomes equal to the potential of the first node Q21. Therefore, the fourth node Q24 maintains a high voltage of about 2 Vcc, and the second NMOS transistor N22 is turned on by this potential to supply the power supply voltage Vcc to the second node Q22. However, since the second control signal KICKb is applied in a high state and inverted to a low state through the first inverter I21, the second capacitor C22 may not be driven. Therefore, the second node Q22 maintains the potential of the power supply voltage Vcc, and this potential is not output to the output terminal OUT because the switching signal is not applied and the third PMOS transistor P23 is not operated.

As described above, the precharge circuit according to the present invention generates a high voltage of about 2 Vcc, and operates the NMOS transistor by the high voltage, thereby stably supplying the power supply voltage Vcc without a voltage drop as much as the threshold voltage of the NMOS transistor. . In addition, the size of the PMOS transistor of the precharge circuit can be reduced by about 10 times or more by the NMOS transistor, thereby improving the loading of the PMOS transistor.

Claims (8)

A first PMOS transistor and a first NMOS transistor for complementarily operating in accordance with the first control signal to adjust the potential of the first node; A second PMOS transistor for supplying a power supply voltage to a second node according to the potential of the first node; A first capacitor configured to charge a power supply voltage supplied to the second node, discharge a charge charged according to a second control signal, and raise a potential of the second node to a predetermined potential; A second NMOS transistor for supplying a power supply voltage to a third node according to the potential of the second node raised to the predetermined potential; And a second capacitor configured to charge the power supply voltage supplied to the third node, discharge the charged charge according to the inversion signal of the second control signal, and raise the potential of the third node to a predetermined potential. A precharge circuit characterized by the above-mentioned. delete delete 2. The precharge circuit according to claim 1, wherein the second PMOS transistor is connected between a power supply terminal and the second node and driven according to the potential of the first node. The precharge circuit according to claim 1, wherein the first capacitor is connected between the second node and the second control signal input terminal. 2. The precharge circuit according to claim 1, wherein the second NMOS transistor is connected between the power supply terminal and the third node and driven according to the potential of the second node. 2. The precharge circuit according to claim 1, wherein the second capacitor is connected between the third node and the inverting means for inverting the second control signal. delete