KR100335780B1 - Negative boosting circuit - Google Patents

Abstract

The present invention relates to a negative boosting circuit, comprising: charge storage means connected to an output node, first means for adjusting the potential of the output node in accordance with first and second control signals, and in accordance with the second control signal A second means for charging a charge in the charge storage means, and a third means for adjusting the potential of the output node in accordance with the potential of the output node. By applying a negative bias of Vtn |, a negative boosting circuit is proposed that can prevent leakage of current and improve the operation reliability of the device.

Description

Negative boosting circuit

The present invention relates to a negative boosting circuit, and more particularly, to a negative boosting circuit that can reduce leakage current by applying a voltage of-| Vtn | to a word line that is not selected when performing a read operation on a flash memory device.

When a read operation is performed on a conventional flash memory device, as shown in the waveform diagram of FIG. 1A, a read voltage V _R is applied to a selected word line, and the remaining word lines of FIG. As can be seen from the waveform diagram, the ground voltage is applied.

However, even in this case, even if the erased cell is detected after the erase operation is performed and the recovery operation is performed through the result, the leakage current increases due to the cell characteristics. Thus, the read operation as well as the program verification operation have a very bad effect. There is a problem.

Accordingly, an object of the present invention is to provide a negative boosting circuit that can reduce leakage current by applying a voltage of about-| Vtn | to a word line that is not selected.

The present invention for achieving the above object is the charge storage means connected to the output node, the first means for adjusting the potential of the output node in accordance with the first and second control signals, and in accordance with the second control signal And second means for charging the charge storage means and third means for adjusting the potential of the output node according to the potential of the output node.

1 (a) and 1 (b) are graphs showing biases applied to conventionally selected and unselected word lines.

2 (a) and 2 (b) are graphs showing biases applied to selected and unselected word lines according to the present invention.

3 is a circuit diagram of a negative boosting circuit for applying a negative voltage to an unselected word line in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

11: NOR gates I11 to I17: first to seventh inverters

P11 to P13: first to third PMOS transistors

N11 to N15: first to fifth NMOS transistors

C11 and C12: first and second capacitor

Q11 to Q14: first to fourth nodes

The present invention will be described in detail with reference to the accompanying drawings.

2 (a) and 2 (b) are waveform diagrams showing voltages applied to selected word lines and non-selected word lines, which are shown to illustrate the concept of the present invention.

In the present invention, the read voltage V _R is applied to the selected word line as shown in FIG. 2 (a), and the bias of-| Vtn | is applied to the unselected word line as shown in FIG. In other words, applying a voltage of about -0.3V reduces the bit line leakage current.

In general, when reading a flash memory device, the bit line leakage current is caused by a subthreshold current, so the amount of current has an exponential function. Therefore, a negative 0.1 V transition of gate bias can theoretically reduce leakage current by about 10 times.

An X-decoder and a sector decoder are configured as a means for controlling the word line of the flash memory device, and the sector decoder is composed of a circuit for switching a positive high voltage and a circuit for switching a negative high voltage.

In the present invention, the negative boosting circuit is connected to the negative voltage switching circuit which controls the low voltage level of the word line.

3 is a circuit diagram of a negative boosting circuit according to the present invention, and is configured as follows.

The enable signal EN is inverted through the first inverter I11 to drive the PMOS side of the transfer gate M11. The second inverter I12 inverts the output signal of the first inverter I11 to drive the NMOS side of the transfer gate M11, and the second PMOS transistor P12 connected between the power supply terminal and the first node Q11. ). The third PMOS transistor P13 connected between the power supply terminal and the fourth node Q14 is driven according to the potential of the first node Q11, and the transfer gate M11 removes the potential of the first node Q11. Transmit to 2 node Q12. The first PMOS transistor P11 connected between the power supply terminal and the second node Q12 is driven according to the potential of the second node Q12. Between the second node Q12 and the ground terminal Vss, the first NMOS transistor N11, which is a native transistor driven according to the reference voltage Vref, and the second NMOS driven according to the sleep signal sleep. The transistor N12 is connected in series. The NOR gate 11 inputs an enable signal EN and a boosting signal boost and logically combines them. The third and fourth inverters I13 and I14 delay the output signal of the NOR gate 11 to determine the potential of the third node Q13. The third NMOS transistor N13, which is a native transistor connected between the fourth node Q14 and the ground terminal Vss, is driven according to the potential of the third node Q13. The fifth NMOS transistor N15, which is a native transistor connected between the fourth node Q14 and the ground terminal Vss, is driven in accordance with the potential of the third node Q13. The fourth NMOS transistor N14 connected between the fourth node Q14 and the ground terminal Vss is driven according to the potential of the fourth node Q14. The fifth to seventh inverters I15 to I17 invert the delay of the boost signal and charge the second capacitor C12 according to the potential of the boost delayed boost signal boost.

Referring to the driving method of the negative boosting circuit according to the present invention configured as described above are as follows.

Since the enable signal EN is applied in the low state because it is applied to the unselected word lines, an operation when the boosting signal boost is applied in the low state will be described.

The enable signal EN applied in the low state is inverted to the high state through the first inverter I11 to turn off the PMOS side of the transfer gate M11. In addition, the signal inverted to the high state through the first inverter I11 is inverted to the low state through the second inverter I12. The second PMOS transistor P12 is turned on by the output signal of the second inverter I12 maintaining the low state, and turns off the NMOS side of the transfer gate M11. The power supply voltage Vcc is applied to the first node Q11 through the turned-on second PMOS transistor P12 to maintain the high state of the first node Q11, and thus the third PMOS transistor P13 is turned on. Is off. Meanwhile, the first NMOS transistor N11 driven according to the reference voltage Vref is turned on, and the second NMOS transistor N12 driven according to the sleep signal sleep is turned off so that the second node Q12 is turned off. The potential of Vcc-Vtp is maintained.

The NOR gate 11 receives the enable signal EN in the low state and the boosting signal boost in the low state to output a high state signal. The high state signal is delayed through the third and fourth inverters I13 and I14 to turn on the third and fifth NMOS transistors N13 and N15. Accordingly, the fourth node Q14 remains low, and accordingly, the fourth NMOS transistor N14 is turned off. In addition, the boosting signal boost in the low state is inverted and delayed through the fifth to seventh inverters I15 to I17 to become a high state, and electric charges are stored in the second capacitor C12 by the potential of the signal. However, the fourth node Q14 remains low because the third and fifth NMOS transistors N13 and N15 do not affect the fourth node Q14 that is held low.

A driving method in the case where the boosting signal transitions to the high state in the above state will be described.

The NOR gate 11 inputs an enable signal EN in a low state and a boosting signal boost in a high state to output a low state signal. The low state signal is delayed through the third and fourth inverters I13 and I14 to turn off the third and fifth NMOS transistors N13 and N15. In addition, the boosting signal boost in the high state is inverted and delayed through the fifth to seventh inverters I15 to I17 to become a low state, and this potential becomes the potential of the fourth node Q14. However, while the potential of the fourth node Q14 remains low, the potential of the fourth node Q14 is negatively boosted by ΔV by the seventh inverter I17 serving as a clock divider due to the coupling by the second capacitor C12. Also, excessively negative boosted bias can affect the X-decoder behavior. In this case, if the negative boosting is strong, the fourth node Q14 can go down as much as-| Vtn | because the fourth NMOS transistor N14 is turned on to extract charges from the ground terminal.

In the case of the currently used model parameter, since the threshold voltage of the fourth NMOS transistor N14 is 0.3V, the potential of the fourth node Q14 is determined by this potential without falling below -0.3V.

This negatively boosted bias transitions the level of the X-decoder from the ground voltage level to -0.3V through the negative voltage switch, causing -0.3V to be applied to all unselected word lines.

As a result, applying a negative bias to the gate terminals of all cells that share the same bitline other than the readout cell will significantly improve the leakage current at the bitline of the unselected cells, which adversely affects the operation of the sense amplifier. Can be.

As described above, according to the present invention, when a negative bias is applied to an unselected word line during a read operation of a flash memory device, malfunctions due to leakage current from the unselected cells can be suppressed to the maximum, thereby improving the operation of the device. Can be.

Claims (6)

Charge storage means connected to the output node, First means for adjusting the potential of the output node in accordance with first and second control signals; Second means for charging charge in the charge storage means in accordance with the second control signal; And a third means for adjusting the potential of the output node in accordance with the potential of the output node. 2. The apparatus of claim 1, wherein the first means comprises: a NOR gate for logically combining the first and second control signals; Delay means for delaying the output of the NOR gate; And first and second switching means for bringing the potential of said output node to ground potential in accordance with the output signal of said delay means. 3. The negative boosting circuit according to claim 2, wherein said first switching means is an NMOS transistor connected between an output node and a ground terminal. 3. The negative boosting circuit according to claim 2, wherein said second switching means is a native NMOS transistor connected between an output node and a ground terminal. 2. The negative boosting circuit according to claim 1, wherein said second means is an inversion delay means composed of a plurality of inverters. 2. The negative boosting circuit according to claim 1, wherein said third means is a native NMOS transistor connected between said output node and a ground terminal and driven according to a potential of said output node.