KR100295807B1 - Dynamic cmos circuit - Google Patents

Abstract

PURPOSE: A dynamic CMOS circuit is provided to secure a stable self-reset operation regardless of a delay time for determining a pulse width of an output signal and regardless of a period and a pulse width of an input signal. CONSTITUTION: The first connection node(N10) has a reference voltage. The second connection node(T2) is pre-charged by a plurality of charges to have a pre-charge state of a pre-charge voltage, and outputs the charged charges to have a discharge state of a discharge voltage. A pre-charge circuit(16) is connected to the second connection node, and supplies the charges to the second connection node. A path forming circuit(12) is connected to the second connection node, and provides a conductive path for the charges supplied from the second connection node. A discharge circuit(14) is connected to the path forming circuit and the reference connection node. The discharge circuit receives a logic signal, and discharges to the reference connection node the plurality of charges from the precharge connection node through the conduction path of the path forming circuit in response to the logic signal. A self-reset circuit maintains the discharge state for a predetermined time when the second connection node is discharged, and then pre-charges the second connection node regardless of an input of the logic signal. The self-reset circuit sets the logic circuit to a standby state, before the logic signal corresponding to a next cycle is input, regardless of a duration of the discharge state.

Description

Dynamic CMOS Circuits {DYNAMIC CMOS CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a dynamic metal oxide semiconductor (CMOS) circuit that provides a high speed output response.

Typically, static random access memory (SRAM). Volatile memory devices, such as dynamic random access memory (DRAM), essentially perform an access operation that reads data stored in a memory cell or writes external data into the memory cell in response to a timing of a signal applied from the outside. Perform. Memory cell arrays (not shown) are activated by activating word lines and bit lines corresponding to arbitrary row addresses and column addresses in order to read and store data stored in the memory cells during the read operation. Allow one memory cell within) to be selected. It is well known that data of the selected memory cell is output to the outside through the sense amplifier circuit and the data output buffer.

In the design of high speed CMOS logic, it is desirable to use NMOS devices to perform logic and to use PMOS devices as a load to eliminate power consumed in the standby state. In dynamic CMOS logic, internal nodes of the logic tree are first precharged to the supply voltage and then selectively discharged depending on the state of the input signal applied to the logic circuit.

Since pre-charge operation for all gates in the chip is generally performed simultaneously, the pre-charge surge current tends to be very high. Dynamic CMOS logic, which is automatically reset, does not reset multiple logic trees simultaneously, so that pre-charge operations for the logic trees are distributed over time.

Increasingly, as the system speed is gradually increased, the speed of the semiconductor chip is required to be fast. Therefore, the system itself is synchronized, and the tendency to design the chip using an external clock signal or an internally generated clock signal is gradually dominant.

In general, it is well known that a CMOS inverter circuit used as a data transfer element is composed of a PMOS transistor and an NMOS transistor. Thus, when its input data goes high or low level, the CMOS inverter circuit not only charges the output capacitive loading, but also grounds from the PMOS transistor to the NMOS transistor, i.e., at the supply voltage VCC. Direct current flows to the potential GND.

This phenomenon can not tilt the logic threshold voltage (hereinafter referred to as Vth) of the inverter circuit in either direction because the data must be transferred quickly at both high and low levels. As a result, the CMOS inverter circuit of the circuit configuration described above is inadequate for transferring data at high speed.

However, according to a recent design technique, the transfer speed can be improved by biasing the logic threshold voltage in either direction and reducing the gate capacitance of either the PMOS transistor or the NMOS transistor. In other words, it is a dynamic circuit that can be delivered at high speed by tilting the logic threshold voltage in one direction and reducing gate capacitance and DC current.

Generally, the dynamic circuit consists of one transistor that is controlled at the input and another transistor that is automatically reset by an external or its output / input. The dynamic circuit has a self-reset circuit for self-resetting the other transistor using its output signal. 1 is a circuit diagram illustrating a dynamic CMOS circuit according to the related art, and FIGS. 2 and 3 are operation timing diagrams according to the related art.

The pulse width of the signal OUT output from the dynamic CMOS circuit is determined by the reset circuit 1 including the delay circuit 2. As is well known, the dynamic circuit of FIG. 1 according to the related art is known that when the input signal IN is discharged from the precharge state, that is, from the low level to the high level, the output signal OUT is also fast. The battery is discharged from a low precharge state.

Then, the output signal OUT is discharged in a discharge state after a predetermined time has elapsed (e.g., the time at which the output signal is fed back to the NMOS transistor, Q, through the reset circuit 1 including the delay circuit 2). You will be in precharge again. The precharged output signal (low or high level) is then fed back through the delay path to reset the other transistor (eg, NMOS transistor-Q in FIG. 1) to an input standby state. This series of processes is called a self-reset operation or a restore operation.

If the time at which the NMOS transistor Q is reset becomes late (e.g., when the characteristics of the MOS transistors constituting the delay path change due to process changes or other factors), as shown in Figs. 2 and 3, Since the node N5 is not set to the high level of the input standby state and remains at the low level, the node N5 cannot receive the input signal IN of the next period.

As such, the reset time is long because it feeds back the precharged output signal through the delay path for determining the pulse width. That is, when the delay time for determining the desired pulse width is changed due to process changes and other factors, the pulse width corresponding to the fed back time is compared with the pulse width corresponding to the desired time when the characteristics of the elements constituting the delay path change. Because it is longer.

Thus, the dynamic circuit according to the related art results in a failure to perform a true self-reset operation. This problem may be caused more seriously as the input period of the input signal IN is shorter (or at a higher operating speed).

Accordingly, an object of the present invention is to provide a dynamic CMOS circuit that guarantees stable self-reset operation regardless of the period of the input signal and the delay time for determining the pulse width of the input signal and the pulse width of the output signal in a semiconductor device requiring high speed operation. To provide.

1 is a circuit diagram showing a dynamic CMOS circuit according to the related art.

2 and 3 are timing diagrams of operations according to the related art.

4 is a circuit diagram showing a dynamic CMOS circuit according to a preferred embodiment of the present invention.

5 is an operation timing diagram according to the present invention.

6 through 8 are circuit diagrams showing modifications of the present invention.

<Description of the symbols for the main parts of the drawings>

24: delay circuit 100: self-reset circuit

[Configuration]

According to one aspect of the present invention for achieving the above object, there is provided an apparatus having a high speed dynamic CMOS circuit, comprising: a first connection point having a reference voltage; A second connection point which receives a plurality of charges and is precharged in a precharge state having a precharge voltage, and is discharged in a discharge state having a discharge voltage by outputting the plurality of charges; A precharge circuit connected to said second connection point for providing said plurality of charges to said connection point; A path forming circuit connected to the second connection point for providing a conductive path for the plurality of charges output from the connection point; Connected to the path forming circuit and the reference connection point, receiving a logic signal and discharging a plurality of charges output from the precharge connection point through the conductive path of the path forming circuit to the reference connection point according to the logic signal. A discharge circuit for; When the second connection point is discharged to the discharge state, the second connection point is freed regardless of the input of the logic signal after maintaining the discharge state for a predetermined time to determine the duration of the discharge state. A self-reset circuit for precharging to a charge state, and then setting the logic circuit to a standby state before inputting the logic signal corresponding to the next cycle regardless of the duration of the discharge state; It is characterized by including.

[apply]

With such a device, a stable self-reset operation can be ensured by allowing the operation for determining the pulse width of the output signal and the operation for self-reset to be determined by different paths.

EXAMPLE

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 8 according to an embodiment of the present invention.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details.

Referring to FIG. 4, the novel dynamic CMOS circuit of the present invention includes a self-reset circuit 100, which before the input signal IN is activated again within the next cycle. The precharge operation for maintaining the operation standby state of the NMOS transistor 14 can be performed regardless of the delay time of the delay path. That is, while the output signal is fed back first, it passes through a delay path for determining the pulse width, while the second fed back output signal passes through another path not passing through the delay path. You can quickly get the input waiting state. As a result, it is possible to ensure stable self-reset operation regardless of the period of the input signal and the delay time for determining the pulse width of the input signal and the pulse width of the output signal in the semiconductor device requiring high speed operation.

A circuit diagram showing a dynamic CMOS circuit according to a preferred embodiment of the present invention is shown in FIG. And, the operation timing diagram according to the present invention is shown in FIG. The present invention provides a different path that does not go through the delay circuit in the self-reset operation, so that the NAND gate 26 is prevented from being delayed due to the delay path (or delay time) in the self-reset operation. Added to the circuit diagram according to the related art of FIG. 1. That is, in the self-reset circuit 100, one of the two inputs of the NAND gate 26 is directly connected to the output node T2 and the other input is connected to the output node T2 through the delay circuit 24. Connected. The output of the NAND gate 26 is connected to the gate of the NMOS transistor 34. Hereinafter, the operation according to the present invention will be described in detail with reference to Figs.

First, while the input signal IN is maintained at the low level, the nodes N10 and T2 are precharged to the high level and the low level through the transistors 10 and 20, respectively. And assuming that node N16 is charged to a high level, PMOS transistor 16 is non-conductive and NMOS transistor 14 is conductive.

Then, under such assumptions, when the input signal IN transitions from low level to high level, the NMOS transistor 12 is challenged and the node N10 transitions from the high level in the precharge state to the low level. As node N10 transitions to a low level, PMOS transistor 18, which is larger in size than NMOS transistor 20, is conductive. As a result, as shown in FIG. 5, the output signal OUT quickly transitions from the low level of the precharge state to the high level. That is, although not shown in the drawings, it is obvious to those who have acquired the general knowledge in this field, but drives the large load of the next stage connected to the output terminal T2 to a high level.

Subsequently, the self-reset circuit 100 having received the level of the output node T2, as is well known, has a PMOS transistor after a predetermined time has elapsed to determine (secure) the pulse width of the output signal OUT. (16) and non-conductive NMOS transistor 14. This will be described in more detail as follows.

The NAND gate 26 in which one input terminal is directly connected to the output terminal T1 has its output determined by the other input terminal because the level of the output signal OUT is high. Therefore, after a predetermined time has elapsed, i.e., after the time required by the delay circuit 24 (time for determining the duration of the output signal) has elapsed, the level of the other input terminal transitions from a low level to a high level. Accordingly, node N12 transitions from a high level to a low level, and nodes N14 and N16 sequentially transition to a high level and a low level, respectively. Eventually, the NMOS transistor 14 of the transistors 14 and 16 controlled at the node N16 is unconducted and the PMOS transistor 16 is conductive so that the node N10 is again at a low level to a high level. Precharged. Subsequently, the output terminals T2 are also precharged again from the high level to the low level by the transistors 20 and 22. As a result, the output signal OUT is output with the desired pulse width.

Thereafter, the feedback of the precharged output node T2 is fed back to set the NMOS transistor 14 into an input standby state, that is, a conductive reset state, and to set the PMOS transistor 16 to a non-conductive state, respectively. A reset operation is performed.

As described above, because one of the input terminals of the NAND gate 26 is connected to the delay circuit and the other is directly connected to the output node T2, again by the low level of the precharged output signal The output of the NAND gate 26 transitions from the low level to the high level regardless of the output of the delay circuit 24. As a result, the PMOS transistor 30 is non-conductive and the NMOS transistor 34 is conductive.

At this time, when the input signal IN is in an active state, that is, maintained at a high level, the NMOS transistor 32 is not electrically conductive through the inverter 28. In this way, a malfunction in which the self-reset operation is performed while the input signal IN is provided can be prevented. In contrast, when the input signal IN is previously deactivated, the node N12 transitions from the low level to the high level, and the nodes N14 and N16 sequentially transition to the low level and the high level, respectively.

Accordingly, the PMOS transistor 16 of the transistors 14 and 16 controlled at the node 16 is non-conductive and the NMOS transistor 14 is conductive. In other words, the self-reset operation is completed in the input standby state for receiving the input signal of the next cycle. At this time, the NMOS transistor 22 is unconducted by the high level of the node 16 through the inverter 40.

As described above, the operation for determining (or securing) the duration of the output signal OUT by using the NAND gate 26 and the operation for self-resetting are determined by different feedback paths. That is, an operation for determining (obtaining) the duration of the output signal is performed through a delay path and an operation for self-resetting is performed through a path without a delay circuit. By such a self-reset circuit, a stable self-reset operation is performed even if the elements constituting the delay path change the delay time due to process change or other factors. For example, as long as the delay time is within the operating cycle, the self-reset circuit according to the present invention can ensure stable self-reset operation. Because, the basic cycle time according to the present invention is limited to the output terminal from the discharge state to the precharge state again, unlike the related art (limited to the time passed through the delay path in the precharged state again). .

Conversely, even if the delay time is small compared to the required duration, it is apparent to those skilled in the art that the self-reset circuit according to the present invention can ensure stable self-reset operation. For example, a stable self-reset operation can be performed even if the operation cycle is shortened. When the dynamic CMOS circuit according to the present invention is used, not only the decoding path of the semiconductor memory device can be realized as the dynamic circuit, but also it can be applied to various other fields.

6 to 8 are circuit diagrams showing modifications of the present invention. The self-reset circuit provided in the dynamic circuit shown in FIGS. 6-8 provides the two different paths described in FIG. 4 in the same way. As a result, it is modified in that of FIG. 4 to adjust the internal logic state but has the same effect as that of FIG. Here, description of them is omitted in order to avoid duplication of description.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, a stable self-reset operation can be ensured by allowing the self-reset operation to be performed regardless of the delay time by the delay path for determining the pulse width of the output signal when the output signal is precharged again. have. In addition, the devices constituting the delay path may ensure a stable reset operation regardless of a delay time, that is, a pulse width or a short period of an input signal due to process change or other factors.

Claims (26)

A device having a high speed dynamic CMOS circuit, the apparatus comprising: a first connection point having a reference voltage; A second connection point receiving a plurality of charges and being precharged in a precharge state having a precharge voltage, and outputting the plurality of charges to be discharged in a discharge state having a multicharge voltage; A precharge circuit connected to said second connection point for providing said plurality of charges to said connection point; A path forming circuit connected to the second connection point and providing a conductive path for the plurality of charges output from the connection point; Connected to the path forming circuit and the reference connection point, receiving a logic signal and discharging a plurality of charges output from the precharge connection point through the conductive path of the path forming circuit to the reference connection point according to the logic signal. A discharge circuit for; When the second connection point is discharged to the discharge state, the second connection point is freed regardless of the input of the logic signal after maintaining the discharge state for a predetermined time to determine the duration of the discharge state. A self-reset circuit for precharging to a charge state and then setting the logic circuit to a standby state before inputting the logic signal corresponding to the next cycle regardless of the duration of the discharge state; Apparatus comprising a. 2. The apparatus of claim 1, wherein the reference voltage has a level of ground voltage when the activation state of the logic signal is a level of a power supply voltage. 3. The apparatus of claim 2, wherein the precharge circuit comprises a PMOS transistor having a gate to which the logic signal is applied, a source to which the power supply voltage is applied, and a drain connected to the first connection point. 3. The apparatus of claim 2, wherein the precharge circuit comprises a PMOS transistor having a gate to which the ground voltage is applied, a source to which the power supply voltage is applied, and a drain connected to the first connection point. 4. The apparatus of claim 3, wherein the path forming circuit comprises a first NMOS transistor having a drain connected to the first connection point, a source connected to the discharge circuit, and a gate connected to the self-reset circuit. 6. The discharge circuit of claim 5, wherein the discharge circuit includes a second NMOS transistor having a gate to which the logic signal is applied, a drain connected to a source of the first NMOS transistor, and a source connected to the ground voltage. Device. 3. The apparatus of claim 2, wherein the self-reset circuit comprises: a combining circuit for accepting the output state of the delay circuit and the state of the second connection point and combining the two states; A PMOS transistor coupled to the second connection point and controlled at the output of the combination circuit to perform the latter precharge operation. 8. The NOR gate according to claim 7, wherein the combination circuit has two input terminals and one output terminal, wherein the one input terminal is connected to the output of the delay circuit and the other input terminal is connected to the second connection point. And; And an inverter coupled to the output of the NOR gate. 8. The self-resetting circuit of claim 7, wherein the self-reset circuit further comprises a blocking circuit for preventing the precharge operation corresponding to the latter while the logic signal is kept active. Device. 10. The circuit of claim 9, wherein the blocking circuit comprises: an inverter for inverting the logic signal; Each having a source, a drain, and a gate, comprising one PMOS transistor and two NMOS transistors sequentially connected in series between the power supply voltage and the ground voltage; The gate of the PMOS transistor and the gate of the NMOS transistor arranged close to the ground voltage are connected to the combination circuit and the gate of the NMOS transistor close to the PMOS transistor is connected to the inverter. 10. The apparatus of claim 9, wherein the self-reset circuit has two inverters latched to each other and additionally includes a latch circuit for latching a signal applied to the PMOS transistor. 2. The apparatus of claim 1, wherein the reference voltage has a level of a power supply voltage when an activation state of the logic signal is a level of ground voltage. 13. The apparatus of claim 12, wherein the precharge circuit comprises an NMOS transistor having a gate to which the logic signal is applied, a source to which the ground voltage is applied, and a drain connected to the first connection point. 15. The apparatus of claim 13, wherein the path forming circuit includes a first PMOS transistor having a drain connected to the first connection point, a source connected to the discharge circuit, and a gate connected to the self-reset circuit. 15. The device of claim 14, wherein the discharge circuit comprises a second PMOS transistor having a gate to which the logic signal is applied, a drain connected to a source of the first PMOS transistor, and a source connected to the power supply voltage. Device. 13. The apparatus of claim 12, wherein the self-reset circuit comprises: a combining circuit for accepting the output state of the delay circuit and the state of the second connection point and combining the two states; An NMOS transistor coupled to the second connection point and controlled at the output of the combination circuit to perform the latter precharge operation. 17. The NOR gate according to claim 16, wherein the combination circuit has two input terminals and one output terminal, wherein the one input terminal is connected to the output of the delay circuit and the other input terminal is connected to the second connection point. And; And an inverter coupled to the output of the NOR gate. 17. The apparatus of claim 16, wherein said self-reset circuit further comprises a blocking circuit for preventing a precharge operation corresponding to said latter while said logic signal remains active. Device. 19. The circuit of claim 18, wherein the blocking circuit comprises: an inverter for inverting the logic signal; Each having a source, a drain, and a gate, comprising two PMOS transistors and one NMOS transistor sequentially connected in series between the power supply voltage and the ground voltage; And a gate of the PMOS transistor arranged close to the power supply voltage and a gate of the NMOS transistor are connected to the combination circuit, and a gate of the PMOS transistor close to the NMOS transistor is connected to the inverter. 19. The apparatus of claim 18, wherein the self-reset circuit has two inverters latched to each other and additionally includes a latch circuit for latching a signal applied to the NMOS transistor. 9. An apparatus having a high speed dynamic buffer circuit, said dynamic buffer circuit comprising: a first connection point having a reference voltage; A second connection point receiving a plurality of charges and being precharged in a precharge state having a precharge voltage, and outputting the plurality of charges and discharged in a discharge state having a discharge voltage; A precharge circuit connected to said second connection point for providing said plurality of charges to said connection point; A path forming circuit connected to the second connection point and providing a conductive path for the plurality of charges output from the connection point; Connected to the path forming circuit and the reference connection point, receiving a logic signal and discharging a plurality of charges output from the precharge connection point through the conductive path of the path forming circuit to the reference connection point according to the logic signal. A discharge circuit for; An output terminal connected to the second connection point via a single inverter; The second connection point and the inverter regardless of input of the logic signal after maintaining the discharge state for a predetermined time to determine the duration of the discharge state when the second connection point is discharged to the discharge state Precharges the output terminal to the precharge state, and then puts the logic circuit into an operation standby state before the logic signal corresponding to the next cycle is input regardless of the duration of the discharge state. And a self-reset circuit for setting. 22. The apparatus of claim 21, wherein the self-reset circuit comprises: a delay circuit coupled to the output terminal and configured to determine a duration of the discharge state; A combining circuit for receiving the output state of the delay circuit and the state of the output terminal and combining the two states; A PMOS transistor coupled to the second connection point and controlled at the output of the combination circuit to perform the latter precharge operation. 23. The NAND gate of claim 22, wherein the combination circuit has two input terminals and one output terminal, the NAND gate having one input terminal connected to an output of the delay circuit and the other input terminal connected to the output terminal. Apparatus comprising a. 23. The apparatus of claim 22, wherein said self-reset circuit further comprises a blocking circuit for preventing a precharge operation corresponding to said latter while said logic signal remains active. Device. 25. The circuit of claim 24, wherein the blocking circuit further comprises: an inverter for inverting the logic signal; Each having a source, a drain, and a gate, comprising one PMOS transistor and two NMOS transistors sequentially connected in series between the power supply voltage and the ground voltage; And the gate of the NMOS transistor arranged close to the gate of the PMOS transistor and the ground voltage is connected to the combination circuit and the gate of the NMOS transistor close to the PMOS transistor is connected to the inverter. 25. The apparatus of claim 24, wherein the self-reset circuit has two inverters latched to each other and additionally includes a latch circuit for latching a signal applied to the PMOS transistor.

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