KR100347143B1 - Apparatus for generating y-address in graphic memory - Google Patents

Abstract

The present invention relates to a device for generating a wire dress in a graphic memory. In the prior art, when a defect occurs among selected cells when a block write command is executed in a graphic memory and a redundancy address is to be used, the redundancy address and the pre-decoder section are used. Since the output is generated by comparing the output, the redundancy wire dress enable signal has a long series of paths for generating the redundancy wire dress enable signal, thereby reducing the operation speed of the entire system. Accordingly, the present invention has been made to solve the above-mentioned conventional problems. When the block write command is used when a redundancy address is used because a defect occurs among selected cells when the block write command is executed in the graphic memory, Accordingly, the address_counting signals (ca) [0: 2] and (ca) [3: k], which are divided into lower and upper levels by counting external addresses, are input, and the redundancy_address signals (cra) [ 0: 2], (cra) [3: k], and the result of the comparison and the normal_wireless_enable signal (YSE) and redundancy_ through the path selected by the block write control signal (BLWT). By controlling the driver by generating the wire dress enable signal YRE, it is possible to eliminate the delay that occurs during signal transmission, thereby enabling high-speed operation by improving the processing speed of the entire system.

Description

Wire dressing device in graphic memory {APPARATUS FOR GENERATING Y-ADDRESS IN GRAPHIC MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generating apparatus. In particular, an address_counting signal (ca) [0: k] counting an external address and an input redundancy_address signal (cra) in a graphic memory according to whether a block write command is input [0: k] is separated into an upper address and a lower address, and the normal_wireless_enable signal YSE and the redundancy_wire are made through the comparison result and the path selected by the block write control signal BLWT. The present invention relates to a device for generating a wire dress in a graphics memory which generates a dress_enable signal (YRE) and controls a driver, thereby eliminating a delay element occurring during signal transmission.

FIG. 1 is a block diagram showing the configuration of a wire dress generation apparatus in a conventional graphic memory. As shown in FIG. 1, an external address signal Ext_ADDR [0: i] and input data DI [0: j] are buffered, respectively. First and second input buffer units 1a and 1b; First and second latch parts 2a and 2b for latching the outputs of the respective input buffer parts 1a and 1b according to a clock signal CLK; A counter (3) counting the output of the first latch unit (2a) and outputting the address_counting signal (ca) [0: k]; A data signal generator 4 controlled by a block write control signal BWLT and outputting the output of the second latch unit 2b as a data signal cam [0: 7]; The pre_decoding signal is decoded by decoding the address_counting signal ca [0: k] of the counter 3 or the data signal cam [0: 7] of the data signal generator 4 according to whether or not a block write command is issued. a pre-decoder section 5 outputting (ay) [0: 7]; The redundancy_address signal cra [0: k] is controlled by the normal_wire dress_generation signal YSEI, and the address_counting signal ca [0: k] and the pre-decoder 5 are free. An address comparator 6 for outputting the redundancy_wire dress_enable signal YRE and the normal_wire dress_enable signal YSE in comparison with the decoding signal ay [0: 7]; A delay unit 7 for delaying the normal_wire dress_generation signal YSEI for a predetermined time; The redundancy select signal RYSI is output by performing an AND operation on the redundancy-wire dress enable signal YRE of the address comparison unit 6 and the normal_wire dress generation signal YSEI delayed by the delay unit 7. And AND gate AD1; The normal_wire signal_enable signal YSE of the address comparison section 6 and the pre_decode signal ay [0: 7] of the pre-decoder section 5 are ANDed to perform a normal_selection signal YSEO. And an AND gate AD2 for outputting; A driver 8 for latching the outputs RYSI and YSEO of the AND gates AD1 and AD2 and outputting them as delayed redundancy select signal RYSID and delayed normal select signal YSEOD; It consists of a Y-decoder section 9 which decodes the outputs RYSID and YSEOD of the driver 8 and outputs them as a redundancy_wiredress_selection signal RYS and a normal_wiredress_selection signal NYS.

The address comparison section 6 compares the pre_decoding signal ay [0: 7] with the redundancy_address signal cra [0: 2] decoded by 8 bits in the 8-bit decoder 6a. A first comparator 6b for outputting a first redundancy wire dress enable signal YRE00; Second comparison unit 6c for outputting second redundancy_wireless_enable signal YRE01 by comparing address_counting signal ca [3: k] with redundancy_address signal cra [3: k]. )Wow; A signal input unit 6e that receives the normal_wire dress_generation signal YSEI and maintains a predetermined level and outputs the same; The normal selector 6d, which is controlled by the outputs of the first and second redundancy_wire dress_enable signals YRE00 and YRE01 and the signal input unit 6e, and outputs a normal_wireless_enable signal YSE. )Wow; And a redundancy selector 6f which is controlled by the first and second redundancy_wiredress_enable signals YRE00 and YRE01 and outputs a redundancy_wiredress_enable signal YRE. The operation of the conventional apparatus will be described.

First, the external address signal Ext_ADDR [0: i] and the input data DI [0: j] are buffered in the first and second input buffer units 1a and 1b to move from the external input range to the internal input range. And then latched in the first and second latch portions 2a and 2b in accordance with the clock signal CLK.

When a block write command is input from the outside, a block write control signal BWLT is generated, and the data signal generator 4 is controlled by the block write control signal BWLT to control the data. The output of the two latches 2b is output as a data signal cam [0: 7].

On the other hand, the counter 3 counts the output of the first latch unit 2a and outputs an address_counting signal (ca) [0: k]. When the block write command is input, the pre-decoder unit 5 Decodes according to the input data signal cam [0: 7] of the input data signal generator 4 while ignoring the address counting signal ca [0: k].

That is, when the block write operation is not performed, the pre-decoder unit 5 decodes the address counting signal ca [0: k] and outputs a pre_decoding signal ay [0: 7]. When a block write command is input, the data signal cam [0: 7] is decoded to output a pre_decoding signal ay [0: 7].

The address comparison unit 6 is controlled by the normal_wire dress_generation signal YSEI output from the memory (not shown) to convert the redundancy_address signal cra [0: k] into the address_counting signal ca. ) [0: k] and the redundancy_wireless_enable signal YRE and the normal_wireless_enable are compared with the pre_decoding signal ay [0: 7] of the pre-decoder section 5. Output the signal (YSE).

At this time, the normal_wire dress_generation signal YSEI is delayed by the delay unit 7 for a predetermined time and then AND gate AD1 is logically multiplied with the redundancy_wire dress_enable signal YRE to provide a redundancy_selection signal. (RYSI), and the pre_decoding signal ay [0: 7] of the pre-decoder section 5 is logically multiplied by the normal_wire dress_enable signal YSE at the AND gate AD2. The normal selection signal YSEO is output.

Then, the driver 8 latches the outputs RYSI and YSEO of each of the AND gates AD1 and AD2 and outputs them as a delay redundancy select signal RYSID and a delay normal select signal YSEOD. These are decoded by the wi-decoder section 9 and output as redundancy_wiredress_selection signal RYS and normal_wiredress_selection signal NYS, respectively.

Here, referring to the operation of the address comparison unit 6, if a defect occurs in a selected cell when a block write command is executed in a graphic memory (not shown) and a redundancy address is used, the address is output from the memory (not shown). The normal_wire dress_generation signal YSEI is input to the signal input unit 6e and the normal_wire dress_generation signal YSEI is a noah gate NR1 together with the test signal TEST set to "low potential". When the normal_wire dress_generation signal YSEI is activated to "low potential", the NOR gate NR1 outputs a "high potential" and the NMOS transistor NM1 is turned on. When the normal_wire dress_generation signal YSEI is inactive to " high potential ", the MOS gate NR1 outputs " low potential " to conduct the PMOS transistor PM3.

That is, when the normal_wire dress_generation signal YSEI is activated, the output of the signal input unit 6e becomes a floating state so that the normal_wire dress_enable signal YSE and the redundancy_wire dress_ When the enable signal YRE is active according to the first and second redundancy_wire dress_enable signals YRE00 and YRE01, respectively, and the normal_wire dress_generation signal YSEI is inactivated. The normal_wireless_enable signal YSE is always in an inactive state and the redundancy_wireless_enable signal YRE is in accordance with the first and second redundancy_wireless_enable signals YRE00 and YRE01. Whether it is active or not is determined.

On the other hand, when the normal_wiredress_generation signal YSEI is active, the comparator 6b decodes the pre_decode signal ay [0: 7] and the redundancy_address signal decoded into 8 bits by the 8-bit decoder 6a. (cra) [0: 2] is compared and the first redundancy_wire dress_enable signal YRE00 of "low potential" is output, and the comparator 6c outputs the address_counting signal ca [ 3: k] and the redundancy_address signal cra [3: k] are compared with each other, and if the same is the same, the second redundancy_wiredress_enable signal YRE01 of "low potential" is output.

Then, the PMOS transistors PM1 and PM2 are electrically connected to each other by the first and second redundancy_wire dress_enable signals YRE00 and YRE01, which are "low potential," so that the power supply voltage VDD is applied to the inverter INV. As a result, the low-potential normal_wire dress_enable signal YSE is output and the normal operation is inactive.

When any one of the first and second redundancy_wire dress_enable signals YRE00 and YRE01 becomes “high potential,” the PMOS transistors PM1 and PM2 are turned off and the NMOS transistors NM2, Since one side of the NM3 is turned on, the normal_wire dress_enable signal YSE becomes a value obtained by inverting the ground voltage VSS, which is the output of the signal input unit 6e.

Similarly, in the case of the redundancy selector 6f, when the first and second redundancy_wireless_enable signals YRE00 and YRE01 are determined according to the comparison result of each of the comparators 6b and 6c, Accordingly, whether or not the NMOS transistors NM2 and NM3 are conducted is determined, and the corresponding redundancy_wire dress_enable signal YRE is output.

That is, when the first and second redundancy_wire dress_enable signals YRE00 and YRE01 are both "low potential", the redundancy_wire dress_enable signal YRE of "high potential" is output and a redundancy operation is performed. When either one of the first and second redundancy_wiredress_enable signals YRE00 and YRE01 becomes "high potential," the redundancy_wiredress_enable signal YRE becomes "low potential". The redundancy operation is terminated.

However, as described above, when a redundancy address needs to be used because a defect occurs among selected cells when performing a block write command in the graphic memory as described above, the redundancy_wiredress is compared by comparing the redundancy address with the output of the pre-decoder section. Since the enable signal is generated, a series of paths for generating the redundancy wire dress enable signal are lengthened, thereby reducing the operation speed of the entire system.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems. The address_counting signal (ca) [divided into upper and lower parts by counting external addresses according to whether a block write command is input in the graphic memory. 0: 2] and (ca) [3: k] are inputted and compared with the redundancy_address signals cra and [0: 2] and (cra) [3: k], respectively. By generating the normal_wireless_enable signal (YSE) and the redundancy_wireless_enable signal (YRE) through the path selected by the result and the block write_control signal (BLWT), and controlling the driver, It is an object of the present invention to provide an apparatus for generating a wire dress in a graphic memory to remove a delay element occurring in the memory device.

1 is a block diagram showing the configuration of a wire dress generation apparatus in a conventional graphic memory;

FIG. 2 is a block diagram showing the configuration of the address comparison section in FIG.

Fig. 3 is a block diagram showing the configuration of the wire dress generating apparatus in the graphic memory of the present invention.

4 is a block diagram showing the configuration of an address comparison section in FIG.

*** Description of the symbols for the main parts of the drawings ***

10a: first input buffer portion 10b: second input buffer portion

20a: first latch portion 20b: second latch portion

30: counter 40: data signal generator

50: pre-decoder section 60: address comparison section

61, 62, 67: comparison unit 63: normal selection unit

64: signal input unit 65: redundancy selector

66: 8-bit decoder 70: Delay

80: driver 90: Y-decoder

AD1, AD2: AND gate INV1 to INV5: Inverter

NM1-NM4: MOS transistor PM1-PM4: PMOS transistor

NR1, NR2: Noah Gate

In order to achieve the above object, the present invention compares the input redundancy address and the output of the pre-decoder unit in the address comparison unit when the block write command is executed, and drives the driver and the Y-decoder unit according to the comparison result. In the wire dress generating device for outputting the wire dress selection signal (RYS) and the normal wire wiring selection signal (NYS), an address counting signal (ca) [counting an external address according to whether a block write command is input or not] 0: k] and the input redundancy_address signal cra [0: k] are separated into the upper address and the lower address, respectively, and compared through the path selected by the comparison result and the block write_control signal BLWT. A data signal cam [0:] which generates a normal_wire dress_enable signal YSE and a redundancy_wiredress_enable signal YRE and converts the input data DI [0: j]. 7] and an address comparator for outputting the redundancy_wiredress_drive signal YREN generated by comparing the redundancy_address signal cra [0: 2] decoded to 8 bits; And a driver which is controlled by the redundancy_wire dress_drive signal YREN of the address comparison unit and outputs a delay redundancy select signal RYSID and a delay normal_select signal YSEOD to the wi-decoder unit. do.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

Fig. 3 is a block diagram showing the configuration of the wire dress generation apparatus in the present invention graphic memory, and as shown therein, the external address signal Ext_ADDR [0: i] and the input data DI [0: j] are respectively shown. First and second input buffer units 10a and 10b for buffering; First and second latch units 20a and 20b for latching the outputs of the respective input buffer units 10a and 10b according to a clock signal CLK; A counter 30 counting the output of the first latch unit 20a and outputting the address_counting signal ca [0: k]; A data signal generator 40 controlled by a block write control signal BWLT and outputting the output of the second latch unit 20b as a data signal cam [0: 7]; The pre_decoding signal is decoded by decoding the address_counting signal ca [0: k] of the counter 30 or the data signal cam [0: 7] of the data signal generator 40 according to whether a block write command is received. a pre-decoder section 50 outputting to (ay) [0: 7]; The redundancy_wireless_enable signal is controlled by the normal_wireless_generation signal YSEI by comparing the redundancy_address signal cra [0: k] with the address_counting signal ca [0: k]. (YRE) and the normal_wire dress_enable signal YSE, and output the data signal cam [0: 7] and the redundancy_address signal cra [0:] of the data signal generator 40. 2] an address comparison unit 60 for comparing the redundancy wire dress driving signal YREN with each other; A delay unit 70 for delaying the normal_wire dress_generation signal YSEI for a predetermined time; The redundancy select signal RYSI is output by performing an AND operation on the redundancy_wire dress_enable signal YRE of the address comparison unit 60 and the normal_wire dress_generate signal YSEI delayed by the delay unit 70. And AND gate AD1; The normal_wire signal_enable signal YSE of the address comparison unit 60 and the pre_decode signal ay [0: 7] of the pre-decoder unit 50 are ANDed to perform a normal_selection signal YSEO. And an AND gate AD2 for outputting; After latching the outputs RYSI and YSEO of each of the AND gates AD1 and AD2, they are controlled by the redundancy_wireless_drive signal YREN to delay delay_selection signal RYSID and delay normal_selection signal YSEOD. A driver (80) for outputting; And a Y-decoder unit 90 which decodes the outputs RYSID and YSEOD of the driver 80 and outputs them as a redundancy_wire dress_selection signal RYS and a normal_wiredress_selection signal NYS.

Here, the address comparison unit 60 compares the address counting signal ca [0: 2] with the redundancy address signal cra [0: 2] to compare the first redundancy_wire dress_enable signal YRE00. A first comparator 61 for outputting; A second comparison unit 62 for comparing the address counting signal ca [3: k] with the redundancy_address signal cra [3: k] and outputting a second redundancy_wireless_enable signal YRE01. )Wow; A signal input unit 64 that receives the normal_wire dress_generation signal YSEI and maintains and outputs a predetermined level; The first and second redundancy_wire dress_enable signals YRE00 and YRE01, the block write control signal BLWT, and the output of the signal input unit 64 are controlled so that the normal_wire dress_enable signal ( A normal selector 63 for outputting YSE); Redundancy selector for controlling the first and second redundancy_wire dress_enable signals YRE00 and YRE01 and the block write_control signal BLWT to output the redundancy_wiredress_enable signal YRE. 65); The 8-bit decoder 66 outputs the redundancy_wiredress_drive signal YREN by comparing the redundancy_address signal cra [0: 2] and the data signal cam [0: 7] decoded to 8 bits. It consists of a third comparison unit 67, and the operation and operation of the embodiment according to the present invention configured in this way will be described in detail.

The external address signal Ext_ADDR [0: i] and the input data DI [0: j] are received and buffered in the first and second input buffer units 10a and 10b, and then the first and second input buffers 10a and 10b are processed according to the clock signal CLK. Latched by the first and second latch portions 20a and 20b, and the output of the first latch portion 20a is counted by the counter 30 so as to address_counting signal ca [0: k]. The output of the latch unit 20b is controlled by the block write control signal BLWT in the data signal generation unit 40 and output as the data signal cam [0: 7], and in the pre-decoder unit 50. Pre_decoding by decoding the address_counting signal ca [0: k] of the counter 30 or the data signal cam [0: 7] of the data signal generator 40 according to whether or not a block write command is issued. The process of outputting the signal ay [0: 7] is the same as in the prior art.

However, when performing a block write command in the graphic memory (not shown), when a defect occurs among selected cells and a redundancy address is to be used, the address comparison unit 60 counts an external address according to whether the block write command is input. Redundancy and address signals (ca) [0: 2], (ca) [3: k] divided into lower and upper levels are input, and redundancy_address signals (cra) [0: 2], ( cra) [3: k], respectively, and compares the result of the comparison and the block write control signal BWLT with the normal_wireless_enable signal YSE and the redundancy_wireless_enable signal. (YRE) and the redundancy_wiredress_ generated by comparing the data signal cam [0: 7] output from the data signal generator 40 with the redundancy_address signal cra [0: 2]. The driver 80 is controlled by the driving signal YREN to provide a redundancy wire dress selection signal RYS. ) Is different.

That is, when the normal_wire dress_generation signal YSEI output from the graphic memory (not shown) is input to the signal input unit 64, the address comparison unit 60 outputs the normal_wire dress_generation signal YSEI. The NOA operation is performed at the NOR gate NR1 together with the test signal TEST set to the “low potential”. When the NO_wire dress_generation signal YSEI is active at the "low potential", the NOA gate NR1 is activated. ) Outputs "high potential" so that the NMOS transistor NM1 conducts, and when the normal_wire dress_generation signal YSEI is inactive to "high potential", the noah gate NR1 becomes "inactive". PMOS transistor PM4 conducts by outputting low potential ".

Here, when the block write control signal BWLT becomes " low potential, " the PMOS transistor PM3 of the normal selector 63 is turned on so that the first and second redundancy_wireless_enable signals YRE00 and YRE01. Is determined by the normal_wire dress_enable signal YSE, and the NMOS transistor NM2 of the redundancy selector 65 is turned off by the block write control signal BLWT having the low potential. The first and second redundancy_wireless_enable signals YRE00 and YRE01 are redundancy_wireless_enable signals along the path of the inverter INV3 turned on by the block write_control signal BLWT. YRE).

When the block write command is input and the block write control signal BWLT becomes “high potential,” the PMOS transistor PM3 of the normal selector 63 is turned off and the yen of the redundancy selector 65 is turned off. The MOS transistor NM2 is turned on. At this time, the normal_wire dress_generation signal YSEI input to the signal input unit 64 is inverted through the inverter INV1 and directly connected to the normal_wire dress_enable signal YSE. Is output.

In addition, the redundancy selector 65 opens the path of the inverter INV4 side by the block write_control signal BWLT having the "high potential", and the second redundancy_wireless_in determined by the second comparator 62. The enable signal YRE01 is inverted through each of the inverters INV2, INV4, and INV5 and output as a redundancy_wireless_enable signal YRE.

On the other hand, the data signal cam [0: 7] output from the data signal generator 40 and the redundancy_address signal cra [0: 2] decoded into 8 bits by the 8-bit decoder 63 are third. The redundancy_wiredress_drive signal YREN is output as the "high potential" to the driver 80 only when both of them are compared by the comparator 64 to become "high potential".

In this case, when the block write command is performed, the redundancy_wire dress_enable signal YRE having the "high potential" is first outputted as the redundancy_selection signal RYSI through the AND gate AD1 and then the "high potential". Redundancy_wiredress_drive signal YREN is generated, wherein the driver 80 passes only the redundancy_selection signal RYSI latched by the redundancy_wiredress_drive signal YREN and delay redundancy_ The redundancy_wire dress_selection signal RYS is generated by outputting to the wi-decoder 90 as the selection signal RYSID.

When both of the data signal cam [0: 7] and the redundancy_address signal cra [0: 2] decoded by 8 bits in the 8-bit decoder 63 are not "high potential", Since the third comparator 67 outputs the "low potential" redundancy_wire dress_drive signal YREN, the third comparison unit 67 sets the redundancy_wire dress_selection signal RYS to "low potential". To keep.

As described above, the present invention provides an address_counting signal ca [0: k] counting an external address and an input redundancy_address signal cra [0:] according to whether a block write command is input in the graphic memory. k] is compared with the upper address and the lower address, and the normal_wire dress_enable signal YSE and the redundancy_wire dress_in are determined through the comparison result and the path selected by the block write control signal BLWT. By generating the enable signal YRE and controlling the driver, there is an effect that high-speed operation is possible by improving the processing speed of the entire system by eliminating the delay factor generated during signal transmission.

Claims (2)

When executing the block write command, the input redundancy address and the output of the pre-decoder section are compared by the address comparison section, and the driver and the Wi-decoder section are driven according to the result of the comparison, so that the redundancy_wiredress_selection signal RYS and the normal are performed. In the wire dress generator for outputting the wire dress selection signal (NYS), an address counting signal (ca) divided into lower and upper parts by counting an external address according to whether a block write command is input or not [0: 2] Inputs (ca) [3: k] and compares them with the redundancy_address signals (cra) [0: 2] and (cra) [3: k] respectively, and compares them and writes the blocks. The normal_wireless_enable signal YSE and the redundancy-wireless_enable signal YRE are generated through the path selected by the control signal BWLT, and the input data DI [0: j] is generated. Decoding into 8 bits with the converted data signal (cam) [0: 7] _ Redundancy address signal (cra) [0: 2] The redundancy created by comparing the wire dress _ _ address and outputting a drive signal (YREN) comparing unit; Drive control is performed by the redundancy_wire dress_drive signal YREN of the address comparison unit, and the redundancy_selection according to the redundancy_wire dress_enable signal YRE and the normal_wire dress_enable signal YSE is selected. And a driver for outputting the delay redundancy selection signal (RYSID) and the delay normal selection signal (YSEOD) to the Y-decoder according to the signal (RYSI) and the normal_selection signal (YSEO). Wire dressing device. 2. The address redundancy_wireless_enable signal of claim 1, wherein the address comparison unit compares the address counting signal ca [0: 2] with the redundancy address signal cra [0: 2]. A first comparing unit for outputting; A second comparison unit for comparing the address counting signal ca [3: k] with the redundancy_address signal cra [3: k] and outputting a second redundancy_wireless_enable signal YRE01; A signal input unit which receives the normal_wire dress_generation signal YSEI and maintains and outputs a predetermined level; It is controlled by the block write control signal BLWT and outputs the normal_wire dress_enable signal YSE according to the first and second redundancy_wire dress_enable signals YRE00 and YRE01. A normal selection unit to receive output control by the output of the signal input unit; Redundancy under control by the block write control signal BWLT and output redundancy_wireless_enable signal YRE according to the first and second redundancy_wiredress_enable signals YRE00 and YRE01. A selection unit; A third outputting the redundancy_wireless_drive signal YREN by comparing the redundancy_address signal cra [0: 2] and the data signal cam [0: 7] decoded to 8 bits by the 8-bit decoder. A wire dress generating device in a graphics memory, characterized by comprising a comparator.