KR100343443B1 - Stacked micro ball grid array package and manufacturing method thereof - Google Patents
Stacked micro ball grid array package and manufacturing method thereof Download PDFInfo
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- KR100343443B1 KR100343443B1 KR1019990042373A KR19990042373A KR100343443B1 KR 100343443 B1 KR100343443 B1 KR 100343443B1 KR 1019990042373 A KR1019990042373 A KR 1019990042373A KR 19990042373 A KR19990042373 A KR 19990042373A KR 100343443 B1 KR100343443 B1 KR 100343443B1
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- insulating layer
- chip
- solder ball
- molding part
- plate
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000011806 microball Substances 0.000 title 1
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 238000000465 moulding Methods 0.000 claims abstract description 42
- 238000005452 bending Methods 0.000 claims abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 56
- 229910052759 nickel Inorganic materials 0.000 claims description 28
- 239000004020 conductor Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000004304 visual acuity Effects 0.000 claims 2
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000011805 ball Substances 0.000 description 27
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
본 발명은 적층형 마이크로 비지에이 패키지 및 제조방법에 관한 것으로서, 종래의 플립 칩 패키지는 두개 이상의 패키지를 적층시키는 패키지의 적층기술에는 부적합한 문제점이 있었으나, 본 발명은 종래의 플립 칩 패키지를 감싸도록 몰딩부를 형성하고, 상기 몰딩부의 상하단에 리드판을 절곡시켜 솔더볼을 접촉하여 적층시킴으로써, 그리드 어레이 형태로서 적층 가능한 플립 칩 패키지를 제조할 수 있다.The present invention relates to a stacked micro-visual package and a manufacturing method, the conventional flip chip package has an unsuitable problem in the stacking technology of a package for stacking two or more packages, the present invention is a molding unit to surround the conventional flip chip package Forming, by bending the lead plate in the upper and lower ends of the molding portion to contact the solder balls to be laminated, it is possible to manufacture a flip chip package that can be stacked in the form of a grid array.
Description
본 발명은 적층형 마이크로 비지에이 패키지 및 제조방법에 관한 것으로서, 보다 상세하게는 그리드 어레이 형태로서 적층 가능한 플립 칩 패키지를 제조할 수 있는 적층형 마이크로 비지에이 패키지 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked microvisual package and a manufacturing method, and more particularly, to a stacked microvisual package and a manufacturing method capable of manufacturing a stackable flip chip package in the form of a grid array.
일반적으로 칩의 크기와 유사한 크기의 패키지를 제조하는 기술의 일환으로 개발된 패키지가 CSP(CHIP SIZE PACKAGE)이며, 이와 같은 CSP의 일종으로 마이크로 비지에이 패키지가 적용되고, 최근 상기 패키지를 적층하는 기술이 크게 부각되고 있다. 따라서, 많은 투자 없이도 시스템이 요구하는 고집적 메모리 및 다기능 디바이스 등을 출현시키고 있는 바, 이를 설명하면 다음과 같다.In general, a package developed as a part of a technology for manufacturing a package having a size similar to that of a chip is a CSP (CHIP SIZE PACKAGE), and a microvisi package is applied as a kind of such a CSP, and a technique of recently stacking the package. This is greatly highlighted. Therefore, the high-integrated memory and the multifunction device required by the system are emerging without much investment.
도 1은 종래의 플립 칩 패키지(FLIP CHIP PACKAGE)의 구조를 나타내 보인 단면도로서, 도시된 바와 같이, 상면에 다수개의 칩패드(1a)가 형성되어 있는 반도체칩(1)과, 상기 각 칩패드(1a)의 상면에 형성된 니켈범프(2)와, 상기 칩(1)의 상면에서 상기 니켈범프(2)의 상면을 노출시키며 도포되는 제1절연층(5a)과, 상기 각 니켈범프(2)의 상면과 접촉하며, 상기 제1절연층(5a)의 상측에 설치되는 다수개의 컨덕터(6)와, 상기 제1절연층(5a)의 상측에서 상기 컨덕터(6)와 동일한 높이로 도포되는 제2절연층(5b)과, 상기 각 컨덕터(6)의 상면에 부착되는 다수개의 솔더볼랜드(7)와, 상기 솔더볼랜드(7)와 동일한 높이로 상면에 도포되는 제3절연층(5c)과, 상기 솔더볼랜드(7)의 상면에 부착되는 솔더볼(8)로 구성된다.FIG. 1 is a cross-sectional view illustrating a structure of a conventional flip chip package. As illustrated, a semiconductor chip 1 having a plurality of chip pads 1a formed on an upper surface thereof, and the respective chip pads. Nickel bumps (2) formed on the upper surface of (1a), the first insulating layer (5a) is applied while exposing the upper surface of the nickel bumps 2 from the upper surface of the chip (1), and each of the nickel bumps (2) A plurality of conductors 6 disposed on the first insulating layer 5a and in contact with the upper surface of the first insulating layer 5a, and applied to the same height as the conductors 6 above the first insulating layer 5a. A second insulating layer 5b, a plurality of solder bores 7 attached to the upper surfaces of the conductors 6, and a third insulating layer 5c applied to the upper surfaces at the same height as the solder bores 7; And a solder ball 8 attached to an upper surface of the solder ball land 7.
상기 종래의 적층형 마이크로 비지에이 패키지의 제조공정을 순차적으로 설명하면 다음과 같다.Referring to the manufacturing process of the conventional laminated micro-visgi package sequentially as follows.
먼저, 도 2a에 도시된 바와 같이, 반도체칩(1)의 상면에 다수개의 칩패드(1a)를 설치하고, 상기 각 칩패드(1a)의 상면에 니켈범프(2)를 형성한다.First, as illustrated in FIG. 2A, a plurality of chip pads 1a are installed on the upper surface of the semiconductor chip 1, and nickel bumps 2 are formed on the upper surface of each chip pad 1a.
다음, 도 2b와 같이, 상기 칩(1)의 상면을 제1절연층(5a)으로 도포한 후, 식각공정으로 상기 니켈범프(2)의 상면을 노출시킨다.Next, as shown in FIG. 2B, the top surface of the chip 1 is coated with the first insulating layer 5a, and then the top surface of the nickel bumps 2 is exposed by an etching process.
그런 다음, 도 2c와 같이, 상기 제1절연층(5a)의 상부에 소정의 두께로 제2절연층(5b)을 도포한 후, 상기 니켈범프(2)의 상면을 식각하고, 상기 식각된 부분에 제2절연층(5b)과 동일한 높이로 컨덕터(6)를 증착시킨다.Then, as shown in FIG. 2C, after applying the second insulating layer 5b to a predetermined thickness on the first insulating layer 5a, the upper surface of the nickel bumps 2 is etched, and the etched The conductor 6 is deposited at the same height as the second insulating layer 5b.
그런 다음, 도 2d와 같이, 상기 제2절연층(5b)과 컨덕터(6)의 상면에 소정의 두께로 제3절연층(5c)을 도포하고, 상기 컨덕터(6)의 상면을 식각시킨 후, 도 2e와 같이, 상기 컨덕터(6)의 상면에 솔더볼랜드(7)를 형성한다.Then, as shown in FIG. 2D, the third insulating layer 5c is coated on the upper surfaces of the second insulating layer 5b and the conductor 6 to a predetermined thickness, and the upper surface of the conductor 6 is etched. 2E, solder ball lands 7 are formed on the upper surface of the conductor 6.
그런 다음, 도 1과 같이, 상기 솔더볼랜드(7)의 상면에 솔더볼(8)을 고정부착하여 마이크로 비지에이 패키지를 완성한다.Then, as shown in FIG. 1, the solder ball 8 is fixedly attached to the upper surface of the solder ball land 7 to complete the micro-visual package.
그러나, 상기와 같은 구성을 갖는 종래의 플립 칩 패키지는 두개 이상의 패키지를 적층시키는 패키지의 적층기술에는 부적합한 문제점이 있었다.However, the conventional flip chip package having the above configuration has an unsuitable problem in the stacking technology of a package in which two or more packages are stacked.
본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 그리드 어레이 형태로서 적층 가능한 플립 칩 패키지를 제조할 수 있는 적층형 마이크로 비지에이 패키지 및 제조방법을 제공하는 데 있다.The present invention has been made to solve the problems of the prior art as described above, an object of the present invention to provide a stacked micro-visgi package and a manufacturing method capable of manufacturing a stackable flip chip package in the form of a grid array. .
도 1은 종래의 적층형 마이크로 비지에이 패키지의 구조를 나타내 보인 단면도.1 is a cross-sectional view showing the structure of a conventional stacked micro-visual package.
도 2a 내지 도 2e는 종래의 적층형 마이크로 비지에이 패키지의 제조공정을 순차적으로 나타내 보인 단면도.2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of a conventional stacked micro-VISI package.
도 3은 본 발명에 따른 적층형 마이크로 비지에이 패키지의 구조를 나타내 보인 단면도.Figure 3 is a cross-sectional view showing the structure of a stacked micro busy package according to the present invention.
도 4a 내지 도 4j는 본 발명에 따른 적층형 마이크로 비지에이 패키지의 제조공정을 순차적으로 나타내 보인 단면도.4A to 4J are cross-sectional views sequentially illustrating a manufacturing process of the stacked micro-VISI package according to the present invention.
도 5는 본 발명에 따른 적층형 마이크로 비지에이 패키지가 적층된 상태를 나타내 보인 단면도.Figure 5 is a cross-sectional view showing a state in which the stacked micro-vision package according to the present invention stacked.
〈 도면의 주요부분에 대한 부호설명〉<Code Description of Major Parts of Drawings>
11 : 칩 11a : 칩패드11: chip 11a: chip pad
12 : 니켈범프 13 : 리드판12 nickel bump 13 lead plate
13a : 상판 13b : 하판13a: top plate 13b: bottom plate
14 : 몰딩부 14a : 리드공14: molding 14a: lead ball
15a : 제1절연층 15b : 제2절연층15a: first insulating layer 15b: second insulating layer
15c : 제3절연층 15d : 제4절연층15c: third insulating layer 15d: fourth insulating layer
16 : 컨덕터 17a : 제1솔더볼랜드16: conductor 17a: first solder borland
17b : 제2솔더볼랜드 18 : 솔더볼17b: second solder ball land 18: solder ball
상기 목적을 달성하기 위하여, 본 발명인 적층형 마이크로 비지에이 패키지는 내측에 공간부가 형성되며 양측에는 리드판을 수용할 수 있는 다수개의 리드공이 형성된 몰딩부와; 상기 각 리드공을 관통하며 상기 몰딩부의 상단 및 하단에서 내측으로 절곡되어 각각 상면과 하면에서 노출되는 상판과 하판이 형성되는 다수개의 리드판과; 상기 몰딩부 내측의 저면부에 설치되는 칩패들과; 상기 칩패들의 상측에 위치되어 그 상면에 다수개의 칩패드가 형성되어 있는 반도체칩과; 상기 각 칩패드의 상면에 형성된 니켈범프와; 상기 칩의 상면에서 상기 니켈범프의 상면을 노출시키며 도포되는 제1절연층과; 상기 각 니켈범프의 상면과 접촉되며 상기 상판의 하면과 접촉되며, 상기 제1절연층의 상측에 설치되는 다수개의 컨덕터와; 상기 제1절연층의 상측에서 상기 컨덕터와 동일한 높이로 도포되는 제2절연층과; 상기 각 상판의 상면에 부착되는 다수개의 제1솔더볼랜드와; 상기 각 하판의 하면에 부착되는 다수개의 제2솔더볼랜드와; 상기 제1솔더볼랜드의 상면과 동일한 높이로 상면에 도포되는 제3절연층과; 상기 제2솔더볼랜드의 하면과 동일한 높이로 하면에 도포되는 제4절연층과; 상기 제2솔더볼랜드의 하면에 부착되는 솔더볼;로 구성된다In order to achieve the above object, the present invention is a laminated micro busy package is formed with a space portion on the inside and a molding portion formed with a plurality of lead holes that can accommodate the lead plate on both sides; A plurality of lead plates penetrating through each of the lead holes and bent inward from upper and lower ends of the molding part to expose upper and lower plates, respectively; A chip paddle installed at a bottom surface of the molding unit; A semiconductor chip positioned above the chip pads and having a plurality of chip pads formed thereon; Nickel bumps formed on upper surfaces of the chip pads; A first insulating layer applied while exposing the top surface of the nickel bumps on the top surface of the chip; A plurality of conductors in contact with an upper surface of each of the nickel bumps and in contact with a lower surface of the upper plate and disposed on an upper side of the first insulating layer; A second insulating layer applied to the same height as the conductor above the first insulating layer; A plurality of first solder ball lands attached to an upper surface of each top plate; A plurality of second solder ball lands attached to a lower surface of each lower plate; A third insulating layer applied to the upper surface at the same height as the upper surface of the first solder ball land; A fourth insulating layer applied to the bottom surface at the same height as the bottom surface of the second solder ball land; Consists of a solder ball attached to the lower surface of the second solder ball land
그리고, 상기 적층형 마이크로 비지에이 패키지의 제조방법은 반도체칩의 상면에 다수개의 칩패드를 설치하고, 상기 각 칩패드의 상면에 니켈범프를 형성하는 단계와; 내측에 공간부가 형성되며 양측에는 리드판을 수용할 수 있는 다수개의 리드공이 형성된 몰딩부를 에폭시로 몰딩하고, 상기 몰딩부 내측의 저면부에 칩패들을 설치하는 단계와; 상기 리드판을 L자 형상으로 절곡하여 하판이 상기 몰딩부의 하단에 밀착된 상태로 노출되도록 상기 각 리드공을 관통시키는 단계와; 니켈범프가 형성된 패키지를 상기 몰딩부의 내측에 형성된 공간부에 실장시키는 단계와; 상기 칩의 상면을 제1절연층으로 도포한 후, 식각공정으로 상기 니켈범프의 상면을 노출시키는 단계와; 상기 제1절연층의 상부에 소정의 두께로 제2절연층을 도포한 후, 상기 니켈범프의 상면을 식각하고, 상기 식각된 부분에 제2절연층과 동일한 높이로 컨덕터를 증착시키는 단계와; 상기 리드판을 상기 몰딩부의 내측으로 절곡하여 상판이 상기 몰딩부의 상단에 밀착된 상태로 노출되도록 하는 단계와; 상기 제2절연층과 컨덕터 및 몰딩부의 상면에 소정의 두께로 제3절연층을 도포하고, 상기 상판의 상면을 식각시키는 단계와; 상기 상판의 상면에 제1솔더볼랜드를 형성하는 단계와; 상기 칩패들과 몰딩부의 하면에 소정의 두께로 제4절연층을 도포하고, 상기 하판의 하면을 식각시키는 단계와; 상기 하판의 하면에 제2솔더볼랜드를 형성하는 단계와; 상기 제2솔더볼랜드의 하면에 솔더볼을 고정 부착하는 단계의 순서로 제조되는 것을 특징으로 한다.In addition, the manufacturing method of the stacked micro-VISI package may include installing a plurality of chip pads on an upper surface of a semiconductor chip, and forming nickel bumps on an upper surface of each chip pad; Molding a molding part in which a space part is formed in the inside and a molding part in which a plurality of lead holes capable of accommodating the lead plate is formed with epoxy, and installing chip paddles in the bottom surface of the molding part; Bending the lead plates into an L shape to penetrate the lead holes so that the lower plate is exposed in close contact with the lower end of the molding part; Mounting a package on which nickel bumps are formed in a space portion formed inside the molding portion; Coating the upper surface of the chip with a first insulating layer, and then exposing the upper surface of the nickel bumps by an etching process; Applying a second insulating layer to a predetermined thickness on the first insulating layer, etching the upper surface of the nickel bumps, and depositing a conductor at the same height as the second insulating layer on the etched portion; Bending the lead plate to the inside of the molding part to expose the top plate to be in close contact with the upper end of the molding part; Applying a third insulating layer to the upper surface of the second insulating layer, the conductor and the molding part to a predetermined thickness, and etching the upper surface of the upper plate; Forming a first solder ball land on an upper surface of the upper plate; Applying a fourth insulating layer to a lower surface of the chip paddle and the molding part to a predetermined thickness and etching the lower surface of the lower plate; Forming a second solder ball land on a lower surface of the lower plate; Characterized in that the manufacturing order of the step of fixing the solder ball on the lower surface of the second solder ball land.
이하 본 발명의 바람직한 일실시례를 첨부 도면에 의거하여 상세히 설명하면 다음과 같다.BEST MODE Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 상기 적층형 마이크로 비지에이 패키지의 단면도로서, 도시된 바와 같이, 내측에 공간부가 형성되며 양측에는 리드판(13)을 수용할 수 있는 다수개의 리드공(14a)이 형성된 몰딩부(14)와, 상기 각 리드공(14a)을 관통하며 상기 몰딩부(14)의 상단 및 하단에서 내측으로 절곡되어 각각 상면과 하면에서 노출되는 상판(13a)과 하판(13b)이 형성되는 다수개의 리드판(13)과, 상기 몰딩부(14) 내측의 저면부에 설치되는 칩패들(19)과, 상기 칩패들(19)의 상측에 위치되어 그 상면에 다수개의 칩패드(11a)가 형성되어 있는 반도체칩(11)과, 상기 각 칩패드(11a)의 상면에 형성된 니켈범프(12)와, 상기 칩(11)의 상면에서 상기 니켈범프(12)의 상면을 노출시키며 도포되는 제1절연층(15a)과, 상기 각 니켈범프(12)의 상면과 접촉되며 상기 상판의 하면과 접촉되며, 상기 제1절연층(15a)의 상측에 설치되는 다수개의 컨덕터(16)와, 상기 제1절연층(15a)의 상측에서 상기 컨덕터(16)와 동일한 높이로 도포되는 제2절연층(15b)과, 상기 각 상판(13a)의 상면에 부착되는 다수개의 제1솔더볼랜드(17a)와, 상기 각 하판(13b)의 하면에 부착되는 다수개의 제2솔더볼랜드(17b)와, 상기 제1솔더볼랜드(17a)의 상면과 동일한 높이로 상면에 도포되는 제3절연층(15c)과, 상기 제2솔더볼랜드(17b)의 하면과 동일한 높이로 하면에 도포되는 제4절연층(15d)과, 상기 제2솔더볼랜드(17b)의 하면에 부착되는 솔더볼(18)로 구성된다3 is a cross-sectional view of the stacked micro-visual package, and as shown, a molding part 14 having a plurality of lead holes 14a formed therein and having a plurality of lead holes 14a capable of accommodating the lead plate 13 on both sides. And a plurality of lead plates penetrating through the lead holes 14a and bent inward from the upper and lower ends of the molding part 14 to expose the upper and lower surfaces 13a and 13b, respectively. 13, chip paddles 19 installed on the bottom surface of the molding part 14, and a plurality of chip pads 11a formed on the upper side of the chip paddles 19. The first insulating layer is applied to expose the semiconductor chip 11, the nickel bump 12 formed on the upper surface of each chip pad 11a, and the upper surface of the nickel bump 12 from the upper surface of the chip 11 15a and the upper surface of each of the nickel bumps 12 and the lower surface of the upper plate, the first insulating layer ( A plurality of conductors 16 provided on the upper side of 15a, a second insulating layer 15b applied to the same height as the conductor 16 above the first insulating layer 15a, and each of the upper plates ( A plurality of first solder bores 17a attached to an upper surface of 13a), a plurality of second solder bores 17b attached to a lower surface of each lower plate 13b, and an upper surface of the first solder bores 17a. The third insulating layer 15c applied to the upper surface at the same height as the upper surface, the fourth insulating layer 15d applied to the lower surface at the same height as the lower surface of the second solder ball land 17b, and the second solder borland ( It consists of a solder ball 18 attached to the lower surface of 17b)
이하, 상기와 같이 구성된 본 발명에 따른 적층형 마이크로 비지에이 패키지의 제조방법을 순차적으로 설명하면 다음과 같다.Hereinafter, the manufacturing method of the stacked micro-visgi package according to the present invention configured as described above are described in sequence.
먼저, 도 4a에 도시된 바와 같이, 반도체칩(11)의 상면에 다수개의 칩패드(11a)를 설치하고, 상기 각 칩패드(11a)의 상면에 니켈범프(12)를 형성한다.First, as illustrated in FIG. 4A, a plurality of chip pads 11a are disposed on the upper surface of the semiconductor chip 11, and nickel bumps 12 are formed on the upper surface of each chip pad 11a.
다음, 도 4b와 같이, 내측에 공간부가 형성되며 양측에는 리드판(13)을 수용할 수 있는 다수개의 리드공(14a)이 형성된 몰딩부(14)를 에폭시로 몰딩하고, 상기 몰딩부(14) 내측의 저면부에 칩패들(19)을 설치한다.Next, as shown in FIG. 4B, a space part is formed on the inner side, and molding parts 14 formed with a plurality of lead holes 14a capable of accommodating the lead plate 13 are molded with epoxy, and the molding part 14 The chip paddle 19 is installed in the bottom surface inside.
그런 다음, 도 4c와 같이, 상기 리드판(13)을 L자 형상으로 절곡하여 하판(13b)은 상기 몰딩부(14)의 하단에 밀착하도록 상기 각 리드공(14a)을 관통시킨다.Then, as shown in FIG. 4C, the lead plate 13 is bent into an L shape so that the lower plate 13b penetrates the lead holes 14a to be in close contact with the lower end of the molding part 14.
그런 다음, 도 4d와 같이, 상기 니켈범프(12)가 형성되어 도 4a에 도시된 패키지를 상기 몰딩부(14)의 내측에 형성된 공간부에 실장시킨 후, 상기 칩(11)의 상면을 제1절연층(15a)으로 도포한 후, 식각공정으로 상기 니켈범프(12)의 상면을 노출시킨다.Then, as shown in FIG. 4D, the nickel bumps 12 are formed to mount the package shown in FIG. 4A in a space formed inside the molding part 14, and then the upper surface of the chip 11 is removed. After coating with one insulating layer 15a, the upper surface of the nickel bumps 12 is exposed by an etching process.
그런 다음, 도 4e와 같이, 상기 제1절연층(15a)의 상부에 소정의 두께로 제2절연층(15b)을 도포한 후, 상기 니켈범프(12)의 상면을 식각하고, 상기 식각된 부분에 제2절연층(15b)과 동일한 높이로 컨덕터(16)를 증착시킨다.Then, as shown in FIG. 4E, after applying the second insulating layer 15b to a predetermined thickness on the first insulating layer 15a, the upper surface of the nickel bump 12 is etched, and the etched The conductor 16 is deposited on the portion at the same height as the second insulating layer 15b.
그런 다음, 도 4f와 같이, 상기 리드판(13)을 상기 몰딩부(14)의 내측으로 절곡하여 상판(13a)을 상기 몰딩부(14)의 상단에 밀착시킨다.Then, as shown in FIG. 4F, the lead plate 13 is bent into the molding part 14 to bring the top plate 13a into close contact with the upper end of the molding part 14.
그런 다음, 도 4g와 같이, 상기 제2절연층(15b)과 컨덕터(16) 및 몰딩부(14)의 상면에 소정의 두께로 제3절연층(15c)을 도포하고, 상기 상판(13a)의 상면을 식각시킨 후, 도 4h와 같이, 상기 상판(13a)의 상면에 제1솔더볼랜드(17a)를 형성한다.Then, as shown in FIG. 4G, the third insulating layer 15c is coated on the upper surface of the second insulating layer 15b, the conductor 16, and the molding part 14 to a predetermined thickness, and the upper plate 13a is disposed. After etching the upper surface of the, as shown in Figure 4h, the first solder ball land (17a) is formed on the upper surface of the upper plate (13a).
그런 다음, 도 4i와 같이, 상기 칩패들(19)과 몰딩부(14)의 하면에 소정의 두께로 제4절연층(15d)을 도포하고, 상기 하판(13b)의 하면을 식각시킨 후, 도 4j와 같이, 상기 하판(13a)의 하면에 제2솔더볼랜드(17b)를 형성한다.Then, as shown in FIG. 4I, the fourth insulating layer 15d is coated on the lower surface of the chip paddle 19 and the molding part 14 to a predetermined thickness, and the lower surface of the lower plate 13b is etched. As shown in FIG. 4J, a second solder ball land 17b is formed on the lower surface of the lower plate 13a.
그런 다음, 상기 제2솔더볼랜드(17b)의 하면에 솔더볼(18)을 고정 부착하여 도 3과 같이 적층형 마이크로 비지에이 패키지를 완성한다.Then, the solder ball 18 is fixedly attached to the lower surface of the second solder ball land 17b to complete the stacked micro-visual package as shown in FIG. 3.
도 5는 본 발명에 따른 적층형 마이크로 비지에이 패키지가 적층된 상태를 나타내 보인 단면도로서, 상부에 적층된 패키지의 솔더볼(18)이 하부에 적층된 제1솔더볼랜드(17a)의 상면에 접촉하게 된다.FIG. 5 is a cross-sectional view illustrating a stacked micro busy package according to the present invention in which the solder balls 18 of the package stacked on the upper surface contact the upper surface of the first solder ball land 17a stacked on the bottom. .
이상에서 설명한 바와 같이, 본 발명에 의한 적층형 마이크로 비지에이 패키지 및 제조방법은 종래의 플립 칩 패키지를 감싸도록 몰딩부를 형성하고, 상기 몰딩부의 상하단에 리드판을 절곡시켜 솔더볼을 접촉하여 적층시킴으로써, 그리드 어레이 형태로서 적층 가능한 플립 칩 패키지를 제조할 수 있는 효과가 있다.As described above, according to the present invention, the laminated micro-visual package and the manufacturing method of the present invention form a molding part to surround a conventional flip chip package, and bend the lead plate on the upper and lower ends of the molding part to contact and stack the solder balls to form a grid. There is an effect of manufacturing a stackable flip chip package in an array form.
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| KR20030029743A (en) * | 2001-10-10 | 2003-04-16 | 삼성전자주식회사 | Stack package using flexible double wiring substrate |
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| KR19980044211A (en) * | 1996-12-06 | 1998-09-05 | 문정환 | Semiconductor package and manufacturing method |
| KR19980043247A (en) * | 1996-12-02 | 1998-09-05 | 김광호 | Chip scale package assembly and multi chip module assembly having the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980043247A (en) * | 1996-12-02 | 1998-09-05 | 김광호 | Chip scale package assembly and multi chip module assembly having the same |
| KR19980044211A (en) * | 1996-12-06 | 1998-09-05 | 문정환 | Semiconductor package and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010035680A (en) | 2001-05-07 |
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