KR100341119B1 - LCD Display - Google Patents

Abstract

The present invention discloses a liquid crystal display device capable of improving switching capability of a thin film transistor while preventing pixel defects. The disclosed liquid crystal display device includes a substrate, a gate bus line disposed in one direction of the substrate, and the gate. A data bus line disposed perpendicularly to the bus line, a gate insulating layer interposed between the gate bus line and the data bus line to insulate them, and a channel layer disposed near an intersection of the gate bus line and the data bus line. And at least one pair of thin film transistors which commonly use the same, and a pixel electrode disposed in contact with the thin film transistor in a unit pixel space surrounded by the gate bus line and the data bus line. The thin film transistor may include a gate bus line, a gate insulating film covering the gate bus line, a channel layer on the gate insulating film, a source electrode extending from the data bus line on one side of the channel layer, and the channel. A drain electrode disposed on the other side of the layer and in contact with the pixel electrode, and a dummy gate electrode disposed on a portion of the channel layer between the source electrode and the drain electrode, wherein the dummy gate electrode includes the gate bus line; Contact is made.

Description

Liquid crystal display

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving on-current of a thin film transistor while preventing pixel defects.

1 is a plan view illustrating unit pixels of a general liquid crystal display. As shown, the gate bus line 1 extends in the first direction on the glass substrate 10, and the data bus line 3 extends in the second direction perpendicular to the gate bus line 1. The unit pixel P is defined. At this time, a gate insulating film (not shown) is interposed between the gate bus line 1 and the data bus line 3 to electrically insulate these two lines. The gate bus line 1 includes a protrusion 1a protruding into the corresponding unit pixel P by a predetermined length in parallel with the data bus line 3. A channel layer (not shown) and an etch stopper 5 are disposed on the protrusion 1a of the gate bus line 1. In addition, the data bus line 3 includes a protrusion 3a protruding to overlap one side of the etch stopper 5.

The protrusion 1a of the gate bus line 1 serves as a gate electrode of the thin film transistor, and the protrusion 3a of the data bus line 3 serves as a small electrode of the thin film transistor.

The pixel electrode 7 is disposed in each of the unit pixel P spaces surrounded by the gate bus line 1 and the data bus line 3. The pixel electrode 7 is contacted with an electrode pattern 3b spaced apart from the protrusion 3a of the data bus line 3 so as to overlap the other side of the etch stopper 5. The electrode pattern 3b is formed together with the data bus line 3 to become a drain electrode of the thin film transistor.

In the above, the thin film transistor TFT1 includes a gate electrode, a source electrode, a drain electrode, a channel layer, and an etch stopper 5.

In the liquid crystal display, when a select signal is applied to the gate bus line 1, a signal applied to the data bus line 3 is transferred to the pixel electrode 7 through the thin film transistor TFT1.

However, the above-described conventional liquid crystal display device has a high risk of generating a short circuit between the gate electrode and the source electrode, or the gate electrode and the drain electrode in the thin film transistor portion, whereby a defect occurs in the thin film transistor TFT1. As a result, there is a problem that pixel defects are caused.

In addition, as the number of unit pixels is increased to obtain a high resolution, the pixel size is reduced, which causes a decrease in the channel length of the thin film transistor, resulting in a decrease in the on-current during the on operation of the thin film transistor. As a result, there is a problem in that the switching capability of the thin film transistor is lowered.

Accordingly, it is an object of the present invention to provide a liquid crystal display device capable of preventing pixel defects caused by defects in thin film transistors.

In addition, another object of the present invention is to provide a liquid crystal display device capable of improving the switching capability of the thin film transistor by increasing the on-current of the thin film transistor.

1 is a plan view of a conventional liquid crystal display device.

2 is a plan view of a unit pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of the thin film transistor, taken along line III-III '.

4 is a plan view of a unit pixel of a liquid crystal display according to another exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

11, 21: gate lines 11a, 21a: protrusions of the gate bus lines

12 gate insulating film 13 channel layer

14: etch stopper 15: doped semiconductor layer

16, 26: data bus line 16a, 26a: protrusion of the data bus line

16a and 26b electrode patterns 17 and 27 pixel electrodes

18,28: dummy gate electrode 20,30: glass substrate

According to an aspect of the present invention, there is provided a liquid crystal display device including a substrate, a gate bus line disposed in one direction of the substrate, a data bus line disposed perpendicular to the gate bus line, and the gate bus line; A gate insulating film interposed between the data bus lines to insulate them, at least one pair of thin film transistors disposed in the vicinity of an intersection of the gate bus lines and the data bus lines and using a channel layer in common, and the gate bus lines And a pixel electrode disposed in contact with the thin film transistor in a unit pixel space surrounded by a data bus line.

The thin film transistor may include a gate bus line, a gate insulating film covering the gate bus line, a channel layer on the gate insulating film, a source electrode extending from the data bus line on one side of the channel layer, and the channel. A drain electrode disposed on the other side of the layer and in contact with the pixel electrode, and a dummy gate electrode disposed on a portion of the channel layer between the source electrode and the drain electrode, wherein the dummy gate electrode includes the gate bus line; Contact is made.

According to the present invention, since a pair of thin film transistors are formed in a unit pixel space, even if a defect occurs in any one of the thin film transistors, it is possible to drive the corresponding pixel through the other thin film transistor. Can be prevented. In addition, when all of the thin film transistors operate without defect, the current during the on operation is increased, thereby improving the switching capability of the thin film transistor.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view of a unit pixel of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view of a thin film transistor cut along line III-III ′, and FIG. 4 is another embodiment of the present invention. It is a top view of the unit pixel of the liquid crystal display device which concerns on an example.

First, referring to FIG. 2, a gate bus line 11 extends in a first direction on a glass substrate 20, and a data bus line 16 is perpendicular to the gate bus line 1 in a second direction. Extends to define the unit pixel P. Here, the gate bus line 11 is formed on the surface of the substrate 20, and a gate insulating film is interposed between the gate bus line 11 and the data bus line 16 so that these two lines 11 and 16 are connected. Electrically insulated.

The gate bus line 11 and the data bus line 16 include protrusions 11a and 16a extending into the unit pixel P. The protruding portion 11a of the gate bus line 11 protrudes in a direction parallel to the data bus line 16 and becomes a gate electrode of the thin film transistor. The protruding portion 16a of the data bus line 16 protrudes in a direction parallel to the gate bus line 11 and becomes a source electrode of the thin film transistor. In addition, the protrusion 16a of the data bus line 16 overlaps with one side portion of the protrusion 11a of the gate bus line 11.

A channel layer (not shown) and an etch stopper 14 are disposed on the protrusion 11a of the gate bus line 11. Accordingly, the protrusion 16a of the data bus line 16 overlaps one side of the etch stopper 14 on the protrusion of the gate bus line 11.

The pixel electrode 17 is disposed in the unit pixel space P. In this case, the pixel electrode 17 is formed of a transparent metal film such as indium tin oxide (ITO), as is well known.

An electrode pattern 16b is formed to contact the pixel electrode 17 while overlapping the other end of the protrusion 11a of the gate bus line 11, preferably the other end of the etch stopper 14. The electrode pattern 16b is formed together with the data bus line 16 and becomes a drain electrode of the thin film transistor.

Hereinafter, reference numeral 11a denotes a gate electrode, 16a denotes a source electrode, and 16b denotes a drain electrode.

The dummy gate electrode 18 is disposed between the source electrode 16a and the drain electrode 16b of the thin film transistor, wherein the dummy gate electrode 18 is in via contact with the gate bus line 11. In Fig. 2, reference numeral C1 denotes a contact portion between the dummy gate electrode 18 and the gate bus line 11.

Referring to FIG. 3, the formation of the thin film transistor and the dummy gate electrode 18 will be described in detail. First, a metal layer is deposited on the glass substrate 20, and then the metal layer is patterned to form a gate bus line. In this figure, only the projection 11a of the gate bus line, that is, the gate electrode, is shown. A gate insulating layer 12 is formed on the entire glass substrate 20 to cover the gate electrode 11a, and a channel layer 13 is formed on the gate insulating layer 12. An etch stopper 14 is then formed on the channel layer 13 to prevent loss of the channel layer 13 in a subsequent process. Next, a doped semiconductor layer 1 is formed on the etch stopper 14 and the channel layer 13, and the doped semiconductor layer 15 and the channel layer 13 are formed on the gate electrode 11a. Partial patterning to include.

Thereafter, a source / drain electrode metal layer is formed, and then source and drain electrodes 16a and 16b are formed so as to be disposed on both sides of the etch stopper 14 while exposing the etch stopper 14. Subsequently, an ITO layer is deposited on the substrate 20 and patterned to form the pixel electrode 17 to be disposed in the unit pixel space while being in contact with the drain electrode 16b.

Next, the gate insulating layer 12 is etched so that a predetermined portion of the gate bus line (not shown) is exposed, and then a metal layer is deposited again, and then the metal layer is patterned to contact the exposed gate bus line and the gate electrode. The dummy gate electrode 18 is formed so as to be disposed between the source electrode 16a and the drain electrode 16b in the upper portion (11a).

Thus, when the dummy gate electrode 18 is formed, the bottom using the gate electrode 11a as a gate while making the source and drain electrodes 16a and 16b and the channel layer 13 common to one thin film transistor region. A bottom type thin film transistor and a top type thin film transistor using the dummy gate electrode 18 as a gate are simultaneously formed.

Here, the bottom type thin film transistor and the top type thin film transistor are operated by the same signal, thereby performing the same operation. Accordingly, when the gate electrode 11a and the source electrode 16a, or the gate electrode 11a and the drain electrode 16b are shorted, the top thin film transistor having the gate of the dummy gate electrode 18 performs a switching action. On the contrary, when the dummy gate electrode 18 and the source electrode, or the dummy gate electrode 18 and the drain electrode 16b are shorted, the bottom type thin film transistor having the gate electrode 11a as a gate performs a switching action. do. Therefore, even if a defect occurs in any one of the thin film transistors, since the pixel switching can be performed by the other thin film transistor, the operation of the pixel electrode is not affected, and eventually, the pixel defect can be prevented.

In addition, when both the top thin film transistor and the bottom thin film transistor operate, the channel is simultaneously controlled by the upper dummy gate electrode 18 and the gate electrode 11a, so that the on current is increased, and as a result, The switching capability is improved.

FIG. 4 illustrates another exemplary embodiment of the present invention. In the present exemplary embodiment, when both the top thin film transistor and the bottom thin film transistor are shorted, the liquid crystal display may not affect the operation of the pixel electrode. Suggest.

As shown, a gate bus line 21 extends in a first direction on the glass substrate 30, and the data bus line 26 extends in a second direction perpendicular to the gate bus line 21. The unit pixel P is defined. The gate bus line 21 is formed on the surface of the substrate 30 as in the above-described embodiment, and the data bus line 26 is formed on the substrate 20 on which the gate bus line 21 is formed. The gate bus line 21 and the data bus line 26 are insulated from each other by a gate insulating film.

The gate bus line 21 includes a protrusion 21a extending into the unit pixel P, that is, a gate electrode. The protrusion 21a protrudes in a direction parallel to the data bus line 26.

First and second channel layers (not shown) above the protrusion 21a of the gate bus line 21 and above the gate bus line 21 near the intersection of the gate bus line 21 and the data bus line 26. The first etch stopper 24-1 and the second etch stopper 24-1 are formed on the first and second channel layers, respectively.

The data bus line 26 includes a first protrusion 26a-1 overlapping with one side of the first etch stopper 24-1 and a second protrusion 26a overlapping with one side of the second etch stopper 24-2. -2), wherein the protrusions 26a-1 and 26a-2 serve as source electrodes.

The pixel electrode 27 is disposed in the unit pixel P, and the first electrode pattern 26b-1 is provided to contact the pixel electrode 27 and overlap the first etch stopper 24-1. The second electrode pattern 26b-2 is provided to be in contact with the pixel electrode 27 and to overlap the second etch stopper 24-2. Here, the first and second electrode patterns 26b-1 and 26b-2 both serve as drain electrodes.

A gate bus line passes between the second protrusion 26b-1 and the second electrode pattern 26b-1 while passing between the first protrusion 26a-1 and the first electrode pattern 26b-1. The dummy gate electrode 28 is disposed to contact the 21. At this time, the dummy gate electrode 28 has a “┌” shape, and the shape of the dummy gate electrode 28 may vary somewhat depending on the arrangement of the channel layer.

Therefore, the unit pixel P of the liquid crystal display device includes the protrusion 21a of the protrusion 21 of the gate bus line, the first protrusion 26a-1 of the data bus line 26, and the first electrode pattern 26b-1. ), The first thin film transistor unit T1 including the first channel layer and the first etch stopper 24-1, and the second protrusions 26a-2 of the gate bus line 21 and the data bus line 26. ), A second thin film transistor portion T2 including the second electrode pattern 26b-2, the second channel layer, and the second etch stopper 24-2.

At this time, each of the thin film transistor units T1 and T2 has a top thin film transistor having the dummy gate electrode 28 as a gate, and a gate bus line 21 or a protrusion 21a of the gate bus line 21 as a gate. The bottom thin film transistor is formed at the same time.

Accordingly, even if a defect occurs in the first thin film transistor unit T1, the pixel electrode may be driven by the thin film transistors of the second thin film transistor unit T2, and a defect occurs in the second thin film transistor unit T2. In this case, the pixel electrode may be driven by the thin film transistors of the first thin film transistor unit T1. In addition, even if a defect occurs in any one of the first and second thin film transistor units T1 and T2, the pixel electrode may be driven by the remaining thin film transistors, so that no pixel defect occurs.

In addition, since four thin film transistors are formed in one unit pixel, all four thin film transistors are driven without defect. During on operation, the current is increased.

As described in detail above, according to the present invention, by forming at least one pair of thin film transistors in a unit pixel space, even if a defect occurs in any one of the thin film transistors, the pixel electrode can be driven by the remaining thin film transistors. Thus, pixel defects caused by defects in the thin film transistors are prevented.

In addition, if all of the thin film transistors operate without defect, the current is increased during the on operation, thereby improving the switching operation of the thin film transistor.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

Board; A gate bus line disposed in one direction of the substrate; A data bus line disposed perpendicular to the gate bus line; A gate insulating layer interposed between the gate bus line and the data bus line to insulate them from each other; At least one pair of thin film transistors disposed near an intersection of the gate bus line and the data bus line and using a channel layer in common; And And a pixel electrode disposed in contact with the thin film transistor in a unit pixel space surrounded by the gate bus line and the data bus line. The thin film transistor of claim 1, wherein the thin film transistor A gate bus line, a gate insulating film covering the gate bus line, a channel layer on the gate insulating film, a source electrode extending from the data bus line on one side of the channel layer, and a second side of the channel layer; And a drain electrode in contact with the pixel electrode, and a dummy gate electrode disposed on a portion of a channel layer between the source electrode and the drain electrode. The liquid crystal display of claim 2, wherein the dummy gate electrode is in contact with the gate bus line.