KR100340853B1 - Method for fabricating metal interconnection of semiconductor device - Google Patents
Method for fabricating metal interconnection of semiconductor device Download PDFInfo
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- KR100340853B1 KR100340853B1 KR1019950019129A KR19950019129A KR100340853B1 KR 100340853 B1 KR100340853 B1 KR 100340853B1 KR 1019950019129 A KR1019950019129 A KR 1019950019129A KR 19950019129 A KR19950019129 A KR 19950019129A KR 100340853 B1 KR100340853 B1 KR 100340853B1
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- Prior art keywords
- film
- etching
- titanium
- tungsten
- titanium nitride
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 42
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 24
- 239000010937 tungsten Substances 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 18
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000203 mixture Substances 0.000 claims abstract description 5
- 239000002131 composite material Substances 0.000 claims description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910021642 ultra pure water Inorganic materials 0.000 claims description 4
- 239000012498 ultrapure water Substances 0.000 claims description 4
- 238000005406 washing Methods 0.000 claims 2
- 230000003667 anti-reflective effect Effects 0.000 claims 1
- 239000002245 particle Substances 0.000 abstract description 3
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 22
- 239000007789 gas Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 239000012535 impurity Substances 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로써,특히 알루미늄 합금막과 텅스텐(W)막을 포함하여 이루어진 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring forming method comprising an aluminum alloy film and a tungsten (W) film.
콘택홀의 크기가 0.5㎛ 이하이면서 종횡비(ASPECT RATIO)가 1.5 이상인 고집적 반도체 소자의 금속배선 형성 방법의 한 예를 제1A도 내지 제1C도를 참조하여 설명하기로 한다. 먼저, 제1A도에 도시된 바와 같이, 실리콘 기판(1)상에 필드산화막(2)을 형성하고 게이트산화막(3), 도핑된 폴리실리콘막(4), 텅스텐실리사이드막(5) 및 TiN막(6)을 소정 두께로 형성하고 사진 식각법으로 게이트전극을 형성한다. 다음에 N-형 불순물을 이온 주입하여 저도핑 영역(7)을 형성하고 소정 두께의 산화막을 증착하고 비등방성 식각하여 산화막 스페이서(8)를 형성한 다음 N+형 불순물을 이온 주입하여 소스/드레인 영역(9)을 형성하므로써, 트랜지스터 부위를 형성한다. 다음에는 소정 두께의 TEOS(TETRA-ETHYL-ORTHO-SILICATE)산화 막(10) 및 BPSG(BORO-PHOSPHO-SILICATE-GLASS) 막(11)을 증착하고 고온 열처리하여 BPSG 막(11)을 플로우(FLOW)시키고 사진 식각법으로 소정의 콘택홀(도시 안됨)을 형성한 다음, 소정 두께의 Ti + TiN 복합막(12), 텅스텐막(13), 알루미늄 합금막(14) 및 TiN막(15)을 각각 적층하고 금속 배선 형성을 위한 감광막 패턴(16)을 형성한다. 다음에 제1B도에 도시된 바와 같이, BCl3및 Cl2가스를 사용한 비등방성 식각법으로 상기 TiN막(15) 및 알루미늄 합금막(14)을 식각한 다음, 상기 텅스텐막(13)을 SF6가스를 사용하여 식각하고, 상기 Ti + TiN 복합막(12)은 Cl2및 Ar 가스를 사용하여 식각한다. 다음에, 상기 감광막 패턴(16)을 제거하게 되면 제1C도에 도시된 바와 같이 금속 배선이 형성되게 된다. 그런데, 이와 같은 종래의 금속배선 제조 방법에 있어서는, 동일한 식각 장치내에서 상기 TiN막(15), 알루미늄 합금막(14), 텅스텐막(13) 및 Ti + TiN 복합막(12)을 식각할 경우 장시간이 소요되어 식각 장치에 무리가 가해지게 되며, 또한 Cl계 가스와 F계 가스의 혼합으로 식각 장치내에 불순물 입자의 발생이 증가할 가능성이 커져서 제조 수율이 저하하게 된다. 그리고 식각 종료 후에는 상기 감광막 패턴(16)이 장시간의 플라즈마에노출되어 경화되었기 때문에 제거하기 어려운 문제점이 있다.An example of a method for forming a metal wiring of a highly integrated semiconductor device having a contact hole of 0.5 μm or less and an aspect ratio of 1.5 or more will be described with reference to FIGS. 1A to 1C. First, as shown in FIG. 1A, the field oxide film 2 is formed on the silicon substrate 1, and the gate oxide film 3, the doped polysilicon film 4, the tungsten silicide film 5, and the TiN film are formed. (6) is formed to a predetermined thickness and a gate electrode is formed by photolithography. Next, N-type impurities are ion implanted to form a low doped region 7, an oxide film having a predetermined thickness is deposited and anisotropically etched to form an oxide spacer 8, and then ion implanted N + type impurities to source / drain regions. By forming (9), a transistor portion is formed. Next, a TEOS (TETRA-ETHYL-ORTHO-SILICATE) oxide film 10 and a BROPS-BOLIC-BOLIC-GLASS film 11 are deposited and subjected to high temperature heat treatment to flow the BPSG film 11 into a flow. And a predetermined contact hole (not shown) by a photolithography method, and then a Ti + TiN composite film 12, a tungsten film 13, an aluminum alloy film 14, and a TiN film 15 of a predetermined thickness are formed. Each of them is stacked and a photosensitive film pattern 16 for forming metal wirings is formed. Next, as shown in FIG. 1B, the TiN film 15 and the aluminum alloy film 14 are etched by anisotropic etching using BCl 3 and Cl 2 gas, and then the tungsten film 13 is SF. 6 gas is etched, and the Ti + TiN composite film 12 is etched using Cl 2 and Ar gas. Next, when the photoresist pattern 16 is removed, metal wirings are formed as shown in FIG. 1C. However, in the conventional metal wiring manufacturing method, when the TiN film 15, the aluminum alloy film 14, the tungsten film 13 and the Ti + TiN composite film 12 are etched in the same etching apparatus. It takes a long time to impose an excessive force on the etching apparatus, and also the possibility of increasing the generation of impurity particles in the etching apparatus by mixing Cl-based gas and F-based gas increases the manufacturing yield is lowered. After the etching is finished, the photoresist pattern 16 is exposed to the plasma for a long time, and thus hardened.
이러한 문제점을 해결하기 위한 종래의 다른 금속 배선 형성 방법에 있어서는, 상기 TiN막(15)과 알루미늄 합금막(14)을 식각하는 식각 장치와 상기 텅스텐막(13)과 Ti + TiN 복합 막(12)을 식각하는 식각 장치를 각각 다른 장치로 선택하여 공정을 진행하기도 한다. 그러나 상기 TiN막(15)과 알루미늄 합금막(14)을 식각한 후, 상기 감광막 패턴(16)이 남아있는 상태로 다른 식각 장치에서 텅스텐막(13)과 Ti + TiN 복합막(12)을 식각할 경우, 식각 장치에 감광막 성분의 불순물이 오염되어 텅스텐 에치백(ETCHBACK)과 같은 전면성(BLANKET) 식각 공정을 혼용할 수 없게 되며, 식각 종료 후에는 상기 감광막 패턴(16)이 장시간의 플라즈마에 노출되어 경화되었기 때문에 제거하기가 어려운 문제점이 여전히 남아있게 된다.In another conventional metal wiring forming method for solving this problem, an etching apparatus for etching the TiN film 15 and the aluminum alloy film 14, the tungsten film 13 and the Ti + TiN composite film 12 In some cases, the etching apparatus for etching is selected as a different apparatus to proceed with the process. However, after the TiN film 15 and the aluminum alloy film 14 are etched, the tungsten film 13 and the Ti + TiN composite film 12 are etched in another etching apparatus while the photoresist pattern 16 remains. In this case, impurities in the photoresist layer may be contaminated in the etching apparatus, so that the BLANKET process, such as tungsten etchback, may not be mixed. Problems remain difficult to remove because they have been exposed and cured.
따라서, 전술한 문제점을 해결하기 위해 안출된 본 발명은, 상기 티타늄 나이트라이드막과 알루미늄 합금막을 식각한 다음에 감광막 패턴을 제거하고, 노출된 티타늄 나이트라이드막을 식각 마스크로 하여 텅스텐막을 식각한 다음에 노출된 티타늄 나이트라이드막과 티타늄-티타늄 나이트라이드 복합막을 동시에 식각함으로써, 파티클에 의한 오염을 방지하고 감광막의 경화를 방지할 수 있는 금속 배선 형성 방법을 제공하는 것을 목적으로 한다.Therefore, in order to solve the above problems, the present invention, after etching the titanium nitride film and the aluminum alloy film to remove the photoresist pattern, and etching the tungsten film using the exposed titanium nitride film as an etching mask An object of the present invention is to provide a method for forming a metal wiring which can prevent contamination by particles and harden the photosensitive film by simultaneously etching the exposed titanium nitride film and the titanium-titanium nitride composite film.
본 발명에 따른 반도체 소자의 금속 배선 형성 방법은, 모스 트랜지스터가 형성되고 상기 트랜지스터의 접합 영역에 콘택홀이 형성되어 있는 전체 구조 상부에, 소정 두께의 티타늄-티타늄 나이트라이드 복합막, 텅스텐막, 알루미늄 합금막 및 반사 방지막을 각각 적층하는 단계와, 금속 배선을 정의하기 위한 소정의 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 식각 마스크로 하여, 비등방성 식각법으로 상기 반사 방지막 및 상기 알루미늄 합금막을 식각하는 단계와, 상기 감광막 패턴을 제거하는 단계와, 상기 노출된 반사 방지막을 식각 마스크로 하여 상기 텅스텐막을 식각하는 단계 및 상기 노출된 반사 방지막과 티타늄-티타늄 나이트라이드 복합막을 식각하는 단계를 포함하는 것을 특징으로 한다.In the method of forming a metal wiring of a semiconductor device according to the present invention, a titanium-titanium nitride composite film, a tungsten film, and a predetermined thickness are formed on an entire structure in which a MOS transistor is formed and a contact hole is formed in a junction region of the transistor. Laminating an alloy film and an antireflection film, forming a predetermined photoresist pattern for defining metal wiring, and using the photoresist pattern as an etching mask, the antireflection film and the aluminum alloy film by anisotropic etching. Etching, removing the photoresist pattern, etching the tungsten film using the exposed antireflection film as an etch mask, and etching the exposed antireflection film and the titanium-titanium nitride composite film. It is characterized by.
이제 본 발명의 실시예에 대하여 첨부도면을 참조하여 보다 상세하게 설명 되게 된다. 먼저 제 2A도에 도시된 바와 같이, 실리콘 기판(21) 상에 필드 산화막(22)을 형성하고 게이트 산화막(23), 도핑된 폴리실리콘막(24), 텅스텐 실리사이드막(25) 및 티타늄 나이트라이드(TiN)막(26)을 소정 두께로 형성하고 사진 식각법으로 게이트 전극을 형성한다. 다음에 N-형 불순물을 이온 주입하여 저도핑 드레인 영역(27)을 형성하고 소정 두께의 산화막을 증착한 다음, 비등방성 식각하여 산화막 스페이서(28)를 형성하고 N+형 불순물을 이온 주입하여 소스/드레인 영역(29)을 형성하므로써 트랜지스터 구조를 형성한다. 다음에, 소정 두께의 TEOS(TETRA-ETHYL-ORTHO-SILICATE) 산화막(30) 및 BPSG(BORO-PHOSPHO-SILICATE-GLASS) 막(31)을 증착하고 고온 열처리하여 BPSG 막(31)을 플로우(FLOW)시키고 사진 식각법으로 소정의 콘택홀(도시 안됨)을 형성하고 소정 두께의 티타늄-티타늄 나이트라이드(Ti + TiN) 복합막(32), 텅스텐막(33), 알루미늄 합금막(34) 및 TiN막(35)을 각각 적층하고, 금속 배선 형성을 위한 소정의 감광막 패턴(36)을 형성한다. 다음에는 제 2B도에 도시된 바와 같이, 감광막 패턴(36)을 식각 마스크로이용하여 상기 TiN막(35) 및 알루미늄 합금막(34)을 BCl3과 Cl2가스를 사용한 비등방성 식각법으로 식각하므로써 상기 텅스텐막(33)을 노출시킨다. 다음에 동일한 장치에서 상기 감광막 패턴(36)을 O2가스를 기본으로 사용하여 제거하고, 초순수(DEIONIZED WATER)를 사용하여 세척한다.Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. First, as shown in FIG. 2A, the field oxide film 22 is formed on the silicon substrate 21, and the gate oxide film 23, the doped polysilicon film 24, the tungsten silicide film 25, and titanium nitride are formed. A (TiN) film 26 is formed to a predetermined thickness and a gate electrode is formed by photolithography. Next, an N-type impurity is ion implanted to form a low doped drain region 27, an oxide film having a predetermined thickness is deposited, and then anisotropically etched to form an oxide spacer 28, and an N + type impurity is ion implanted to form a source / The transistor structure is formed by forming the drain region 29. Next, a TEOS (TETRA-ETHYL-ORTHO-SILICATE) oxide film 30 and a BORO-PHOSPHO-SILICATE-GLASS (31) film 31 having a predetermined thickness are deposited and subjected to high temperature heat treatment to flow the BPSG film 31 in a flow. And a predetermined contact hole (not shown) by a photolithography method, and a titanium-titanium nitride (Ti + TiN) composite film 32, tungsten film 33, aluminum alloy film 34 and TiN of a predetermined thickness Each of the films 35 is laminated, and a predetermined photosensitive film pattern 36 for forming metal wirings is formed. Next, as shown in FIG. 2B, the TiN layer 35 and the aluminum alloy layer 34 are etched by anisotropic etching using BCl 3 and Cl 2 gas using the photoresist pattern 36 as an etching mask. Thus, the tungsten film 33 is exposed. Next, in the same apparatus, the photoresist pattern 36 is removed using O 2 gas as a base, and washed using ultra pure water (DEIONIZED WATER).
특히, 상기 감광막 패턴(36) 제거시에 O2, CF4, CH3OH, H2O 등의 가스를 적정 비율로 혼합하여 사용하며, 초순수 세척시에 10% 이내의 현상액을 첨가하여 감광막 제거 능력을 향상토록 하는 것이 바람직하다. 다음에는 제 2C도에 도시된 바와 같이, 상기 노출된 TiN막(35)을 식각 마스크로 하여 상기 텅스텐막(33)을 SF6가스를 사용하여 식각한 다음에, 노출된 Ti + TiN 복합막(32) 및 TiN막(35)을 Cl2와 Ar 가스를 사용하여 동시에 식각함으로써 금속배선을 형성한다. 이때, 상기 텅스텐 막(33) 식각시에는 상기 TiN막(35) 및 알루미늄 합금막(34)를 식각하는 장치와 다른 식각 장치를 사용하고, W : TiN의 식각비가 30 : 1 이상의 식각 속도 차이를 갖도록 사용하는 가스, 압력, 전력, 온도 등을 적절하게 조절하는 것이 바람직하다.In particular, when removing the photoresist pattern 36, a mixture of gases such as O 2 , CF 4 , CH 3 OH, H 2 O and the like is used at an appropriate ratio, and when the ultrapure water is washed, a developer within 10% is added to remove the photoresist. It is desirable to improve the ability. Next, as shown in FIG. 2C, the tungsten film 33 is etched using SF 6 gas using the exposed TiN film 35 as an etching mask, and then the exposed Ti + TiN composite film ( 32) and the TiN film 35 are simultaneously etched using Cl 2 and Ar gas to form metal wiring. In this case, when etching the tungsten film 33, an etching apparatus different from the apparatus for etching the TiN film 35 and the aluminum alloy film 34 is used, and the etching rate difference of W: TiN is 30: 1 or more. It is preferable to appropriately adjust the gas, pressure, electric power, temperature, and the like to be used.
고집적 반도체 소자 제조시 전술한 바와 같은 본 발명을 이용하여 금속 배선을 형성 하므로써, 텅스텐막을 식각하는 장치에 감광막 패턴이 형성되어 있는 웨이퍼를 사용하지 않으므로 텅스텐 에치백과 같은 전면 식각 공정을 혼용할 수 있게 되어 생산 효율을 향상할 수 있으며, 알루미늄 합금막을 식각하고 감광막 패턴을 제거함으로써 감광막 제거를 용이하게 할 수 있게 되어 반도체 제품의 제조 수율및 신뢰성을 향상시키는 효과가 있다.By forming the metal wiring by using the present invention as described above in the fabrication of highly integrated semiconductor devices, since the wafer having the photosensitive film pattern is not used in the device for etching the tungsten film, it is possible to use a front surface etching process such as tungsten etch back. Production efficiency can be improved, and by etching the aluminum alloy film and removing the photoresist pattern, the photoresist can be easily removed, thereby improving the manufacturing yield and reliability of the semiconductor product.
제 1A도 내지 제 1C도는 종래의 금속 배선 형성 방법에 따른 제조 공정도.1A to 1C are manufacturing process diagrams according to a conventional metal wiring forming method.
제 2A도 내지 제 2C도는 본 발명의 금속 배선 형성 방법에 따른 제조 공정도.2A to 2C are manufacturing process diagrams according to the metal wiring forming method of the present invention.
※ 도면의 주요 부분에 대한 부호의 설명 ※※ Explanation of code about main part of drawing ※
32 : 티타늄-티타늄 나이트라이드(Ti + TiN) 복합막32: titanium-titanium nitride (Ti + TiN) composite film
33 : 텅스텐막 34 : 알루미늄 합금막33 tungsten film 34 aluminum alloy film
35 : TiN막 36 : 감광막 패턴35 TiN film 36 Photosensitive film pattern
Claims (8)
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| KR1019950019129A KR100340853B1 (en) | 1995-06-30 | 1995-06-30 | Method for fabricating metal interconnection of semiconductor device |
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