KR100338945B1 - Wafer scale package and the manufacturing method - Google Patents
Wafer scale package and the manufacturing method Download PDFInfo
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- KR100338945B1 KR100338945B1 KR1019990057111A KR19990057111A KR100338945B1 KR 100338945 B1 KR100338945 B1 KR 100338945B1 KR 1019990057111 A KR1019990057111 A KR 1019990057111A KR 19990057111 A KR19990057111 A KR 19990057111A KR 100338945 B1 KR100338945 B1 KR 100338945B1
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- wafer
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- bonded
- lead wire
- circuit board
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- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000011247 coating layer Substances 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 20
- 239000011810 insulating material Substances 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000010949 copper Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- GSJBKPNSLRKRNR-UHFFFAOYSA-N $l^{2}-stannanylidenetin Chemical compound [Sn].[Sn] GSJBKPNSLRKRNR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 웨이퍼 스케일 패키지 및 그 제조방법에 관한 것으로서, 본 발명은 복수개의 칩패드(53)가 형성된 웨이퍼(51)와, 상기 웨이퍼(51)의 상면에 부착된 소정 패턴의 금속막(57)이 형성된 절연테이프(55)와, 상기한 각각의 칩패드(53)와 절연테이프(55)의 금속막(57)에 양끝단이 본딩되고 중간의 팁 부분이 인쇄회로기판에의 실장시 상기 인쇄회로기판의 랜드에 접합되는 복수개의 리드와이어(59)와, 상기 리드와이어(59)들 사이의 공간을 메워 인접한 리드와이어(59)간의 절연이 이루어지도록 상기 리드와이어(59)가 본딩된 부위에 형성된 절연코팅층(61)과, 상기 리드와이어(59)의 강도 강화를 위해 리드와이어(59)의 팁 부분에 형성된 도금층(63)을 포함하여 구성됨으로써 상기 리드와이어(59) 사이에서 발생되는 상호간의 전기적 간섭이 방지되는 동시에 상기 리드와이어(59)의 강도가 강화되어 외부의 충격에 별 영향을 받지 않는 견고한 구조가 되고, 이로 인해 패키지의 품질 및 신뢰성이 향상되도록 한 것이다.The present invention relates to a wafer scale package and a method of manufacturing the same. The present invention relates to a wafer 51 having a plurality of chip pads 53 formed thereon, and a metal film 57 having a predetermined pattern attached to an upper surface of the wafer 51. Both ends are bonded to the formed insulating tape 55 and the metal film 57 of each of the chip pad 53 and the insulating tape 55, and the middle tip portion is printed on the printed circuit board. A portion of the lead wire 59 bonded to the plurality of lead wires 59 bonded to the lands of the circuit board and the lead wires 59 to fill the space between the lead wires 59 to insulate the adjacent lead wires 59. The insulating coating layer 61 and the plating layer 63 formed on the tip portion of the lead wire 59 to enhance the strength of the lead wire 59 are formed to be mutually generated between the lead wires 59. The electrical interference is prevented at the same time The strength of the wire (59) is a rigid reinforced structure that is not affected by the external impact and, to a so This improves the quality and reliability of the package.
Description
본 발명은 웨이퍼 스케일 패키지 및 그 제조방법에 관한 것으로서, 특히 웨이퍼 상태에서의 일괄 생산이 가능한 웨이퍼 스케일 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer scale package and a method of manufacturing the same, and more particularly, to a wafer scale package capable of batch production in a wafer state and a method of manufacturing the same.
도 1은 종래 기술에 따른 웨이퍼 스케일 패키지를 제조하는 과정에서 웨이퍼에 리드와이어가 형성된 상태가 도시된 정면도이고, 도 2는 도 1의 A부 구조가 상세하게 도시된 단면도이다.1 is a front view illustrating a state in which a lead wire is formed on a wafer in a process of manufacturing a wafer scale package according to the prior art, and FIG. 2 is a cross-sectional view illustrating the structure of part A of FIG. 1 in detail.
상기한 도 1 및 도 2를 참조하여 종래 기술에 따라 웨이퍼 스케일 패키지를 제조하는 과정을 설명하면 다음과 같다.A process of manufacturing a wafer scale package according to the prior art will be described with reference to FIGS. 1 and 2 as follows.
먼저, 복수개의 칩패드(3)가 형성된 웨이퍼(1)에 와이어 본딩을 수행하여 상기한 각각의 칩패드(3)에 일단이 본딩된 스프링 형태의 리드와이어(5)를 형성한다.First, wire bonding is performed on a wafer 1 on which a plurality of chip pads 3 are formed to form a spring-like lead wire 5 having one end bonded to each of the chip pads 3 described above.
이때, 상기 리드와이어(5)는 와이어 본더에 의해 와이어가 칩패드(3)에 1차 본딩되어 스프링 형태로 형성된 후 상기한 와이어 본더의 자체 제어에 의해 끊어지는 방식으로 형성된다.In this case, the lead wire 5 is formed in a manner that the wire is first bonded to the chip pad 3 by a wire bonder and formed in a spring shape, and then broken by self-control of the wire bonder.
이후, 상기 리드와이어(5)의 강도 강화를 위해 리드와이어(5)의 표면에 도금을 실시하여 니켈(Ni), 구리(Cu), 은(Ag)과 같은 금속 재질의 도금막(7)을 형성한다.Thereafter, in order to strengthen the strength of the lead wire 5, the surface of the lead wire 5 is plated to form a plated film 7 made of metal such as nickel (Ni), copper (Cu), and silver (Ag). Form.
상기와 같이 리드와이어(5)의 표면에 도금막(7)이 형성되면 웨이퍼(1)를 적정크기로 절단하는 소잉(Sawing) 공정을 실시하여 패키지를 완성한다.When the plating film 7 is formed on the surface of the lead wire 5 as described above, a sawing process of cutting the wafer 1 to an appropriate size is performed to complete the package.
그러나, 상기와 같은 종래의 웨이퍼 스케일 패키지 및 그 제조방법은 리드와이어(5)들이 개별적으로 노출되어 있는 구조이기 때문에 상기 리드와이어(5)의 강도가 약해 외부의 충격에 취약한 구조가 될 수밖에 없고, 이로 인해 패키지의 성능 및 신뢰성이 떨어지는 문제점이 있었다.However, the conventional wafer scale package and its manufacturing method as described above have a structure in which the lead wires 5 are individually exposed, so that the strength of the lead wires 5 is weak, so that the structure is vulnerable to external impact. As a result, the performance and reliability of the package was inferior.
또한, 상기한 종래 기술은 리드와이어(5)들 사이에서 발생되는 상호간의 전기적 간섭을 방지할 수 있는 구조를 구비하고 있지 않기 때문에 상기 리드와이어(5)간에 전기적 자장에 의한 간섭이 발생되어 패키지의 작동불량이 유발되고, 특히 미세 피치의 리드와이어(5)를 갖는 구조에는 매우 부적합한 문제점이 있었다.In addition, since the above-described conventional technology does not have a structure that can prevent electrical interference between the lead wires 5, interference by the electric magnetic field is generated between the lead wires 5 Malfunction is caused, and in particular, there is a problem that is very unsuitable for a structure having a fine pitch lead wire (5).
상기한 바와 같은 문제점을 감안하여 안출한 본 발명의 목적은, 리드와이어 사이에서 발생되는 상호간의 전기적 간섭이 방지되는 동시에 상기 리드와이어의 강도가 강화되어 외부의 충격에 별 영향을 받지 않는 견고한 구조가 되도록 하는 웨이퍼 스케일 패키지 및 그 제조방법을 제공함에 있다.The object of the present invention devised in view of the above-described problems is to prevent the electrical interference generated between the lead wires and at the same time the strength of the lead wire is strengthened to have a robust structure that is not affected by external impact To provide a wafer scale package and a method of manufacturing the same.
도 1은 종래 기술에 따른 웨이퍼 스케일 패키지를 제조하는 과정에서 웨이퍼에 리드와이어가 형성된 상태가 도시된 정면도,1 is a front view showing a state in which a lead wire is formed on a wafer in the process of manufacturing a wafer scale package according to the prior art;
도 2는 도 1의 A부 구조가 상세하게 도시된 단면도,2 is a cross-sectional view showing in detail the structure of part A of FIG.
도 3은 본 발명에 따른 웨이퍼 스케일 패키지의 구조가 도시된 단면도,3 is a cross-sectional view showing the structure of a wafer scale package according to the present invention;
도 4는 본 발명에 따른 웨이퍼 스케일 패키지가 인쇄회로기판에 실장된 상태가 도시된 단면도,4 is a cross-sectional view illustrating a state in which a wafer scale package according to the present invention is mounted on a printed circuit board;
도 5는 본 발명에 따른 웨이퍼 스케일 패키지를 제조하는 과정이 순서대로 도시된 단면도이다.5 is a cross-sectional view sequentially showing a process of manufacturing a wafer scale package according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
51 : 웨이퍼 53 : 칩패드51: wafer 53: chip pad
55 : 절연테이프 57 : 금속막55: insulating tape 57: metal film
59 : 리드와이어 61 : 절연코팅층59: lead wire 61: insulating coating layer
63 : 도금층 71 : 인쇄회로기판63: plating layer 71: printed circuit board
73 : 랜드73: land
상기한 바와 같은 본 발명의 목적을 달성하기 위하여, 복수개의 칩패드가 형성된 웨이퍼와, 상기 웨이퍼의 상면에 부착된 소정 패턴의 금속막이 형성된 절연테이프와, 상기한 각각의 칩패드와 절연테이프의 금속막에 양끝단이 본딩되고 중간의 팁 부분이 인쇄회로기판에의 실장시 상기 인쇄회로기판의 랜드에 접합되는 복수개의 리드와이어와, 상기 리드와이어들 사이의 공간을 메워 인접한 리드와이어간의 절연이 이루어지도록 상기 리드와이어가 본딩된 부위에 형성된 절연코팅층을 포함한 것을 특징으로 하는 웨이퍼 스케일 패키지가 제공된다.In order to achieve the object of the present invention as described above, a wafer having a plurality of chip pads formed, an insulating tape formed with a metal film of a predetermined pattern attached to the upper surface of the wafer, and the metal of each of the above chip pads and insulating tape Both ends of the film are bonded to each other, and a plurality of lead wires joined to lands of the printed circuit board when the middle tip portion is mounted on the printed circuit board and the space between the lead wires are filled to insulate the adjacent lead wires. A wafer scale package is provided, including an insulating coating layer formed on a portion where the lead wire is bonded.
또한, 본 발명에 의하면, 웨이퍼의 상면에 소정 패턴의 금속막이 형성된 절연테이프를 부착하는 제 1과정과, 상기 웨이퍼의 칩패드와 절연테이프의 금속막에 각각 와이어 본딩을 수행하여 상기 칩패드와 절연테이프에 양끝단이 본딩된 리드와이어를 형성하는 제 2과정과, 상기 리드와이어들 사이의 공간이 메워져 인접한 리드와이어간의 절연이 이루어지도록 상기 리드와이어가 본딩된 부위에 절연물질을 코팅한 후 경화시켜 절연코팅층을 형성하는 제 3과정과, 상기 리드와이어 중간의 팁 부분이 인쇄회로기판에의 실장시 상기 인쇄회로기판의 랜드에 접합되도록 상기한 팁 부분에 형성된 절연코팅층을 제거하는 제 4과정과, 상기 웨이퍼를 적정 크기로 절단하여 패키지를 완성하는 제 5과정으로 이루어진 것을 특징으로 하는 웨이퍼 스케일 패키지의 제조방법이 제공된다.In addition, according to the present invention, the first step of attaching an insulating tape having a metal film having a predetermined pattern on the upper surface of the wafer, and wire bonding to the chip pad of the wafer and the metal film of the insulating tape, respectively, to insulate the chip pad from the wafer. A second process of forming lead wires bonded to both ends of the tape, and coating and curing an insulating material on a portion where the lead wires are bonded so that the space between the lead wires is filled to insulate the adjacent lead wires. A third process of forming an insulation coating layer, a fourth process of removing the insulation coating layer formed on the tip portion such that the tip portion of the lead wire is joined to the land of the printed circuit board when the lead wire is mounted on the printed circuit board; The wafer scale package, characterized in that the fifth step of completing the package by cutting the wafer to a suitable size This crude method is provided.
이하, 본 발명의 실시 예를 첨부한 도면을 참조하여 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명에 따른 웨이퍼 스케일 패키지의 구조가 도시된 단면도이고, 도 4는 본 발명에 따른 웨이퍼 스케일 패키지가 인쇄회로기판에 실장된 상태가 도시된 단면도이고, 도 5는 본 발명에 따른 웨이퍼 스케일 패키지를 제조하는 과정이 순서대로 도시된 단면도이다.3 is a cross-sectional view showing the structure of a wafer scale package according to the present invention, Figure 4 is a cross-sectional view showing a state in which the wafer scale package according to the invention mounted on a printed circuit board, Figure 5 is a wafer according to the present invention The process of manufacturing the scale package is a cross-sectional view shown in sequence.
상기한 도 3 및 도 4를 참조하면, 본 발명에 따른 웨이퍼 스케일 패키지는, 복수개의 칩패드(53)가 형성된 웨이퍼(51)와, 상기 웨이퍼(51)의 상면에 부착된 소정 패턴의 금속막(57)이 형성된 절연테이프(55)와, 상기한 각각의 칩패드(53)와 절연테이프(55)의 금속막(57)에 양끝단이 본딩되고 중간의 팁 부분이 인쇄회로기판(71)에의 실장시 상기 인쇄회로기판(71)의 랜드(73)에 접합되는 복수개의 리드와이어(59)와, 상기 리드와이어(59)들 사이의 공간을 메워 인접한 리드와이어(59)간의 절연이 이루어지도록 상기 리드와이어(59)가 본딩된 부위에 형성된 절연코팅층(61)과, 상기 리드와이어(59)의 강도 강화를 위해 리드와이어(59)의 팁 부분에 형성된 도금층(63)을 포함하여 구성된다.3 and 4, the wafer scale package according to the present invention includes a wafer 51 having a plurality of chip pads 53 formed thereon, and a metal film having a predetermined pattern attached to an upper surface of the wafer 51. Both ends are bonded to the insulating tape 55 on which the 57 is formed, and the metal film 57 of each of the chip pads 53 and the insulating tape 55 described above, and the tip portion in the middle thereof is a printed circuit board 71. In order to provide insulation between adjacent lead wires 59 by filling a space between the plurality of lead wires 59 bonded to the lands 73 of the printed circuit board 71 and the lead wires 59 when they are mounted on the wires. Insulation coating layer 61 formed on a portion where the lead wire 59 is bonded, and a plating layer 63 formed on the tip portion of the lead wire 59 to strengthen the lead wire 59.
또한, 상기 도금층(63)은 리드와이어(59)의 팁 부분에 형성되어 인쇄회로기판(71)에 대한 최종적인 접촉단자 역할을 하는 것으로서, 니켈(Ni), 구리(Cu), 틴(Tin)과 같은 금속 재질로 되어 있다.In addition, the plating layer 63 is formed on the tip of the lead wire 59 to serve as a final contact terminal for the printed circuit board 71. Nickel (Ni), copper (Cu), tin (Tin) It is made of metal.
상기와 같이 구성된 본 발명에 따른 웨이퍼 스케일 패키지를 제조하는 과정을 도 4를 참조하여 설명하면 다음과 같다.A process of manufacturing a wafer scale package according to the present invention configured as described above with reference to FIG. 4 is as follows.
먼저, 웨이퍼(51)의 상면에 소정 패턴의 절연테이프(55)를 부착한 후, 와이어 본더를 통해 상기 웨이퍼(51)의 칩패드(53)와 절연테이프(55)에 각각 와이어 본딩을 수행하여 상기 칩패드(53)와 절연테이프(55)에 양끝단이 본딩된 리드와이어(59)를 형성한다.First, the insulating tape 55 of a predetermined pattern is attached to the upper surface of the wafer 51, and then wire bonding is performed on the chip pad 53 and the insulating tape 55 of the wafer 51 through a wire bonder. Lead wires 59 having both ends bonded to the chip pad 53 and the insulating tape 55 are formed.
이때, 상기 절연테이프(55)의 상부에는 이후의 리드와이어(59)의 본딩이 용이하도록 금속막(57)이 형성된 상태이다.In this case, the metal film 57 is formed on the insulating tape 55 to facilitate bonding of the lead wire 59.
상기와 같이 리드와이어(59)의 본딩 작업이 끝나면 상기 리드와이어(59)들 사이의 공간이 메워져 인접한 리드와이어(59)간의 절연이 이루어지도록 상기 리드와이어(59)가 본딩된 부위에 열경화성 절연물질을 코팅한다.When the bonding operation of the lead wire 59 is completed as described above, the thermosetting insulating material is bonded to the portion where the lead wire 59 is bonded to fill the space between the lead wires 59 to insulate the adjacent lead wires 59. Coating.
이때, 상기 절연테이프(55)가 절연물질에 대한 댐(Dam) 역할을 하게 되어 상기 절연물질은 원활하게 코팅되게 된다.At this time, the insulating tape 55 serves as a dam for the insulating material so that the insulating material is smoothly coated.
이후, 상기 절연물질이 코팅된 웨이퍼(51)를 오븐에 넣고 소정 온도에서 일정 시간동안 경화시킴으로써 절연코팅층(61)을 형성한다.Thereafter, the insulating material-coated wafer 51 is placed in an oven and cured at a predetermined temperature for a predetermined time to form the insulating coating layer 61.
상기와 같이 리드와이어(59)가 본딩된 부위에 절연코팅층(61)이 형성되면 식각조(75)의 식각액(76)에 상기 리드와이어(59)의 팁 부분을 담그는 방식으로 상기 팁 부분에 형성된 절연코팅층(61)을 제거한다.When the insulating coating layer 61 is formed on the portion where the lead wire 59 is bonded as described above, the tip portion of the lead wire 59 is immersed in the etching solution 76 of the etching bath 75. The insulating coating layer 61 is removed.
이후, 상기 리드와이어(59)의 팁 부분을 도금조(77)의 도금액(78)에 담그는 방식으로 상기 팁 부분에 니켈, 구리, 틴과 같은 금속 재질을 갖는 도금층(63)을 형성한다.Thereafter, a plating layer 63 having a metal material such as nickel, copper, or tin is formed on the tip portion by dipping the tip portion of the lead wire 59 into the plating solution 78 of the plating bath 77.
이때, 상기 도금층(63)은 리드와이어(59)의 강도 강화를 위한 것으로서, 결과적으로는 패키지의 실장시 인쇄회로기판(71)의 랜드(73)에 직접 접합되게 되어 최종적인 접촉단자 역할을 하게 된다.At this time, the plating layer 63 is to enhance the strength of the lead wire 59, and as a result, the plating layer 63 is directly bonded to the land 73 of the printed circuit board 71 when the package is mounted to serve as a final contact terminal. do.
또한, 상기 도금액(78)으로는 전기도금 및 무전해도금이 가능한 동시에 상기 절연코팅층(61)이 녹지 않을 수 있는 용액을 선택하여 사용한다.In addition, the plating solution 78 may be used by selecting a solution that can be electroplated and electroless plated and the insulation coating layer 61 is not melted.
상기한 바와 같이 리드와이어(59)의 팁 부분에 도금층(63)까지 모두 형성되면 웨이퍼(51)를 적정 크기로 절단하는 소잉(Sawing) 공정을 실시하여 패키지를 완성한 후, 이렇게 완성된 패키지를 인쇄회로기판(71)에 실장한다.As described above, when all of the plating layer 63 is formed on the tip portion of the lead wire 59, a sawing process of cutting the wafer 51 to an appropriate size is completed to complete the package, and then the finished package is printed. It is mounted on the circuit board 71.
한편, 본 발명의 다른 실시 예에 의하면, 웨이퍼를 자르는 소잉 공정을 리드와이어(59)를 형성한 후 바로 실시하고, 그 후에 절연코팅층(61)과 도금층(63)을 각각 형성하는 방식으로 패키지를 제조할 수도 있다.Meanwhile, according to another embodiment of the present invention, the sawing process of cutting the wafer is performed immediately after the lead wire 59 is formed, and then the package is formed in such a manner as to form the insulating coating layer 61 and the plating layer 63, respectively. It can also manufacture.
이상에서 설명한 바와 같이 본 발명에 따른 웨이퍼 스케일 패키지 및 그 제조방법은, 리드와이어(59)들 사이의 공간을 메우도록 형성된 절연코팅층(61)에 의해 리드와이어(59) 사이에서 발생되는 상호간의 전기적 간섭이 방지되어 이로 인한 패키지의 작동불량이 제거되고, 특히 미세 피치의 리드와이어(59)를 갖는 구조의 패키지에 아주 효과적인 이점이 있다.As described above, the wafer scale package and the method of manufacturing the same according to the present invention are formed by the insulating coating layer 61 formed to fill the space between the lead wires 59. Interference is prevented, thereby resulting in a malfunction of the package, which is particularly effective for packages of structures with fine pitch leadwires 59.
또한, 본 발명은 리드와이어(59)가 본딩된 부위에 형성된 절연코팅층(61)과 중간의 팁 부분에 형성된 도금층(63)에 의해 상기 리드와이어(59)의 강도가 강화되어 외부의 충격에 별 영향을 받지 않는 견고한 구조를 가질 수 있게 되고, 이로 인해 패키지의 신뢰성이 향상되는 이점이 있다.In addition, according to the present invention, the strength of the lead wire 59 is strengthened by the insulating coating layer 61 formed on the portion where the lead wire 59 is bonded and the plating layer 63 formed on the tip portion of the intermediate portion, so that the impact of the lead wire 59 is increased. It is possible to have a robust structure that is not affected, thereby improving the reliability of the package.
Claims (6)
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| KR1019990057111A KR100338945B1 (en) | 1999-12-13 | 1999-12-13 | Wafer scale package and the manufacturing method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990039990A (en) * | 1997-11-15 | 1999-06-05 | 구본준 | Manufacturing method of chip size semiconductor package |
| KR19990049144A (en) * | 1997-12-12 | 1999-07-05 | 구본준 | Chip size semiconductor package and manufacturing method thereof |
| KR100214545B1 (en) * | 1996-12-28 | 1999-08-02 | 구본준 | Making method of chip size semicomductor package |
| KR20000059861A (en) * | 1999-03-09 | 2000-10-16 | 김영환 | A wire arrayed chip size package and the fabrication method thereof |
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1999
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100214545B1 (en) * | 1996-12-28 | 1999-08-02 | 구본준 | Making method of chip size semicomductor package |
| KR19990039990A (en) * | 1997-11-15 | 1999-06-05 | 구본준 | Manufacturing method of chip size semiconductor package |
| KR19990049144A (en) * | 1997-12-12 | 1999-07-05 | 구본준 | Chip size semiconductor package and manufacturing method thereof |
| KR20000059861A (en) * | 1999-03-09 | 2000-10-16 | 김영환 | A wire arrayed chip size package and the fabrication method thereof |
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