KR100337203B1 - Input data storage circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to an input data storage circuit of a semiconductor memory device, and more particularly, by sequentially storing input data entered into an input pad in a latch circuit of the last stage and outputting them at once, thereby reducing the flow of the entire data. The present invention relates to an input data storage circuit of a semiconductor memory device which reduces a chip size and removes unnecessary signals.

An input data storage circuit of a semiconductor memory device according to the present invention for realizing this includes at least a receiving buffer circuit for inputting serial data coming into an input pad, wherein the clock signal, pulse signal, and reset signal are respectively provided. Pulse shifter means for outputting a plurality of shifted pulse signals in response to each of the following clock signals when the reset signal has a first logic and the clock signal toggles as an input; and in the pulse shifter means And a plurality of latch means for accepting and storing the input data output from the receiving buffer circuit when the output pulse signal is input as the input and the pulse signal has the second logic.

Description

Input data storage circuit of semiconductor memory device

The present invention relates to an input data (Data) storage circuit of a semiconductor memory device, and more particularly, to sequentially store the input data entered into the input pad (PAD) immediately in the latch circuit of the last stage and then output them all at once. The present invention relates to an input data storage circuit of a semiconductor memory device which reduces the size of a chip and removes unnecessary signals by reducing the flow of entire data.

The present invention can be applied to all semiconductor memory devices using a method of serially receiving data and storing them in parallel, and in particular, it can be used in RAMBUS DRAM.

FIG. 1 is a block diagram illustrating a conventional method of storing input data entered into a pad in parallel using several latch circuits, and then sequentially storing the input data into a latch circuit at a final stage.

As shown in the prior art, each data received through the pad PAD is latched by sequentially passing through each latch block in synchronization with a control signal generated by a clock, and then internal control. Two bits of data are stored in the sixth latch circuits 30 and 30 after the two clocks by the signals 'Wrt0' and 'Wrt0b', and the next two bits are stored by the next two clocks. The data is stored in the latch block, and the sixth latch circuits 30 and 30 at the last stage have four bits Bit by the control signals 'Wrt4' and 'Wrt4b', respectively. 30 ').

However, in the input data (Data) storage circuit of a conventional semiconductor memory device configured as described above, long data is stored by sequentially storing data received through the input pad PAD sequentially through a complicated data path through a latch circuit. It generates and uses paths and unnecessary internal control signals. This is because the first incoming data is input through a long data path, there is a problem that is exposed to the ambient noise.

Accordingly, the present invention was devised to solve the above problems, and an object thereof is to sequentially store the input data entered into the input pad PAD in the latch circuit of the last stage and output them all at once. The present invention provides an input data storage circuit of a semiconductor memory device in which a chip size is reduced and unnecessary signals are removed by reducing the flow of entire data.

1 is a block diagram illustrating a conventional method of storing input data entered into a pad in parallel using several latch circuits and sequentially storing the input data into a latch circuit at a final stage.

FIG. 2 is a block diagram of an input data storage circuit of a semiconductor memory device according to the present invention configured to sequentially store input data entered into a pad immediately in a latch circuit of a final stage and then output them all at once.

3 is a block diagram of a pulse shifter circuit used in the present invention

4 is a circuit diagram of a pulse shifter unit used in the present invention.

5 is an operation timing diagram according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10: receiving buffer circuit 12: clock signal input buffer circuit

14, 16: light control signal input buffer circuit

20 ~ 30: Latch circuit 40 ~ 46: Latch pin

50 to 56: last latch circuit 70: pulse shifter circuit

72 to 78: first to fourth pulse shifter portion

In order to achieve the above object, the input data (Data) storage circuit of the semiconductor memory device of the present invention, the receiving buffer circuit for buffering the serial data input from the input pad to output in parallel data, clock signal, pulse signal, reset The pulse shifter means and the pulse shifter means outputting a plurality of shifted pulse signals in response to each of the following clock signals when the reset signal has the first logic and the clock signal toggles as the input signal, respectively. And a plurality of latch means for storing the parallel data outputted from the reception buffer circuit when the pulse signal is input as the input and the pulse signal has the second logic.

Here, the first logic and the second logic are both "high" state. The pulse shifter means preferably includes as many shifter circuits as the number of latch means.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

FIG. 2 is a block diagram of an input data storage circuit of a semiconductor memory device according to the present invention configured to sequentially store input data entered into a pad immediately in a latch circuit of a final stage and then output them all at once.

Here, reference numeral 10 denotes a reception buffer circuit that receives and buffers serial data coming into the input pad PAD. Reference numerals 50 to 56 denote latch circuits of the final stage, and reference numeral 70 denotes a pulse shifter circuit implemented in the present invention. The pulse shifter circuit 70 receives a clock signal Clk, a pulse signal, and a reset signal as inputs, respectively, and when the clock signal is toggled, each shifted pulse signal Dat1 according to each clock signal. , Dat2, Dat3, and Dat4 are outputted to the latch circuits 50 to 56, respectively. At this time, the latch circuits 50 to 56 receive input data from the receiving buffer circuit 10 when the Dat1, Dat2, Dat3, and Dat4 signals, which are output signals of the pulse shifter circuit 70, are "1" (High). It will be accepted and stored.

3 is a block diagram of the pulse shifter circuit 70 used in the present invention, FIG. 4 is a circuit diagram of the pulse shifter parts 72 to 78 used in the pulse shifter circuit 70, and FIG. Operation timing diagram.

As shown, the pulse shifter circuit 70 includes first to fourth pulse shifter portions 72 to 78, and the first to fourth pulse shifter portions 72 to 78 are illustrated in FIG. 4. Each has a circuit configuration.

According to FIG. 4, the circuit of the pulse shifter unit is disposed between the first and second transfer gates TG1 and TG2 and the first and second transfer gates TG1 and TG2 that are operated in reverse by the clock signal Clk, respectively. Resets the node potential between two inverters G2 and G3 connected in parallel and serving as one unit cell, and between the first transfer gate TG1 and an input terminal of the inverters G2 and G3. NMOS switching element NM which bypasses to ground by a signal, and inverter G4 which inverts the output signal of the said 2nd transfer gate TG2, and sends it to the output terminal Out.

According to the above configuration, in the present invention, when the chip first receives data, the pulse shifter circuit 70 becomes “zero” by reset, and the clock is toggled. In this case, the pulse signal is shifted to each of the "Dat1", "Dat2", "Dat3" and "Dat4" nodes in accordance with each of the following clock signals.

When each of the "Dat" signals becomes "1", each of the final latch circuits 50 to 56 receives and stores data received through the reception buffer circuit 10. Eventually, when the parallel data is collected, the final data is delivered to the core at once.

As described above, according to the input data storage circuit of the semiconductor memory device according to the present invention, the input data stored in the input pad PAD is sequentially stored in the latch circuit of the last stage and then outputted at once. By reducing the flow of the entire data, it is possible to reduce the chip size and eliminate unnecessary signals.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and changes should be considered to belong to the following claims. something to do.

Claims (4)

A receiving buffer circuit for buffering serial data input from an input pad and outputting the parallel data; When the clock signal toggles with the clock signal, the pulse signal, and the reset signal as inputs, respectively, the pulse signal outputs a plurality of shifted pulse signals in accordance with the next clock signal. Pulse shifter means; And And a plurality of latch means for respectively inputting the pulse signals output from the pulse shifter means and storing parallel data output from the reception buffer circuit when the pulse signal has a second logic. Input data storage circuit of a semiconductor memory device. The method of claim 1, And the first logic and the second logic are both " high ". The method of claim 1, And said pulse shifter means comprises as many shifter circuits as said latch means. The method of claim 3, wherein The shifter circuit unit, First and second transfer gates operated in opposition to each other by the clock signal, two inverters connected in parallel to each other and acting as one unit cell between the first and second transfer gates, and the first transfer gate And an NMOS switching element which bypasses the node potential between the input terminal of the inverter to ground by a reset signal, and an inverter that inverts the output signal of the second transfer gate to an output terminal. Input data storage circuit.