JP2002260382A - Burst address counter for semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an access time and to perform high speed operation without requiring a new circuit. SOLUTION: This device has a 3 bits binary counter a1 to which initial addresses A0, A1, A2 are loaded by an initial address load signal 1d and which is operated synchronizing with clock signals (CK, /CK) composing of continuous pulse train, a 2 bit binary counter a2 which is initialized by a reset signal and operated synchronizing with clock signals (CK, /CK) composing of continuous pulse train, and a carry signal selecting circuit a3 selecting carry signals (crya0, crya1) being carry signals from the 3 bits binary counter a1 or carry signals (cryb0, cryb1) being carry signals from the 2 bits binary counter a2 by a burst mode switching signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst address counter for a semiconductor memory device, and more particularly to an interleave / sequential address generation for a synchronous semiconductor memory device operating in synchronization with a rising edge or a falling edge of a system clock signal. It relates to a counter circuit.

[0002]

2. Description of the Related Art In recent years, as the processing speed of microprocessors and the like has increased, the processing speed of semiconductor memory devices has also been required to increase. As a result, although the data write and read access methods are subject to some restrictions, the normal random access speed is increased, and the burst operation mode that operates in synchronization with a clock signal enabling high speed read is also provided. Semiconductor memory devices having the same have been developed.

[0003] The burst operation mode is a high-speed access mode in which a given data stream is continuously output in synchronization with a clock signal in an arbitrary clock synchronous semiconductor memory device. As a semiconductor memory device having a burst operation mode, there is a synchronous DRAM (hereinafter referred to as an SDRAM) and the like. The SDRAM includes a data string selecting means for outputting a specified data string in synchronization with the clock signal by an address signal generated by a burst counter in synchronization with the clock signal from an initial address signal captured by a control signal. ing.

In a semiconductor memory device having a burst operation mode, in order to increase a data transfer rate, a clock signal is operated at a higher speed, and a selected data train is switched at a higher speed, thereby increasing the data transfer rate. For this reason, it is essential to increase the switching speed of the data string selecting means.

In response to such a demand for increasing the switching speed of the data string selecting means, Japanese Patent Laid-Open Publication No.
Japanese Patent No. 1292 discloses a method of decoding a burst address generated by a burst counter in synchronization with a clock signal, generating a burst selection signal for selecting a data string, and switching the data string at high speed. .

FIG. 7 shows a burst selection signal generation circuit disclosed in Japanese Patent Application Laid-Open No. 11-191292. This burst selection signal circuit has two inputs, first to fourth.
Decoder circuits 51 to 54 and three input first
To fourth multiplexer (MUX) circuits 61 to 64;
It comprises first to fourth register (Reg) circuits 71 to 74. In the burst selection signal circuit,
Address signals A0 and A1 and respective inverted signals / A
0 and / A1 are internal address signals generated by inputting the lower two bits of the external address signal to an address buffer circuit (not shown), and input to the two-input decoder circuits 51 to 54, respectively. . CK is SD
This is an internal clock signal supplied from the outside of a memory chip such as a RAM, and is input to register (Reg) circuits 71 to 74, respectively.

Two-input first to fourth decoder circuits 51 to 51
54 have internal address signals (A0, A
1), (/ A0, A1), (A0, / A1), (/ A
0, / A1) is input.

[0008] Three-input first to fourth multiplexers (MU)
X) The circuits 61 to 64 include a first input terminal, a second input terminal,
Each of the first input terminals i1 of the first to fourth multiplexer (MUX) circuits 61 to 64 has a third input terminal, and the output signal of each of the decoder circuits 51 to 54 is input to the corresponding first input terminal i1. . Each multiplexer (MUX)
When the control signal S1 is input, the circuits 61 to 64 select and output any one of the input of the first input terminal i1, the input of the second input terminal i2, and the input of the third input terminal i3.

First to fourth register (Reg) circuits 71
Numerals 74 to 74 denote circuits for taking in input signals in synchronization with the input CK (clock signal). Each output signal of the first to fourth multiplexer (MUX) circuits 61 to 64 is synchronized with CK, 1st to 4th register (Reg) circuits 71 to
74 are respectively input.

Second to fourth register (Reg) circuits 72
The output signals of the first to third multiplexers (M to M) are output via the first loop wiring 81.
UX) input to the second input terminals i2 of the circuits 61 to 63,
The output signal of the first register (Reg) circuit 71 is input to the second input terminal i2 of the multiplexer (MUX) circuit 64. Each output signal of the first to third register (Reg) circuits 71 to 73 is supplied to the second loop-shaped wiring 82.
Via the third input terminal i of each of the adjacent second to fourth multiplexer (MUX) circuits 62 to 64
3 and the output signal of the fourth register (Reg) circuit 74 is input to the third input terminal i3 of the first multiplexer (MUX) circuit 64.

With such a circuit configuration, at the start of the operation of the burst address counter, the multiplexer (MU)
X) In the circuits 61 to 64, the decoder circuits 51 to 54
Select the first input terminal i1 to which the output signal of
A start address is preset in register (Reg) circuits 71-74.

Thereafter, a multiplexer (MUX) circuit 6
1 to 64, in the case of the sequential mode, select the signal of the second input terminal i2, shift the data in a loop by the first loop wiring 81, and register (Re)
g) A sequential mode burst selection signal is output from the circuits 71 to 74. In the case of the interleave mode, the first loop wiring 81 for selecting the signal of the second input terminal i2 according to the logical level of the lower address A0 in the address signals A1 and A0 at the start, or the third loop wiring
Second loop wiring 82 for selecting a signal of input terminal i3
To shift the data and register (Reg)
The circuits 71 to 74 output burst selection signals in the interleave mode, respectively.

In this method, since the decoding of the address signal and the switching of the interleave / sequential mode are performed by multiplexers (MUX) circuits 61 to 64 at the preceding stage of the register to which the clock signal is input, the rising edge of the clock signal is used. Alternatively, since the operation from the falling edge to the output of the burst selection signal is a delay caused only by the register Reg) circuits 71 to 74, a relatively high-speed operation becomes possible.

However, in the circuit configuration as described above, if the number of burst addresses for switching between interleave / sequential modes increases, a circuit is required for each burst selection signal after decoding the address signal. However, there is a problem that the circuit scale is increased by a factor of two for each additional line. Also, in the wiring space from the above-described circuit that generated the burst selection signal to the data string switching circuit that uses the selection signal,
There is also a problem that the selection signal after the address signal is decoded is increased by a factor of 2 in proportion to the circuit size for wiring.

Japanese Patent Application Laid-Open No. Hei 10-92173 discloses a proposal for speeding up a burst address counter circuit itself. FIG. 8 shows a configuration diagram of this burst address counter circuit.

The burst address counter circuit shown in FIG. 8 comprises a first binary counter 85, a second binary counter 86, a first burst code generator 87, and a second burst code generator. 88.
This circuit configuration is characterized in that the sequential address / interleave address is output by a single circuit group.

In the burst address counter circuit shown in FIG. 8, when a burst counter reset signal is input, the first and second burst code generators 87 and 88 are reset, respectively. Thereafter, when the burst type selection signal is selected and input, one of the sequential address / interleave address operation is selected. In this case, when the sequential address operation is selected, an operation for setting a second burst counter address is performed. When the starting address signal of the second burst counter address is HIGH, the clock signal is set to 1 as shown in the output waveform of FIG.
The second burst counter output is determined by inputting only the clock and counting up. Conversely, when the output of the starting address signal is LOW level, the input of the second binary counter unit 86 is output as it is as the second burst counter address.

Further, the burst type selection signal
When the interleave address operation is selected, the outputs of the first and second binary counter units 85 and 86 in FIG. 8 become the outputs of the first and second burst counter addresses as they are.

By such a circuit operation, each of the sequential address and the interleave address can be output by one circuit group, and the circuit scale can be reduced.

[0020]

However, in such a circuit configuration, when a starting address other than the lowest address is set, it is necessary to input a dummy clock for putting the system in a standby state, and two or more bits are required. When applied to a burst counter circuit, a dummy clock for putting many systems in a standby state is required. As a result, when used in a semiconductor memory device or the like, the initial access time may increase. There is also a problem that a comparison circuit between the initial address signal input to the device and the initial setting address signal of the counter set by the dummy clock for putting the system in a standby state is newly required.

An object of the present invention is to solve such a problem. It is an object of the present invention to reduce the access time and to reduce the access time and to use a sequential / interleaved access mode having a multi-bit configuration of 2 bits or more without a new circuit. The purpose of the present invention is to provide a burst address counter for a semiconductor memory device that performs the above operation at high speed.

[0022]

In the burst address counter for a semiconductor memory device according to the present invention, an initial address signal is loaded by an initial address load signal, and the first binary counter operates in synchronization with a clock signal composed of a continuous pulse train. A counter, a second binary counter which is initialized (reset) by an initial address load signal and operates in synchronization with a clock signal composed of a continuous pulse train, and a first binary signal which is a carry signal from the first binary counter. A carry signal selection circuit for selecting a carry signal and a second carry signal, which is a carry signal from the second binary counter, by a burst mode switching signal.

When the carry signal selection circuit selects the first carry signal, the operation in the sequential access mode is performed, and when the second carry signal is selected, the operation in the interleave access mode is performed.

The second binary counter is provided with the first binary counter.
Is loaded with the initial address signal by the initial address load signal, and at the same time, is initialized by the initial address load signal.

The carry signal selection circuit outputs the selected first or second carry signal to the first binary counter.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of a burst address counter for a semiconductor memory device according to an embodiment of the present invention.

In the burst address counter for a semiconductor memory device shown in FIG. 1, n initial load signals (n = 2, 3, 4) are loaded when an initial address load signal ld is input to a load (ld) terminal. ..) And an initial address load signal ld are input to the rst terminal (reset terminal), so that all counter outputs are LOW. An n-1 bit binary counter a2 composed of n-1 D-FFs resetting to a level, and carry signals crya0 to cryan-1 output from the cryout terminal of each bit of the n-bit binary counter a1.
(N = 2, 3, 4...) And carry signals cryb0 to crybn-1 (n = 2, 3) output from the cryout terminal of each bit of the n-1 bit binary counter a2.
3, 4...) Is selected by the burst mode switching signal, and the carry signal switching for connecting to the cryin input terminal of the D-FF with the initial address load function of the upper bit constituting the n-bit binary counter a1 And a circuit a3.

In the present embodiment, description will be made for a case where n = 3.

In the circuit constructed as the burst address counter for the semiconductor memory device shown in FIG. 1, first, an initial address signal A is output from a 3-bit binary counter a1.
0, A1, and A2 are input to the DIN terminals of the D-FFs 1 to 3 having the initial address load function, respectively, and the loads (l
d) Initial address signals A0, A1, and A2 are loaded based on the initial address load signal ld input to the terminal. At the same time, a 2-bit binary counter a
In 2, the D-FFs 6 and 7 with the reset function receive the initial address load signal ld at the reset (rst) terminal, and all the outputs of the counters are LO based on this signal.
It is reset to W level. After that, the burst counter output signals Ain0 to Ain2, which are the output signals from the D-FFs 1 to 3 having the initial address loading function of the 3-bit binary counter a1, are transferred to the carry signal switching circuit a.
3 is controlled based on the burst mode switching signal input to each of the carry signal switching circuits 4 and 5.

In this embodiment, when the burst mode switching signal is at the HIGH level, the sequential access mode is selected, and the burst mode switching signal is set to LOW.
In the case of the level, select the interleave access mode.

When the burst mode switching signal is at the HIGH level, the sequential address mode is selected for the burst address counter for the semiconductor memory device, and the carry signal switching circuits 4, 5 are provided with the initial address loading function of the 3-bit binary counter a1 having the initial address loading function. -FF1,2
Carry signal cry output from the cryout terminal of
a0 and crya1 are connected so as to be input to the cryin terminals of the D-FFs 2 and 3 with the initial address load function, which are upper bits. Next, the clock signal C is supplied to each of the D-FFs 1, 2, and 3 having the initial address load function.
K is input to a clock (CK) terminal, and a clock signal C
D- with initial address load function from the rise of K
After the operation delay time of the FFs 1, 2, and 3, the address signals sequentially incremented (carried up) from the initial address signals are burst counter output signals Ain0, Ain1, A
as in2, each with an initial address load function
-Output from the DOUT terminals of FF1, FF2 and FF3.

When the burst mode switching signal is at the LOW level, the interleave access mode is selected for the burst address counter for the semiconductor memory device, and the carry signal switching circuits 4 and 5 are each provided with a reset signal of the 2-bit binary counter a2 having a reset function. C of FF6,7
carry signal cryb0 output from ryout terminal
To cryb1 are D-FF2 with an initial address load function, which are upper bits of a 3-bit binary counter a1,
3 cryin terminal. Next, each of the D-FFs 1, 2, 3 with the initial address load function
The clock signal CK is input to the clock (CK) terminal, and after an operation delay time of each of the D-FFs 1, 2, and 3 with the initial address load function from the rise of the clock signal CK, an interleave address signal based on the initial address signal is burst. The counter output signals Ain0, Ain1,
Ain2 is output from the DOUT terminals of the D-FFs 1, 2, and 3 with the initial address load function, respectively.

FIG. 2 shows a D with an initial address load function constituting a 3-bit binary counter a1 provided in a burst address counter for a semiconductor memory device according to the present invention.
It is an internal circuit diagram of -FF1-3. The D-FFs 1 to 3 with the initial address load function have the same configuration.

D with initial address load function shown in FIG.
-FF1 to FF1 to 3 load the initial address signal input to the DIN terminal based on the initial address load signal input to the load (ld) terminal, and the carry signal of the lower bit is cryin. When input to the terminal, the counter circuit section 12 performs a counting operation based on the clock signal CK input to the clock (CK) terminal. An output latch circuit unit 13 that latches and outputs a burst counter output signal from a DOUT terminal, and a carry signal generation circuit unit 14 that outputs a carry signal from a cryout terminal to D-FFs 2 and 3 with an initial address load function of upper bits Have been.

The initial address load circuit section 11 receives an initial address load signal ld input to a load (ld) terminal.
And the inverter i
nv110 output signal and initial address load signal l
The clocked inverter ckinv111 is controlled by d and receives an initial address signal via a DIN terminal.

The counter circuit section 12 has a D-FF inverter with an initial address load function of the same bit as the carry signal of the lower bit input from the cryin terminal.
Exclusive NOR gate exnor to which a burst counter output signal which is an output signal of v131 is input
120 and exclusive NOR gate exnor1
The gate operation of the output signal 20 is set to H of the clock signal / CK.
Transfer gate tg for transferring data during the period of the IGH level (the period of the LOW level of clock signal CK)
121, an inverter inv122 to which an output signal from the transfer gate tg121 is input, and a feedback inverter inv123 having a low driving ability for feeding back the output signal of the inverter inv122 to the input side of the inv122.
And a transfer gate tg124 that transfers data during the HIGH level period of the clock signal CK (the LOW level period of the clock signal / CK) for the gate operation of the output signal of the inverter inv122.

The output latch circuit 13 is provided with an output signal of the transfer gate tg124 and the clocked inverter c.
an inverter inv131 to which a node φ130 in which the output signal of the kinv111 is wired-ORed is input;
The output signal of inverter inv131 is converted to inverter inv
It is constituted by a feedback inverter inv132 having a low driving ability for feeding back to the input side of 131.

The carry signal generation circuit 14 is provided with an inverter inv140 to which the carry signal of the lower bit is input.
And the carry signal of the lower bit is connected to the inverter inv14.
0, the carry signal inverted by 0, the output signal of the transfer gate tg124, and the clocked inverter ck.
A node φ130 obtained by wired-ORing the output signal of the inv111 and a NOR gate nor141 to which a node φ130 is input is provided.

FIG. 3 is an internal circuit diagram of the D-FFs 6 and 7 having a reset function constituting the 2-bit binary counter a2 provided in the burst address counter for a semiconductor memory device of the present invention. D-FF with reset function
6 and 7 have the same configuration.

The D-FF 6 with reset function shown in FIG.
Reference numeral 7 denotes a counter circuit 21 to which a carry signal of lower bits is input from the cryin terminal and performs a count operation based on clock signals (CK, / CK) input to a clock (terminal), and an output signal from the counter circuit 21. And an output latch circuit section 22 for latching and resetting an initial address load signal input from a reset terminal;
A carry signal generation circuit section 23 to which the carry signal of the lower bit and the output signal from the counter circuit 21 are inputted and the carry signal to the carry switching circuit a3 is outputted from the cryout terminal.

The counter circuit 21 is provided with a carry signal of the lower bit input from the cryin terminal and the inverter i.
an exclusive NOR gate exnor210 to which an output signal of the nv220 is input, and an exclusive N gate
The gate operation of the output signal of the OR gate exnor 210 is performed by inputting the transfer gate tg211 for transferring data during the HIGH level period of the clock signal / CK (the LOW level period of the clock signal CK) and the output signal from the transfer gate tg211. Inverter i
nv212 and the output signal of the inverter inv212 are i
The feedback inverter inv213 having a low driving ability to feed back to the input side of the nv212 and the gate operation of the output signal of the inverter inv212 are gated during the HIGH level period of the clock signal CK (the LOW level period of the clock signal / CK).
And a transfer gate tg214 that transfers data to the transfer gate.

The output latch circuit section 22 includes an inverter i to which an output signal of the transfer gate tg214 is input.
nv220 and an inverter inv221 for inverting the initial address load signal ld input from the rst terminal.
And the output signal of inverter inv220 and inverter i
A signal ldb obtained by inverting the initial address load signal ld by nv221 is input, and an NAND gate nand222 that feeds back an output signal based on the input signal to the input side of the inverter inv220.

The carry signal generation circuit 23 includes an inverter inv230 for inverting the carry signal of the lower bit.
And a NOR gate nor231 to which the carry signal inverted by the inverter inv230 and the output signal of the transfer gate tg214 are input.

FIG. 4 shows carry signal switching circuits 4 and 5 of carry signal switching circuit a3 provided in the burst address counter for a semiconductor memory device of the present invention.
FIG. 2 is an internal circuit diagram of a multiplexer circuit 10 used in each of the embodiments.

The multiplexer circuit 10 shown in FIG. 4 includes an inverter inv 310 to which a burst mode switching signal is input from an input terminal and an initial address load of lower bits input from an input terminal when the burst mode switching signal is HIGH. A clocked inverter ckinv312 that inverts the carry signal crya from the D-FF1 with function, and the carry signal cryb of the D-FF6 with reset function of the lower bit input from the input terminal when the burst mode switching signal is at the LOW level. Inverted clocked inverter ckin
v311 and an inverter inv313 to which a node φ310 obtained by wired-ORing the output signal of the clocked inverter ckinv312 and the output signal of the clocked inverter ckinv311 is input.

The operation of the thus configured burst address counter for a semiconductor memory device of the present invention will be described.

First, the operation based on the initial address load signal will be described. The load (ld) terminals of the initial address load circuit units 11 of the D-FFs 1 to 3 having the initial address load function shown in FIG. 2 and the D-FFs with the reset function shown in FIG.
Reset terminal rs of output latch circuit 22 of FFs 6 and 7
At t, an initial address load signal for loading the initial address signal when the signal is at the HIGH level is input. FIG.
Load (ld) of the initial address load circuit 11 shown in FIG.
When an initial address load signal is input to the terminal, the clocked inverter cquinv111 is enabled and DI
The signal levels of the initial addresses A0, A1, and A2 input from the N terminal are inverted, and the inverted output signal is transmitted to the node φ130 of the carry signal generation circuit unit 14. The output signal transmitted to the node φ130 is further inverted by the inverter inv131 of the output latch circuit unit 13, and the D-FF1, 2,
3, the signal levels of the initial addresses A0, A1, A2 are output as they are as the burst counter output signal, and the signal level of the burst counter output signal is
It is held by the feedback inverter inv132.

At the same time, the D- with reset function shown in FIG.
The high-level initial address load signal ld input to the reset terminal rst of the output latch circuit unit 22 of each of the FFs 6 and 7 is inverted (LOW level) by the inverter inv221, input to the NAND gate nand222, and Gate nand
222 is reset. And the NAND gate na
The nd 222 receives the output signal from the inverter inv 220 and outputs a HIGH-level output signal whose signal level is inverted by the NAND gate nd 222.
The signal level is inverted (LOW level) by the NOR gate nor 231, and the D-FF 6 with the reset function
7 is output as a LOW level carry signal from the cryout terminal.

Thus, the operation of the burst address counter for the semiconductor memory device based on the initial address load signal is completed. The cryin terminal of the D-FF1 with the initial address loading function of the lower bits of the 3-bit binary counter a1 and the D-FF6 with the reset function of the lower bits of the 2-bit binary counter a2 are connected to the cryin terminal during operation.
A HIGH level signal is input.

Next, the operation based on the burst mode switching signal will be described.

When the burst mode switching signal is at the HIGH level, the sequential address mode is selected. In this case, the burst mode switching signal is input to the inverter inv310, and the inverter inv3
Since the signal level is inverted from 10 and output at the LOW level, the clocked inverter cquinv 312 of the multiplexer circuit 10 of the carry signal switching circuits 4 and 5 shown in FIG. 4 is enabled (selected).
The cryo of the carry signal generation circuit 14 of the D-FF1 with the lower-order bit initial address load function shown in FIG.
Carry signal crya output from the ut terminal is input to clocked inverter cquinv312 from the input terminal of multiplexer circuit 10, and an inverted output signal is output from clocked inverter ckinv312 and transmitted to node φ310. Node φ3
The output signal transmitted to the inverter 10 is further inverted by the inverter inv 313 and output from the output terminal of the multiplexer circuit 10 as a carry signal cryc. Is input to the cryin terminal of the counter circuit section 12 of FIG.

Thereafter, the D-FFs 1, 2, and 3 with the initial address load function shown in FIG.
The following operation is performed by input of (CK).

First, when the carry signal input from the cryin terminal of the counter circuit section 12 is at a low level,
The signal level of the output signal of the inverter inv131 of the output latch circuit unit 13 is set to an exclusive NOR gate e.
xnor 120, the signal level is output without being inverted, and the output signal is transferred to the transfer gate tg.
It becomes 121 input signals. At this time, the clock signal CK is at the LOW level (the clock signal / CK is at the HIGH level).
Then, the transfer gate tg121 is in the data transfer state, and the exclusive NOR gate exnor
The output signal of the inverter 120 is transmitted to the inverter inv122. The output signal transmitted to the inverter inv122 is:
The signal output from the inverter inv122 is held by the feedback inverter inv123.

Further, when the clock signal CK is at the HIGH level (the clock signal / CK is at the LOW level), the transfer gate tg121 is in the data cutoff state,
The next transfer gate tg124 enters a data transfer state, and the inverter inv122 and the feedback inverter in
v123 and the signal data held at the node φ1
30 and further input to the inverter inv131 of the output latch circuit, the signal level of the node φ130 is inverted, and the D-FF1 with the initial address load function is provided.
3 are output as burst counter output signals from DOUT. The signal level of the output signal of the inverter inv131 and the exclusive NOR gate exnor1
The signal levels of the 20 output signals are the same.

Next, when the carry signal input from the cryin terminal of the counter circuit section 12 is at the HIGH level, the inverter inv of the output latch circuit 13 shown in FIG.
The output signal of 131 is an exclusive NOR gate e
The input signal is input to xnor 120 and inverted, and the inverted output signal becomes the input signal of transfer gate tg121.

At this time, when the clock signal CK is at the LOW level (the clock signal / CK is at the HIGH level), the transfer gate tg121 is in the data transfer state.
The output signal of the exclusive NOR gate exnor120 is transmitted to the inverter inv122. The output signal transmitted to the inverter inv122 is maintained at the signal level by the feedback inverter inv123.
Further, when the clock signal CK is at the HIGH level (the clock signal / CK is at the LOW level), the transfer gate tg121 enters the data cutoff state, the next transfer gate tg124 enters the data transfer state, and is held by the inverter inv122 and the feedback inverter inv123. The signal data transmitted to the node φ130 is input to the inverter inv131 of the output latch circuit 13, the signal level of the node φ130 is inverted, and the DOUs of the D-FFs 1, 2, and 3 with the initial address load function are provided.
It is output as a burst counter output signal from the T terminal.

At this time, the output level of the output signal of the inverter inv131 and the exclusive NOR gate exn
The signal levels of the output signals of or120 are mutually inverted levels. Also, the carry signal input to the cryin terminal is at a high level, and the inverter inv131
Is also at the HIGH level, the carry signal output from the cryout terminal is at the HIGH level.

By repeating the above operation, the 3-bit binary counter a1 shown in FIG. 2 can obtain an output in the sequential address mode using the initial address signal as the start address.

FIG. 5 shows a timing chart of each signal in the sequential address mode (burst mode switching signal: HIGH level) of the burst address counter of the present invention.

First, D with each initial address load function
-Initial address signals A0 (0), A1 (1) and A2 (0) input to the DIN terminals of FF1 to 3 are loaded (l
d) Loaded by a high-level initial address load signal input from the terminal. At this time, the burst address output signal (Ain2) is obtained by the circuit operation of the initial address load circuit section 11, the output latch circuit section 13, and the carry signal generation circuit section 14 shown in FIG. , Ain1, Ain0)
= (0, 1, 0) is output and cr is used as a carry signal.
ya0: LOW level and crya1: LOW level are output.

Thereafter, the initial address load signal becomes LOW.
When the clock signal (CK, / CK) becomes a level and is input to the counter circuit unit 12 of each of the D-FFs 1, 2, and 3 with the initial address load function, the transfer gate tg1
21 and the transfer gate tg124 operate,
Carry carry signals crya0 and crya1 are H
By switching to the IGH level and the LOW level, the burst address output signal becomes (Ain2, Ain2).
1, Ain0) = (010) → (011) → (100)
→ (101) → (110) ...
The address data that is sequentially carried is output.

Next, when the burst mode switching signal is
In the case of the W level, the interleave address mode is selected. In this case, the burst mode switching signal is input to the inverter inv 310 and the inverter i
Since the signal level is inverted and output at HIGH level from nv310, clocked inverter ckinv311 of multiplexer circuit 10 of carry signal switching circuits 4 and 5 shown in FIG. 4 is enabled (selected),
The carry signal cryb output from the cryout terminal of the D-FF 6 with the reset function of the lower bits shown in FIG.
Is input to the clocked inverter cquinv311 from an input terminal of the circuit of the multiplexer, and an output signal whose signal level is inverted is output from the clocked inverter cquinv311 and transmitted to the node φ310. The output signal transmitted to node φ310 is further inverted in signal level by inverter inv313, and carry signal cr is output from the output terminal of multiplexer circuit 10.
It is output as yc and input to the respective cryin terminals of the D-FFs 2 and 3 with the initial address load function shown in FIG.

Further, D- with reset function shown in FIG.
The FFs 6 and 7 perform the following operations in response to the input of the clock signal CK.

First, when the carry signal input from the cryin terminal of the counter circuit section 21 is at a low level,
The inverter inv2 of the output latch circuit unit 22 shown in FIG.
20 output signal is an exclusive NOR gate ex
nor210, the signal level is output without being inverted, and the output signal is transferred to transfer gate tg.
211 is input.

At this time, when the clock signal CK is at the LOW level (the clock signal / CK is at the HIGH level), the transfer gate tg211 is in the data transfer state,
The output signal of the exclusive NOR gate exnor210 is transmitted to the inverter inv212. The output signal transmitted to inverter inv212 is
v212 and output from the feedback inverter inv213
Holds the signal level.

Further, when clock signal CK is HIGH (clock signal / CK is LOW), transfer gate tg210 is in a data cutoff state,
The next transfer gate tg214 enters the data transfer state and the inverter inv212 and the feedback inverter inv
213 is input to the inverter inv220 of the output latch circuit 22, and the signal level of the output signal of the inverter inv212 is inverted, and this output signal is output to the NAND gates nand222 and N.
Through OR gate NOR231, D- with reset function
It is output as a carry signal from the cryout terminals of the FFs 6 and 7. At this time, the signal level of the output signal of the inverter inv220 and the exclusive NOR gate ex
The signal level of the output signal of the nor 210 is the same level.

Next, when the carry signal input from the cryin terminal of the counter circuit 21 is at the HIGH level, the inverter inv22 of the output latch circuit 22 shown in FIG.
0 is output to an exclusive NOR gate exn.
or210 is input and inverted, and the inverted output signal is input to the transfer gate tg211.

At this time, when the clock signal CK is at the LOW level (the clock signal / CK is at the HIGH level), the transfer gate tg211 is in the data transfer state,
The output signal of the exclusive NOR gate exnor210 is transmitted to the inverter inv212. The output signal transmitted to inverter inv212 is
v212 and output from the feedback inverter inv213
Holds the signal level.

Further, when the clock signal CK is at the HIGH level (the clock signal / CK is at the LOW level), the transfer gate tg211 is in the data cutoff state,
The next transfer gate tg214 enters the data transfer state, and the inverter inv212 and the feedback inverter in
v213 is input to the inverter inv220 of the output latch circuit 22, and the signal level of the output signal of the inverter inv212 is inverted.
This signal is applied to NAND gate nand222 and NO
Through R gate NOR231, DF with reset function
It is output as a carry signal from the cryout terminals of F6 and F7. At this time, the signal level of the output signal of the inverter inv220 and the exclusive NOR gate exn
The signal levels of the output signals of or210 are inverted levels from each other. Also, the carry signal input to the cryin terminal is at a high level, and the inverter inv22
If the output level of 0 is HIGH, cryout
The carry signal output from the terminal becomes HIGH level.

By repeating the above operation, the 2-bit binary counter a2 shown in FIG.
After the initial address load signal is input and reset, the FFs 6 and 7 sequentially increment the address signal and output addresses sequentially, and at the same time, sequentially use the initial address signal A0 = (0) as a start address. Carry signal c according to address
ryb is output. The 3-bit binary counter a1 shown in FIG. 2 receiving the carry signal cryb can obtain an output in an interleave address mode using the initial address as a start address.

In the interleave access mode (burst switching signal: L
FIG. 6 shows a timing chart of each signal in the case of (OW level).

Until the clock signals (CK, / CK) are input to the clock terminals (CK) of the 3-bit binary counter a1 and the 2-bit binary counter a2, the burst address output signal is the same as the operation in the sequential access mode. (Ain2, Ain1, Ain
0) = (0, 1, 0) is output, and crya0: LOW level and crya1: LOW level are output as carry signals.

Thereafter, the initial address load signal becomes LOW.
Level, and the clock signals (CK, / CK) are supplied to the counter circuit unit 12 of each of the D-FFs 1, 2, and 3 with the initial address load function and the D-FFs 6 and 7 with the reset function.
, The transfer gates tg121 and tg124 of the counter circuit unit 12, and the transfer gates tg211 and tg2 of the counter circuit unit 21 are input.
214 operates and the carry signals cryb0 and cryb1 of the carry are switched to the HIGH level and the LOW level, whereby the burst address output signal becomes (Ai).
n2, Ain1, Ain0) = (010) → (011)
→ (000) → (001) → (110)..., And the address data in the interleave access mode is output.

As described above, in the burst address counter for semiconductor memory device of the present invention, the delay time from the input of the clock signal (CK) to the output of the burst counter output signal is different between the sequential access mode and the interleave access mode. In either operation, only the operation time of the 3-bit binary counter a1 and the 2-bit binary counter a2 is required, and the access can be speeded up without adding a new circuit.

[0076]

According to the burst address counter for a semiconductor memory device of the present invention, a first binary counter loaded with an initial address by an initial address load signal and operating in synchronization with a clock signal composed of a continuous pulse train, and a reset signal , A second binary counter operating in synchronization with a clock signal composed of a continuous pulse train, a first carry signal as a carry signal from the first binary counter, and a second binary counter. And a carry signal selection circuit for selecting a second carry signal, which is a carry signal of the above, by a burst mode switching signal, thereby shortening the access time and reducing the number of bits of two bits or more without requiring a new circuit. Multi-bit sequential / interleave access mode operation at high speed It can be carried out.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a burst address counter for a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is an internal circuit diagram of a 3-bit binary counter provided in a burst address counter for a semiconductor memory device of the present invention.

FIG. 3 is an internal circuit diagram of a 2-bit binary counter provided in a burst address counter for a semiconductor memory device of the present invention.

FIG. 4 is an internal circuit diagram of a carry signal switching circuit provided in a burst address counter for a semiconductor memory device of the present invention.

FIG. 5 is a timing chart of each signal when a sequential address of a burst address counter of the present invention is selected.

FIG. 6 is a timing chart of each signal when an interleave address of the burst address counter of the present invention is selected.

FIG. 7 shows a conventional burst selection signal generation circuit.

FIG. 8 is a configuration diagram of a conventional burst address counter circuit.

9 is a timing chart of the signal output waveform of FIG.

[Explanation of symbols]

 Reference Signs List 1 D-FF with initial address load function 2 D-FF with initial address load function 3 D-FF with initial address load function 4 Carry switching circuit 5 Carry switching circuit 6 D-FF with reset function 7 D-FF with reset function 10 Multiplexer circuit 11 Initial address load circuit section 12 Counter circuit section 13 Output latch circuit section 14 Carry signal generation circuit section 21 Counter circuit section 22 Output latch circuit section 23 Carry signal generation circuit section 51 First decoder circuit 52 Second decoder circuit 53 3 decoder circuit 54 4th decoder circuit 61 1st multiplexer (MUX) circuit 62 2nd multiplexer (MUX) circuit 63 3rd multiplexer (MUX) circuit 64 4th multiplexer (MUX) circuit 71 1st register (Reg) times 72 second register (Reg) circuit 73 third register (Reg) circuit 74 fourth register (Reg) circuit 81 first loop-shaped wiring 82 second loop-shaped wiring 85 first binary counter unit 86 second Binary counter unit 87 First burst code generation unit 88 Second burst code generation unit a1 3-bit binary counter a2 2-bit binary counter a3 Carry switching circuit

Claims (4)

[Claims] 1. An initial address signal is loaded by an initial address load signal, a first binary counter which operates in synchronization with a clock signal composed of a continuous pulse train, and is initialized (reset) by an initial address load signal. A second binary counter that operates in synchronization with a clock signal composed of a pulse train, a first carry signal that is a carry signal from the first binary counter, and a carry signal from the second binary counter. A carry signal selection circuit for selecting a second carry signal with a burst mode switching signal, the burst address counter for a semiconductor memory device. 2. The method according to claim 1, wherein the carry signal selection circuit is provided with the first signal.
2. The burst address counter for a semiconductor memory device according to claim 1, wherein the operation of the sequential access mode is performed when the carry signal is selected, and the operation of the interleave access mode is performed when the second carry signal is selected. 3. The second binary counter according to claim 1, wherein the first binary counter is initialized by an initial address load signal at the same time that the first binary counter is loaded with an initial address signal by an initial address load signal. Burst address counter for semiconductor memory device. 4. The burst address counter according to claim 1, wherein the carry signal selection circuit outputs the selected first or second carry signal to the first binary counter.