KR100329944B1 - Main memory system with multiple data paths - Google Patents

Abstract

A system with a microprocessor is provided with a first burst access memory subsystem tightly coupled to the microprocessor data bus for optimum performance, and a data buffer to provide micro memory with high memory capacity without overloading the microprocessor bus. It has a main memory divided into a second combined memory subsystem. The second memory subsystem can be burst access or page mode memory. Part of the second memory subsystem acts as a video frame buffer.

Description

MAIN MEMORY SYSTEM WITH MULTIPLE DATA PATHS

The present invention relates to a microprocessor system architecture. In particular, it relates to memory subsystem architecture, memory-to-microprocessor interface design, computer motherboard design, and processor daughterboard design.

As personal computers become more high-performance, memory devices of low cost and high speed and high density, such as standard DRAM, are required. Today, fast page mode DRAM is the most widely used standard DRAM. In fast page mode operation, the row address portion of the multiplexed DRAM address is latched using a row address strobe (/ RAS). While / RAS is active, several column address strobes (/ CAS) each latch a column address to random access the data in the selected row. At the falling edge of / CAS, the address is latched and the DRAM output is enabled. When / CAS transitions to a high state, the DRAM output is in a high impedance state (tri-state). Advances in integrated circuit fabrication technology have made the operation of DRAM internal circuits faster. This high speed circuit allows for a faster page mode cycle time. When the memory device operates with a minimum of fast page mode cycle times, there is a problem in reading the DRAM. Although / CAS can be low at most 15ns at most, the data access time from / CAS to valid output data (tCAC) can be up to 15ns, so in the worst case output data can be There is no time to latch. Even if the memory device runs faster than the required specification, the data may be valid only a few ns. If the microprocessor memory bus is overloaded, it is very difficult to latch an asynchronous signal that is only valid for a few ns. Providing a new address every 35ns also requires a large number of address drivers, creating a significant amount of electrical noise in the system. In order to improve the data throughput of memory systems, it is common to place a plurality of memory devices on a common bus and interleaving them. For example, two high speed page mode DRAMs may be connected to a common address and data bus. One DRAM stores data of odd addresses, and another DRAM stores data of even addresses. The disadvantage of this method is that additional memory cycle time is needed to turn off one memory device and then turn on another. In addition, to achieve a specific data bandwidth, it is necessary to minimize the number of memory devices to be interleaved if the required memory capacity can be satisfied with fewer memory devices.

In today's personal computer systems, there is a need for faster, higher density random access memory integrated circuits. To meet these demands, numerous methods have been proposed as alternatives to the standard DRAM architecture. One such method is Extended Data Out (EDO) mode, which allows longer periods of data remain valid at the DRAM output without increasing the fast page mode cycle time. In an EDO DRAM, the data line is not in a tri-state between read cycles during a fast page mode operation. Instead, the data remains valid until after / CAS goes high until some time after the next low-state pulse of / CAS is generated, or until / RAS or the output enable (/ OE) goes high. Is retained. Determining when valid data arrives at the fast page mode or the output of an EDO DRAM depends on when the column address input is valid, when / CAS goes down, the status of / OE, and when / CAS goes up in the previous cycle. It can be a complex function, for example. The period of time that the data is valid for control line signals (especially / CAS) will depend on the particular implementation of the EDO mode adopted by various DRAM manufacturers. EDO DRAM allows memory to operate at higher speeds by lengthening the window in which data output is valid during page mode operation, but this feature results in little compatibility with the interleaved memory architecture described above. For EDO memory, see CP000445400 Bargery C .: Hyper Page Mode DRAM, published September 1, 1994, Electronic Engineering, Vol. 66, No. 813, pages 47-48. Please.

In methods that further shorten memory access cycles, additional circuitry, additional control pins, and nonstandard device pinouts tend to be needed. For example, the proposed industry standard synchronous DRAM (SDRAM) additionally has a pin for receiving system clock signals. Since the system clock is connected to each device in the memory system, it is very expensive and always toggles the circuitry in every device. The SDRAM also has a clock enable pin, a chip select pin, and a data mask pin. Signals with names similar to those in standard DRAM have very different functions in SDRAM. Adding a few control pins makes the device's pinout different from standard DRAM, making the design effort to use these new devices more difficult. In SDRAM devices, quite a lot of additional circuitry is required, resulting in higher device manufacturing costs.

In order for existing computer systems to use advanced devices with non-standard pinouts, they must be extensively modified. In addition, in the design of existing computer system memory architectures, the control and address signals cannot be switched at the frequencies required to operate the new memory device at high speed because of the large capacitive load of the signal lines. Single in-line memory modules (SIMMs) are a type of industry standard for memory packaging in computer systems. In the SIMM, all address lines are connected to the DRAM. In addition, the row address strobe (/ RAS) and the write enable (/ WE) may be connected to each DRAM of the SIMM. Inherently, these lines have a large capacitive load because of the high input of the device they drive. Because SIMM devices usually leave the output enable (/ OE) pins grounded, / OE is not very attractive as a candidate for memory device expansion.

Because of the enormous number of computers that use SIMMs, they differ from standard SIMM designs and encounter a lot of resistance. The widespread adoption of these devices has been delayed by the industry's resistance to radically breaking standards and the inability of current systems to accommodate new memory devices. Thus, devices with very different architectures are initially manufactured in limited quantities. As such, the limited production quantity makes it difficult to reduce the cost that can be achieved through productivity improvement and efficiency increase due to mass production.

In typical microprocessor system configurations found in personal computers or workstations, the microprocessor is coupled to a memory controller and high speed static random access memory (SRAM). The large main memory is connected to the microprocessor bus through a memory controller, an address buffer, and a data buffer. The main memory is usually DRAM, which is a high-density data storage device having relatively wide data bandwidth and capable of random access. The data buffer may be a transceiver, a register, a registered transceiver, a latch, or the like. By performing the necessary isolation by these buffers, the load on the microprocessor local bus can be limited to be handled by the microprocessor signal driver.

See US Pat. No. 5,249,277 for such a conventional system.

With the advent of multimedia devices and software applications, a large number of peripheral devices have become widely available. Depending on the purpose of such an application, an external device or an internal add in circuit board, which communicates with a host system, may be a peripheral device, but is not limited thereto. These devices are also indirectly connected to the microprocessor or main memory. Such peripheral devices include mass data storage devices such as CD ROMs and magnetic hard drives; Floppy disk drive; Input and output ports for keyboard and mouse devices; Sound card; Fax and modem devices; Display devices and other devices. Due to signal drive limitations, it is not possible to connect all of these peripheral subsystems directly to each other. Unfortunately, buffering, multiplexing, and the separation of microprocessors and subsystems can introduce delays and degrade system performance.

To maximize performance, the system resources that the microprocessor needs most often should be resources that the microprocessor can access with minimal time delay. The main factor in system performance is the bandwidth of the microprocessor-memory interface. Because of this, the memory subsystem is designed for high-speed access, but the interface or peripherals may be a Peripheral Component Interconnect (PCI) bus, a Video Electronics Standards Association (VESA) local bus, or an ISA bus (Industry Standard). It can be accessed through system buses such as Architecture.

The microprocessor executes system tasks with instructions and data. Instructions and data are stored in main memory, usually DRAM. By storing the instructions and data that the microprocessor uses most often in an internal or external SRAM cache, you can significantly improve system performance. Using cache memory provides fast access to the data, but the data in the cache is a copy of the data in main memory and does not increase the memory capacity of the system. Fast SRAMs are unfortunately one of the most expensive memory devices at any memory density. Due to the high cost and limited device density, high speed SRAMs are not used in most main memory applications. Even with a relatively small amount of cache memory, the performance of conventional systems can be significantly improved by increasing the probability that the information required by the processor is in the cache. However, the increase in the 'hit rate' of cache memory tends to become smaller long before the cache capacity approaches the main memory capacity, so using large amounts of SRAM cache is not economical. Although DRAM provides a more economical main memory solution, it still requires a significant number of DRAM chips for optimal system performance. This in turn means that these chips must be buffered from the microprocessor bus. This buffering, along with the initial access time of DRAM, which is relatively slow compared to SRAM, limits system performance.

There is a need for new system designs that increase bandwidth between microprocessor-main memory, eliminate the need for SRAM caches in mid to high performance systems, and improve performance in systems that use SRAM caches. Improving main memory access time and bandwidth results in improved performance of conventional system architectures. However, whether current system architectures can utilize memory devices with these wider bandwidths is limited by signal loading, buffer delays, and asynchronous timing of memory-microprocessors. In addition, there is a need to increase the bandwidth between the system elements and the memory other than the microprocessor.

Integrated circuit memory devices with standard DRAM pinouts are designed to enable high speed data access and maintain compatibility with existing memory systems. A fast burst mode operation is provided in which multiple accesses occur sequentially after one column address, and the read data is output in accordance with the / CAS control signal. In this burst mode of operation, the address is incremented internally within the device, eliminating the need to switch external address lines to high frequencies. The read / write command is issued only once for each burst access, eliminating the need to toggle the read / write control lines at high speed. To clock the internal address counter and the data input / output latch, only one control line (/ CAS) can be toggled to the operating frequency for each memory chip. Since each / CAS generally only needs to control a data bus that is one byte wide, the load on each / CAS is less than the load on other control signals (/ RAS, / WE, and / OE). The internal circuitry of the memory device is largely compatible with existing extended data out (EDO) DRAM. This similarity allows the addition of only a small amount of other circuitry to produce two types of components on one die. The ability to switch between standard non-burst mode and high speed burst mode makes it possible to use this device as a replacement for a standard device, eliminating the need to switch to more complex high speed memory devices. By creating internal addresses, data access times are faster than is possible with fast page mode or EDO DRAM. Since the operation of the burst EDO device is performed at high speed, there is no need to interleave the memory device in order to increase data processing capability. When a standard DRAM device operates at 30 MHz, the data validity period is only a few nanoseconds (ns), while the burst EDO device has a data validity period of 5 nanoseconds even when operating at 100 MHz. The device is also compatible with existing memory module pinouts. The memory modules include, but are not limited to, a single inline memory module (SIMM), a multi-chip module (MMC), a dual in-line memory module (DIMM), and the like. By combining these features, it is possible to significantly improve system performance with minimal design changes.

In one embodiment of the invention, this new system architecture has a main memory that is divided into two main memory subsystems. The first portion of main memory consists of burst access DRAMs tightly coupled to the microprocessor data bus for optimal performance, and the second portion of main memory is connected to the microprocessor data bus through a data buffer. Loosely coupled. The tightly coupled portion provides the processor with a wide bandwidth and high density data and information storage that can be synchronized with the processor clock. The second portion provides additional memory capacity, but processor bus loading does not increase proportionally. In a preferred embodiment, both of these subsystems are removable to facilitate capacity / performance upgrades of the memory subsystem. In another preferred embodiment, only the loosely coupled system is removable, and the tightly coupled system is mounted directly on the computer motherboard to provide controlled signal propagation characteristics to maximize performance. .

The second portion also allows for wider access bandwidth between peripherals and subsystems and memory. Some of the second portions may be used as display buffers for refreshing display information, which requires very wide bandwidth data access. In the preferred embodiment, the display buffer accesses the tightly coupled system, while the microprocessor accesses the tightly coupled system. In this embodiment, there is almost no problem of performance penality with respect to the position of the display frame buffer in the main memory. By using main memory as the display buffer, there is no additional cost associated with a separate display buffer. In particular, the use of video RAM can significantly increase the cost of a computer system. Another advantage of the main memory display buffer is that it can provide multiple display resolutions, where the memory not used for display is made available to the system as additional main memory.

Frequently required information should be stored in the first main memory portion so that the microprocessor can access it quickly. In the case of a system using an SRAM cache, the microprocessor can obtain information from this cache very frequently. If it is a cache miss, the information may be available in tightly coupled parts of main memory. Since the ratio of time required for requesting information to the second part of the main memory is small, the overall system performance is not significantly affected by the performance degradation due to the uncoupling characteristic of the second part in most applications.

In a graphical user interface (GUI) environment, there are cases where multiple applications are open at the same time (the user launches the application). In some cases, one application may run in the background while another application may run in the background. If each application is running, more main memory is required. In a preferred embodiment of the present invention, the tightly coupled main memory is allocated to the lowest address space of the main memory, and the uncombined memory is allocated to the upper address space. For example, in a system with 144 megabytes of memory, the first 16 megabytes of the main memory address space are for tightly coupled main memory, and the remaining 128 megabytes are for small combined main memory at higher address values. will be. When the operating system allocates memory, it uses the lower address memory first. If a user is running only a few applications, both application code and data can be stored in tightly coupled memory, so system performance is optimized in terms of speed. When a user runs many applications, some application code may end up and then be placed in the uncoupled main memory. If the microprocessor has access to the uncoupled main memory, the system will exhibit poor performance. However, in some cases the flexibility to run many applications simultaneously is more important than the need to run at maximum computation speed. This system provides the flexibility of a large memory computer system, while its speed can be achieved through the use of limited tightly coupled main memory.

In this system, various types of memory can coexist in the system. For example, the first tightly coupled portion of the memory may be a burst EDO memory, and the second smallly coupled portion may be an EDO memory. Program the memory controller to access the first portion of the burst EDO format at a first access rate and access the second portion of the EDO format at a second access rate. By doing so, the user can have a large amount of memory, and at the same time, at least part of the memory can be accessed at a high speed. The second portion of main memory may be subdivided into multiple memory banks. The first bank of the second part may be an EDO memory, and may be used as the primary additional memory capacity for information that is not suitable for the first tightly coupled part. The second bank of the second part may be used as a display frame buffer having sufficient bandwidth to support high resolution information display, in addition to providing additional system memory capacity as a burst EDO memory. SDRAM or other burst access memory devices may also be used as the first memory portion.

At power up or reset, the system can determine the type and amount of memory present in each memory bank and adjust the memory access signal timing parameters accordingly. Otherwise, the user may need to fill a particular memory bank with a particular type of memory. If a particular bank of memory can be one of several types of memory, the user can control system price / performance characteristics by selecting the most economical and highest performing memory subsystem for his computer use.

1 is an electrical schematic configuration diagram of a burst EDO memory device.

2 is a contrast table of linear addressing formats and interleaved addressing formats.

3 is a preferred pinout view of the device of FIG.

4 is a timing diagram of an access method of the apparatus of FIG.

5 is another timing diagram of an access of the apparatus of FIG.

6 is an electrical schematic configuration diagram of a single in-line memory module.

7 is a front view of another memory module using the device of FIG.

8 is a preferred pinout diagram of the memory module of FIG.

9 is a schematic representation of a system designed in accordance with the present invention.

10 is a schematic representation of another embodiment of a system designed in accordance with the present invention.

11 is a timing diagram of a method for determining the type of memory present in the system.

<Explanation of symbols for main parts of the drawings>

112: microprocessor

114: local bus

116: address and control signal

118: data signal

120: timing and control circuit

136: data transceiver

FIG. 1 shows a 16 megabit burst access extended data out dynamic random access memory (BEDO DRAM). This memory device is composed of eight 2-megabit BEDO DRAMs having an 8-bit data input / output path 10 to provide a data storage device for 2,097,152 bytes of information in the memory array 12. In a preferred embodiment, the device of FIG. 1 has an industry standard pinout for an 8-bit wide EDO DRAM. A row-active row address strobe (/ RAS) signal 14 is used to latch the first portion of the multiplexed memory address from address input 16 to latch 18. The latched row address 20 is decoded in the row decoder 22. One row of the memory array 12 is selected using the decoded row address. The second portion of the memory address from the address input 16 is latched in the column address counter 26 using the column address strobe (/ CAS) signal 24. The latched column address 28 is decoded in the column address decoder 30. One column of the memory array 12 is selected using the decoded column address.

In a burst read cycle, data in the memory array located at the row and column address selected by the row and column address decoder is read from the memory array and sent to the output latch 34 along the data path 32. Data 10 driven from a burst EDO DRAM is latched outside of this memory device in synchronization with / CAS after a predetermined number of / CAS cycle delays (latency). If you design a wait time of two cycles, use the first / CAS falling edge to latch the initial address for burst access. The first burst data from this memory is driven from memory after the second / CAS falling edge and remains valid until the third / CAS falling edge. Once the memory device starts to output data in a burst read cycle, the output driver 34 will turn off the output enable 42 and write enable 36 (/ OE and / WE) control lines during the period when / CAS is high. Depending on the state, the data line continues to be driven without making the data output tri-state, thus allowing the system to gain additional time to latch the output data. Once the row and column addresses are selected, the additional shifting of the / CAS signal is used to increment the column addresses in the column address counter in a predetermined order. As long as / OE remains low and / WE is high, the time that data is valid at the output of the burst EDO DRAM depends only on the timing of the / CAS signal. The output data signal level may be driven according to standard CMOS, TTL, LVTTL, GTL, or HSTL output level specifications, but is not limited thereto.

Addresses can be incrementally linearly or interleaved to best suit the overall system requirements. FIG. 2 is a diagram illustrating an addressing sequence of linear and interleaved schemes when burst lengths are 2, 4, and 8 cycles. In the diagram, the 'V' of the start addresses A1 and A2 represent address values that do not change throughout the burst sequence. In the case where one or more data words are read out of the array with each column address, the column address may be incremented for each / CAS transition, for each pulse, or for multiple / CAS pulses. When the address is incremented for each transition of the / CAS signal, data is also driven from that portion after each transition following the wait time of the memory device, which is referenced for each edge of the / CAS signal. This enables a burst access cycle in which the highest switching control line (/ CAS) is toggled (high to low, or low to high) only once during each memory cycle. This is either standard DRAM where / CAS must go low during each cycle and then high, or synchronous (which requires a full clock cycle (high state transition and low state transition) during each memory cycle). In contrast to synchronous DRAM. To maximize compatibility with existing EDO DRAM devices, the present invention will be further described with reference to devices designed to latch and increment column addresses at the falling edge of the / CAS signal.

In order to apply this latch and incremented address to the array early in the access cycle, it is desirable to latch and increment the column address after the first / CAS falling edge. For example, the device may be designed to access two data words per cycle (prefetch architecture). The memory array for the prefetch architecture device may be divided into odd and even arrays. The least significant bit of the column address is then used to select either the odd or even side, and the remaining column address bits select one column from each of the bisected arrays. In the interleaved access mode, when the column address is 1, the data of the columns 0 and 1 are read, the data of the columns 0 is output, and then the data of the columns 1 is output according to the standard interleaving addressing as described in the SDRAM specification. . In the linear access mode, column address 1 is applied to the odd-numbered array and then incremented to address 2 and the even-numbered array is accessed for two word access. One way to implement this kind of device architecture is to install a column address increment circuit between the column address counter and the even-side array. Incremental circuits increment a column address only if the initial value of the column address in the burst access cycle is odd and the address mode is linear. Otherwise, the incremental circuit passes the column address unchanged. In a design using prefetch with two data accesses per cycle, the column address is incremented once every two active edges of the / CAS signal. A prefetch architecture is also possible that accesses two or more data words.

Another memory architecture that can be applied to the present invention is a pipeline architecture in which memory accesses are performed sequentially, but require more than one cycle to complete each access. In pipeline architectures, the total throughput of the memory reaches one access per cycle, but the data output from the memory is dependent on the pipeline length and / or the desired latency from / CAS. It may be offset by the number of cycles that result.

In a burst access memory device, each new column address from the column address counter is decoded and used to access additional data in the memory array, but there is no need to assign an additional column address to the address input 16. . This burst sequence of data continues for each / CAS falling edge until a predetermined number of data accesses, such as burst length, are made. At the received / CAS falling edge after the last burst address has occurred, another column address is latched from the address input 16 and a new burst sequence is started. Read data is latched and output at each falling edge of / CAS after the first / CAS wait time.

During a burst write cycle, data 10 is latched in input data latch 34. Data sent to the first address determined by the row address and column address are latched by the / CAS signal when the first column address is latched (when the write cycle data wait time is zero). Other write cycle data latency values are possible, but 0 is desirable in today's memory systems. Additional input data words to be stored at incremented column address positions are latched by / CAS in successive / CAS pulses. Input data from the input latch 34 is transferred to the memory array along the data path 32 and stored at a location selected by the row and column address decoder. As in the burst read cycle described above, a predetermined number of burst access writes are made without providing additional column addresses to the address line 16. After a predetermined number of burst writes, the next / CAS pulse latches the new start column address and starts another burst read or write access.

The memory device of FIG. 1 may include an operation mode switching option between a burst EDO and a standard EDO. In this case, use the write enable signal (/ WE) 36 at the row address latch time (/ RAS down, / CAS high state) to determine whether the memory access to that row is a burst mode cycle or a page mode cycle. Will be decided. If / WE is low when / RAS descends, the burst access cycle is selected. If / WE is high when / RAS descends, the standard Extended Data Out (EDO) page mode cycle is selected. Using either a burst mode cycle or an EDO page mode cycle, there is no need to put the data line 10 high impedance in the interval between data read cycles while / RAS is low for the data output driver 34. Therefore, the operating frequency of the memory device can be increased. In addition to serving as a standard DRAM control, the DRAM control circuit 38 controls the I / O circuit 34 and the column address counter / latch 26 according to the mode selected by / WE when / RAS is lowered. do. In burst-only DRAM or devices designed differently between burst access cycles and non-burst access cycles, switching between interleaved addressing mode and linear addressing mode using the / WE state when / RAS is down. Switching between different possible operation modes. Alternatively, when the / WE state at the time of / RAS descending is not used to select an operation mode, / WE may be 'don't care'.

In a burst access cycle, when the column address initial value of the burst cycle is latched by / CAS, a write enable signal is used to select read or write burst access. If / WE is low at the time of column address latching, burst write access is selected. If / WE is high at the time of column address latching, burst read access is selected. The level of the / WE signal must remain high throughout its burst access during reads and low during write burst access. If there is a transition from the low state to the high state during the burst write access, the burst access ends and no further recording is performed. If / WE transitions from a high state to a low state during a burst read access, the burst read access is likewise terminated and the data output 10 is placed in a high impedance state. The transition of the / WE signal is locked out during the critical timing period of the access cycle to reduce the likelihood of triggering a false write cycle. After the threshold timing period, the status of / WE determines whether burst access is continuing, initialized, or terminated. If the burst access has ended, reset the burst length counter and cause the DRAM to be ready to receive another burst access command. If both / RAS and / CAS go high during burst access, the burst access cycle is also terminated, putting the data driver into high impedance output state, and also resetting the burst length counter. If / RAS is high only and / CAS is enabled for compatibility with the hidden refresh cycle, the read data will remain valid at the device output, but only / RAS is high. Is used to terminate burst access. When it is desired to minimize the delay between burst accesses by terminating the burst read and then starting another burst read or ending burst write before another burst write, only the write enable pulse width needs to be minimized. For burst reads, / WE transitions from high to low to terminate the first burst read, then transitions / WE back to high before the next falling edge of / CAS to specify a new burst read cycle. do. In the case of burst writes, / WE transitions high to terminate the current burst write access, then transitions high again before the next falling edge of / CAS to start another burst write access.

In the basic implementation of the apparatus shown in FIG. 1, the burst length is fixed at 4, the / CAS wait time is also fixed at 2, and the sequence of interleaved burst addresses is also fixed. In this basic implementation, very few circuits need to be added to the standard EDO page mode DRAM, so that it can be mass-produced to provide the functionality of both standard EDO page mode and burst EDO DRAM. Using this device, the output enable pin (/ OE) can also be grounded for compatibility with many SIMM module designs. If / OE is not disabled (grounded), control is done asynchronously, so if it is inactive (high) before / CAS descends and remains inactive after / CAS has risen, In the read cycle, the data cannot be driven. If these setup and hold conditions are not satisfied, the read data cannot be driven in part of the read cycle. You can also synchronize the / OE signal with / CAS, but this will increase the delay from / CAS to data validity, without reading any additional / CAS low pulses until / RAS goes high. Cannot be disabled. This additional / CAS low pulse is otherwise unnecessary. In a preferred embodiment, if / OE transitions high at any time during a read cycle, the output remains high impedance until the next falling edge of / CAS despite the further transition of the / OE signal.

Burst length, / CAS wait time, and address sequence can be programmed using the mode register, which, upon receipt of a write- / CAS-before- / RAS (WCBR) programming cycle. The state of one or more address input signals 16 or data signals 10 is latched. In such a device, the output 44 from the mode register controls the essential circuit of the DRAM. Burst length options of 2, 4, 8 and full page and / CAS latency of 1, 2, 3 are available. As the operating speed of the device increases and computer architecture evolves, other burst length and latency options may also be provided. In the preferred embodiment of the apparatus of FIG. 1, the address sequence can be programmed by latching the state of the least significant address bit during the WCBR cycle with the burst length and / CAS latency of this particular embodiment fixed. Other possible characteristics that such a DRAM may have include having only a fixed burst mode, choosing between a standard fast page mode (non-EDO) or burst mode, and output enable pin (/ OE) 42 with / RAS. Use them together to select an operating mode. Rather than using / RAS and control signals together, the WCBR refresh cycle can also be used to select the operating mode. More complex memory devices use various combinations of / WE and / OE when / RAS descends to provide additional modes of operation, such as fast page mode, EDO page mode, static column mode, and switching between burst operations. May be provided. By using a WCBR cycle that encodes a desired mode using multiple addresses or data lines, one mode can be selected from a set of similar modes. In contrast, a device having multiple modes of operation has a wire bond location, a programmable fuse, or a nonvolatile memory device, which is used to program the mode of operation of the device.

A preferred embodiment of a 16-bit wide burst EDO mode DRAM designed according to the present disclosure has two column address strobe input pins / CASH and / CASL. In a read cycle, only one / CAS signal needs to be toggled. The second / CAS continues high or toggles with another / CAS. During a burst read cycle, all 16-bit data is driven in a portion of the read cycle even if one / CAS is inactive. In a typical system application, the microprocessor reads all data bits onto the data bus in each read cycle, but only writes certain bytes of data in the write cycle. Keeping one of the / CAS control signals static during the read cycle helps to reduce the total power consumption and noise in the system. For burst write access cycles, each / CAS signal (/ CASH and / CASL) operates with write enable for 8 bits wide data. The two / CAS signals are AND coupled to provide one internal / CAS that goes low when the first external / CAS falls and then returns high again after the last external / CAS goes high. When the first / CAS signal transitions low, all 16 data inputs are latched. If only one / CAS signal transitions to the low state, the 8-bit data associated with / CAS that remained high is not stored in memory.

The present invention has been described with reference to several preferred embodiments. As fast page mode DRAMs and EDO DRAMs are available in various configurations, including data widths of x1, x4, x8, and x16, and densities of 1 megabit, 4 megabits, 16 megabits, and 64 megabits; The memory device of the present invention may take the form of many different memory configurations. Those skilled in the art of integrated circuit memory design are believed to be able to design a variety of memory devices without departing from the spirit of the invention with the aid of the present specification. Therefore, it is considered that a detailed description of the configuration of various memory devices that can be applied to the present invention is not necessary.

A preferred pinout of a burst EDO memory device is shown in FIG. Note that this pinout may be the same as the pinout of standard EDO DRAM. Because pinout is common, this new device can be used in existing memory designs with minimal design changes. In addition, because pinouts are common, those skilled in the art familiar with standard EDO DRAM pinouts can facilitate new designs. In the above modification of the invention, which maintains the standard EDO DRAM pinout, the / CAS pin is driven by the system clock signal to synchronize data access of the memory device to the system clock. In this embodiment, it may be desirable to latch the row address using the first / CAS active edge after the / RAS falling, and latch the first column address of the burst access cycle using the later edge. After latching the row and column addresses in the device, the addresses may be internally incremented to provide a burst access cycle synchronized with the system clock. Another alternative to the pin is to drive the burst address increment signal to the / OE pin because it does not require the data output disable feature of the / OE pin. Another alternative use of the / OE pin is to maintain the standard EDO pinout, but provide additional functionality such as burst mode access. The / OE pin can also be used to signal the presence of a valid column start address or to terminate burst access. Each of these embodiments provides a fast burst access memory device, which may be used in current memory systems with minimal redesign.

4 is a timing diagram of executing burst recording after burst reading of the apparatus of FIG. In Figure 4, the row address is latched by the / RAS signal. For one embodiment of this design, / WE is low when / RAS is down, which uses the state of the / WE pin to specify a burst access cycle at / RAS time. Next, with / WE set high, / CAS is driven low to start burst read access and latch the column address. The data output signal DQ is not driven in the first / CAS cycle. At the second falling edge of the / CAS signal, the internal address generation circuit increments the column address and starts another array access, and the first data output is driven from the device after the time between / CAS-data access (tCAC). For devices with a burst length of 4, an additional burst access cycle continues to the fifth falling edge of / CAS, which latches a new column address for a new burst read access. When / WE drops in the fifth / CAS cycle, burst access terminates and initializes the device for further burst access. With / WE low, the sixth / CAS falling edge is used to latch the new burst address and input data and start the device's burst write access. The additional data values continue to latch until burst access ends on successive / CAS falling edges.

5 is a timing diagram illustrating that a burst read cycle comes after a burst write access cycle. As in Fig. 4, although the row address is latched using the / RAS signal, in this embodiment of the present invention, / WE is a don't care state when the / RAS descends. With / WE low, the first / CAS falling edge starts a burst write access with the latched first data. Additional data values are latched on successive / CAS falling edges, and memory addresses are incremented inside the device in an interleaved or sequential manner. At the fifth / CAS falling edge, the new column address and associated write data are latched. The burst write access cycle continues until the / WE signal goes high in the sixth / CAS cycle. The transition of the / WE signal terminates the burst write access. The seventh / CAS low state transition latches the new column address and starts a burst read access (/ WE is high). Burst reading continues until the burst access ends.

4 and 5, it should be noted that, except for a short data transition period, as long as the / OE pin is low, data remains valid at the device output during a burst read cycle. Also, since the / WE pin is low when or before / CAS is lowered, the data I / O line is not driven at that portion of the write cycle, and the / OE pin is 'don't care'. Only the / CAS signal and the data signal are toggled to relatively high frequencies, and no control signals other than / CAS need to be active or inactive for one / CAS cycle time or less. In this respect, it contrasts with SDRAM, which sometimes keeps the row address strobe, column address strobe, data mask, and read / write control signals valid for one clock cycle or less for the various functions of the device. Needs to be. In a typical DRAM, a column address may be propagated through the array to initiate data access prior to / CAS drop. This is to provide fast data access from the / CAS drop if the address was in a valid state for a time prior to CAS drop sufficient to access data from the array. In this design, an address transition detection circuit is used to resume memory access if the column address changes before / CAS drop. In this method, additional time is required to actually perform the memory access, because there must be time to prepare a new column address at the beginning of each memory cycle since the last address transition. If the column address changes just before / CAS descent, the access time increases by approximately 5 ns. In one embodiment of the present invention, the column address can be passed directly to the array only after / CAS is lowered. This eliminates the need for an address transition detection circuit and allows for fixed array access to / CAS. The column address is not delivered directly to the array until the falling / CAS transition, but the counter prepares for the next falling / CAS edge by incrementing at the / CAS rising edge and providing a valid column address.

6 is a schematic representation of a single inline memory module (SIMM) designed in accordance with the present invention. SIMM has a standard SIMM module pinout for physical compatibility with existing systems and sockets. Functional compatibility with EDO page mode SIMM is maintained when each of the 2 M x 8 memory devices 10, 12, 14, and 16 are operated in EDO page mode. Each of the / CAS signals 18, 20, 22, and 24 controls a 32-bit data bus 26, 28, 30, and 32 one byte wide. The / RAS signal 34 is used to latch a row address in each memory device, and the / RAS signal in conjunction with / WE 36 is used for a device capable of operating in both page mode and burst mode. Select one of the page mode and burst mode access cycles. The address signal 38 provides the multiplexed row and column addresses to each memory device on the SIMM. In burst mode, when each edge of the / CAS signal is used as described above, only the activated / CAS control line is required to toggle to the operating frequency of the device or its half frequency. The data line should be switchable to half the frequency of the / CAS line, or to the same frequency, and the other control and address signals should be switched to frequencies lower than the / CAS and data lines. As shown in Fig. 6, each / CAS signal and each data line can be connected to a single memory device to switch to a higher frequency than other control and address signals. Each memory device 10, 12, 14, and 16 is designed in accordance with the present invention to enable burst mode operation, in which a plurality of memory devices 10, 12, 14, and 16 can be operated in timing along the / CAS control line after latching the first row and column addresses. Internal address generation is provided for data access to memory address storage locations sequentially or interleaved.

7 is a front view of another SIMM designed in accordance with the present invention. Each device on the SIMM is a 4 megabit DRAM consisting of 1 M x 4. In this configuration, one / CAS will control two memory devices, providing access to a one byte wide data bus. The eight devices shown form a four megabyte SIMM that is 32 bits wide. In the case of a 32-bit wide 8 megabyte SIMM, there are eight additional devices behind (not shown).

8 illustrates a preferred pinout of a memory module designed in accordance with the apparatus of FIG. These pinouts are compatible with the pinouts of fast page mode SIMMs and EDO SIMMs. A presence detect pin is provided to indicate EDO operation on pin 66 and the / OE input is provided on pin 46 in accordance with standard EDO component types.

In other embodiments of the SIMM module of FIGS. 6, 7, and 8, two / RAS signals are used, each of which controls a 16-bit wide data bus according to the standard SIMM module pinout. A further 4M x 8 EDO burst mode DRAM is added to the device of FIG. 6 to prepare a 4M x 32 bit SIMM. A 16 bit wide DRAM can also be used, which typically has two / CAS signals, each of which controls 8 bits wide data. Parity bit or error detection and correction circuitry is included to provide other possible SIMM module configurations. Methods for performing error detection and / or correction are known to those skilled in the art, and detailed descriptions of such circuits will not be described herein. Additional SIMM designs using the new memory device of the present invention may be designed by one skilled in the art with the aid of this specification. Although the present invention has been described with reference to a SIMM design, it is not limited to the SIMM. The invention is equally applicable to other types of memory modules, including dual inline memory modules (DIMMs) or multi-chip modules (MCMs).

9 is a schematic diagram of a data processing apparatus designed in accordance with the present invention. In the present specification, the microprocessor may be a microprocessor, a microcontroller, a digital signal processor (DSP), an arithmetic processor, a central processing unit (CPU), or the like, but is not limited thereto. In Figure 9, microprocessor 112 is coupled to a microprocessor local bus 114, which consists of an address and control signal 116 and a data signal 118. The microprocessor is a timing and control circuit 120. Access to multiple resources. For example, the timing and control circuitry may receive address and control signals from a microprocessor and transmit the control signals to a static random access memory (SRAM) cache 117, a tightly coupled noncaching burst access DRAM 119, And the uncombined DRAM 132.

Microprocessor memory access speeds and memory bandwidths are important parameters for microprocessor system performance. To maximize this parameter, when using the SRAM cache, it is common to connect to the microprocessor local bus 114 without an intermediate data buffer or latch. In general, a main memory made of DRAM needs to provide a large amount of data storage capacity. Because microprocessors have limited bus driving capabilities, main memory consisting of several or more memory chips needs to be separated from the microprocessor through address and data buffers. In the system of FIG. 9, the microprocessor address bus is coupled to the uncoupled main memory 132 via control circuit 120 and optionally via additional buffer 130. In general, microprocessor instructions and address signals need to be reformatted in the control circuit 120. All or part of the reformatted address and control signals (126 for uncoupled memory and 127 for tightly coupled memory) also require buffering through buffer 130 to drive the load of associated memory. The buffered address and control signals for the uncoupled memory are shown as signal 128. As an example of address reformatting that must be done within the control circuit 120, a 32-bit address from a microprocessor is multiplexed into a 12-bit row address and a 12-bit column address to a 16 megabyte small memory. On a 12-bit multiplexed address bus. Reformatting the control signals generates / RAS and / CAS in response to memory access requests from the microprocessor. The microprocessor data bus 118 is coupled to the main memory data bus 134 coupled via the data transceiver 136. The data transceiver is a bidirectional data buffer that can exchange memory data with a microprocessor. The tightly coupled non-cache portion 119 of the main memory is more directly connected to the microprocessor for high speed data transfer. The microprocessor address and control signals are coupled to the tightly coupled main memory through a control circuit, which in a preferred embodiment is such that the multiplexed address signal and memory specific timing control signal 127 are tightly coupled to the main memory. to provide. Further, in order to reduce the load on the control circuit, additional buffers can be added between the control circuit and the tightly coupled memory, but this is undesirable since this causes additional delays. In a preferred embodiment, the tightly coupled memory consists of eight 2 M x 8 burst EDO DRAMs, which are soldered to a circuit board common to the microprocessor. The number of memory circuits can be other than eight, but it is desirable to provide a data width equal to the processor data width, in this case a 64-bit data bus width. Similarly, SDRAM or other burst access memory devices may be used in place of burst EDO DRAM. In such a system where a limited number of memory circuits are directly connected to the system circuit board, a high performance memory-microprocessor interface is provided. If the system is designed to accommodate a large number of tightly coupled memory configurations, the maximum performance of the memory interface must be degraded to account for variations in bus load and signal noise. After the initial access delay, the burst EDO DRAM may provide data to the microprocessor at each clock cycle during the burst access. This is in contrast to the uncoupled main memory, which typically requires idle clock cycles (standby states) between data accesses in page mode operation.

The control circuit 120 also provides the microprocessor with access to other system components located on the local system bus 140. The local bus 140 may be a Peripheral Component Interconnect (PCI) bus, a Video Electronics Standards Association (VESA) Local Bus (VL), or an equivalent architecture. The VL bus is primarily used in computers using Intel 486 generation microprocessors. The PCI bus is used primarily for Intel Pentium-class microprocessors, but is also widely used for computers using IBM Power PC microprocessors. Similarly, computers using next generation microprocessors will have new local bus standards, but this does not depart from the scope or spirit of the present invention. The local bus has access to the main memory which is sub-coupled via the control circuit 120 and the additional data transceiver set 138. The control circuit 120 controls access to the tightly coupled device from the peripheral device via the local system bus 140.

Additional control circuitry 150 may be used to provide an interface to the Industry Standard Architecture (ISA) bus 154. The bus provides compatibility with previous generations of computers and peripherals designed for use. Additional peripherals 152 such as keyboards, mice, CD ROM drives, floppy disk drives, hard drives, etc., are also interfaced to the local bus via control circuit 150. A computer add-in card 158 designed according to the ISA bus interface is accessed by a microprocessor or system resources through the ISA bus. Basic Input Output System (BIOS) ROM 156 is also accessible via the ISA bus. Interface signal 148 controls the device and other peripheral devices on the ISA bus to access the PCI bus. Video frame buffer card 144 is commonly interfaced to the local bus to improve system performance as the display buffer bandwidth continues to increase. Another PCI card 146 may be present on the PCI bus. In such a system architecture, the system components accessed by the microprocessor most often are placed on the microprocessor local bus to improve overall system performance. Other frequently accessed devices, such as video buffers, are accessed via the local system bus. Finally, devices with slow access times or that are not critical to overall system performance are on the ISA bus. The local bus and ISA bus are usually integrated into the system motherboard. The processor, cache memory, and main memory are also located on the system motherboard, but it is also possible to place some or all of these system components on the secondary board to facilitate performance upgrades by replacing the secondary board with a higher performance processor subsystem. . Multiprocessor systems are also possible, where in a preferred embodiment each processor has one of its own tightly coupled main memory subsystems, its own coupled memory subsystem or a sharedly coupled memory subsystem.

In operation, when there is a tightly coupled burst EDO main memory portion, the microprocessor reads data by supplying address and control signals to the memory through memory controller circuitry. In response to the initial address, read command, and access cycle strobe, the memory begins to access the first data word at the initial address. The second access cycle strobe increments the address in the memory in the second access period of the burst access and initiates a read access of data from the second address. If the wait time is 2, the first data is driven from the memory after the second access cycle strobe signal is generated. Typically, the first data is latched in the microprocessor in response to a third access cycle strobe that occurs at the beginning of the third access cycle period of the burst access. The third access cycle strobe also drives the second data value from the memory. The third access cycle strobe also generates the third address in memory, and the third data access begins. The burst data is latched in the microprocessor in response to the third, fourth, fifth, and sixth access cycle strobes in the case of four word burst access. In this way, four data values are received by the microprocessor in response to a single address and multiple access cycle strobes. If the memory is designed to execute a four word burst sequence and requires additional data values to the memory, the microprocessor provides a second address to the memory with a fifth access cycle strobe signal. In this case, the second four word burst sequence begins while the microprocessor is receiving data from the first four word burst. The relationship of the burst access to the 66 MHz system clock is, for example, as follows: first cycle, latching address and control information to the control circuit 120; In a second cycle, generating a row address and a / RAS signal for a memory tightly coupled to the signal line 127; In a third cycle, generating a column address in the signal line 127; Fourth cycle, generating a first access cycle strobe on signal line 127; Fifth cycle, generating a second access cycle strobe on signal line 127; Generate a sixth cycle, a third access cycle strobe and latch the first data value to the microprocessor via the data bus 118; It then generates a cycle, access cycle strobe and latches the data to the microprocessor. For four word burst access, the timing when the first data value is latched after six system clock cycles and the next three data values are latched in the next system clock cycle is described as 6-1-1-1. can do. A typical SRAM cache, in contrast, supplies data in a 3-1-1-1 sequence. While cache hits are typically limited to approximately 80% due to the size limitations of the SRAM cache, relatively large, tightly coupled memory provides a hit rate close to 100%. In systems without tightly coupled memory, it is common for cache misses to result in a 7-2-2-2 access sequence from the loosely coupled memory. If the hit rate is 100% with only uncombined main memory, then the average access cycle time is (7 + 2 + 2 + 2) /4=3.25 system clock cycles. The tightly coupled main memory with a 100% hit rate results in an average access cycle time of 9/4 = 2.25 system clock cycles. Similarly, a system including a uncoupled main memory and an SRAM cache can see that the average access cycle time is [(.8x6) + (. 2x13)] / 4 = 1.85 system clock cycles. As a result, a tightly coupled system with an SRAM cache has an average access time of 1.65 system clock cycles when the cache hit rate is 80% and the tightly coupled memory hit rate is 20%. These values represent both the read and write access times for the main memory combined with the SRAM cache. However, it is common for the tightly coupled burst EDO memory write cycles to be faster because there is no latency associated with the access cycle signal. This means that tightly coupled memory burst writes result in a 4-1-1-1 write cycle sequence. The inclusion of tightly coupled main memory provides a medium to high performance system without the use of an SRAM cache, or a very high performance system with an SRAM cache.

Burst EDO memory devices of the present invention can operate with shorter cycle times than conventional DRAMs and are therefore particularly suitable for use in tightly coupled main memory applications. Placing a conventional DRAM memory directly on the processor bus has little benefit, because the cycle time is long enough (perhaps two system clock cycles), so adding an additional data buffer does not increase the access time much while the data buffer If not, it will put a load on the processor data bus. On the other hand, if a data buffer is included, the burst EDO DRAM will not be able to operate at a relatively high clock frequency, for example with a 6-1-1-1 access sequence, because the delay of the buffer is almost all of the minimum cycle time. Because it occupies.

In a preferred embodiment of the present invention, the uncoupled memory 132 of FIG. 9 is operated with one of two or more different types of memory. For example, the memory may be comprised of a burst EDO, fast page mode, or EDO memory device. The system may be adapted to accommodate a memory module having, for example, a fast page mode, EDO, or burst EDO memory device, in which case the module will have the same or nearly the same pinout so that the system can be expanded and the memory combined You can add or upgrade.

Flash memory and SDRAM memory are also suitable for use in fused memory, but they are typically incompatible with other types of memory devices, thus limiting the variety of system configurations. In particular, flash memory may be advantageous for use in portable computers, where flash memory has certain performance advantages over magnetic hard disk drive technology. In this configuration, the uncoupled nonvolatile memory bank can function as an internal solid state hard drive, in which case the available memory (not disk space) is a low performance random access memory. Can be extended to a high performance tightly coupled memory subsystem.

10 is a schematic diagram of another embodiment of the present invention. Elements having functions and descriptions common to those of Fig. 9 are numbered accordingly. In FIG. 10, the uncoupled main memory 132 has a memory data bus 134, which controls and buffers data paths between the uncombined memory and the CPU 112 via the processor bus 114. It is coupled to the control circuit 120 to provide. The control circuit 120 also provides access to the uncoupled main memory from other system components via the system bus 140. As clearly shown in FIG. 10, display device 160 is coupled to video control circuitry 144, which may include a display frame buffer. The display device includes, but is not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), or a field emission display (FED).

11 is a timing diagram of a method of determining what kind of memory is present in a system as disclosed herein. To provide one particular embodiment, the data values shown are for a system having a data width of four bits. In practice, a typical system data bus may have 8, 16, 32, 64, or other data widths. Similarly, observing this timing diagram with reference to the system of FIG. 9, the method described above may utilize a memory device capable of operating in one or more of at least two different access modes in accordance with the teachings of the present invention. Equally useful for a wide variety of system configurations. In Fig. 11, two data values are recorded in the memory using the page mode recording format. This format correctly stores data in fast page mode, EDO, or burst EDO memory devices. If the memory is a burst EDO, the second column address represented by (Cn + 1) is ignored by the memory device or devices to be written because the second address is generated internally. After writing the two data values 0110 and 1001 selected so that they can be easily distinguished from the undriven bus and from each other easily, the memory is read in burst EDO format. Waveforms with DATA FPM represent the data bus of a system whose memory is operating in fast page mode. A waveform with DATA EDO written represents the data bus of a system whose memory is operating in EDO mode. A waveform with DATA BEDO written represents the data bus of a system whose memory is operating in burst EDO mode. Vertical lines t1, t2, t3, t4, and t5 represent some times at which data can be sampled to distinguish different types of memory present in the system. Especially at time t5, each memory type provides a different response to the read operation. The fast page mode memory does not drive the data bus because / CAS is high at time t5. When the bus is not driven, the bus is typically terminated to a level that is either floated or digitally interpreted as a pattern of high states, low states, or high and low values. In no case will the data match the recorded pattern. In systems using narrow data buses or when the bus characteristics are unknown, it is desirable to repeat the method with various data patterns so that the bus does not provide a signal level that is interpreted as matching the recorded data. In a wide data bus, it is not very likely that a large number of patterns will be needed since the undriven bus is very unlikely to match a pattern of random or properly changing data bits. Possible patterns for a 32-bit data bus are, for example, 0110 1001 1111 0001 1100 0011 0000 1110. At time t5, since the read address does not change from cycle to cycle, the EDO memory drives data from the column address Cn to the data bus. In the example of FIG. 11, this value is 0110. At time t5, the burst EDO memory automatically increments the internal address in the burst read access cycle, so the burst EDO memory with latency 2 provides data from column address Cn + 1. As such, whether the memory type is a fast page mode, an EDO, or a burst EDO may be determined at time t5. In a more comprehensive method, two or more write cycles and three or more read cycles are executed in consideration of the case of a burst EDO memory device having a wait time other than two. For example, if four read cycles are followed by five read cycles and data is sampled when / CAS is high after the fifth read cycle, the data is bus-dependent for fast page mode memory. bus dependent) and continue to be equal to the first data value for the EDO memory, and any of the fourth, third, or second data values for the burst EDO memory having a wait time of 2, 3, or 4, respectively. Same as

In another method in accordance with the present invention, while providing multiple data patterns while toggling / CAS, data is written in burst mode format to maintain column addresses at Cn. Read cycles at address Cn + x (Cn + x is within the range of addresses to be written in the burst EDO memory device) are performed as part of a burst or page mode read sequence. The data pattern read from address Cn + x will match the pattern written to Cn + x after the wait time if the memory is a burst EDO memory. Fast page mode and EDO memory provide any data that was present in Cn + x prior to burst mode write. Alternatively, a single read cycle to address Cn, where the data is sampled near the end of the / CAS low state period, provides a valid data output for fast page mode or EDO memory, but for burst EDO memory. The latency is not satisfied and therefore does not provide a valid data output.

In each of the above methods for determining the type of memory present in the system, the step of placing the memory in a particular mode should be performed if the memory itself has a plurality of operating modes. To determine the operating modes that the memory supports, the memory is tested after performing the appropriate procedure for placing the desired memory in each of the operating modes. Also, if the memory has the ability to switch between these addressing modes, linear to sequential addressing mode should be considered. Prior to performing the method described above, the SRAM cache may need to be disabled, or additional steps may be required to ensure that the data being read is not the cached data. In addition, known background data patterns may be written in the address range to avoid erroneous data matching for uninitialized memory locations when the method is used.

The present invention realizes a system having multiple memory banks in the case where some or all memory banks have one of several kinds of memory. In a system designed according to these instructions, each bank is tested as described above, respectively. The memory controller of the system is programmed to access each bank according to the type of memory present.

While the invention has been described with reference to preferred embodiments, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of the invention.

Claims (62)

In a memory device having a plurality of memory elements each having an associated address, Receive at least a first portion of an address from a source external to said memory device in response to a transition of an address strobe signal and further increment said address in a predetermined address sequence in response to a subsequent transition of said address strobe signal. An addressing circuit; And An output buffer circuit adapted to drive data with burst read access from the memory device only after a plurality of transitions of the address strobe signal The memory device further comprises. The circuit of claim 1, wherein the output buffer circuit further comprises: And switch between a logic low data value and a logic high data value in response to a single transition of the address strobe signal. The circuit of claim 1, wherein the output buffer circuit further comprises: Drive a logic low data value from the device after the falling edge of the address strobe signal, and then drive a logic high data value from the device after a rising edge of the address strobe signal. Device. In a memory device having a plurality of memory elements each having an associated address, Addressing circuitry adapted to provide a series of addresses in a burst mode of operation; And A write enable signal node for receiving a write enable signal configured to select between a read cycle and a write cycle of the memory device Include more, And burst access of the memory device terminates in response to a transition of the write enable signal. A memory device having an address latch node for receiving an address strobe signal, an address latch for receiving at least a portion of a first memory address, and a memory element array, comprising: An address generating circuit for generating a second memory address in response to an output of said address strobe signal and said address latch, said second memory address being used to access said array; And An output circuit in electrical communication with the address latch node to drive data received from the array after the plurality of transitions of the address strobe signal to the outside of the memory device; Memory device comprising a. The method of claim 5, wherein the output circuit, And drive data out of the memory device after a programmable number of transitions of the address strobe signal. The method of claim 5, An output enable signal node for receiving an output enable signal to enable data to be driven from the memory device; And Means for performing a burst read and burst write access cycle while the output enable signal node is connected to a supply potential node that defines a state of the output enable signal for enabling data to be driven The memory device further comprises. The method of claim 5, wherein the address latch receives a column portion of the first address, The memory device, A row address strobe signal node for receiving a row address strobe signal; A row address latch coupled to the row address strobe signal node for latching a row address in response to the row address strobe signal; A control signal node for receiving a control signal; And A mode control latch for electrically communicating with said control signal node and said row address strobe signal node to latch a state of said control signal upon transition of said row address strobe signal, said condition being non-burst mode of said memory device. Used to select between burst modes The memory device further comprises. 9. The memory device of claim 8, wherein the control signal node is a write cycle enable signal node. 6. The apparatus of claim 5, wherein the address generation circuitry latches a first column address in response to a first transition of the address strobe signal and generates a second column address in response to a second transition of the address strobe signal. And incrementing the first column address. 6. The memory device of claim 5, wherein said address latch comprises a transparent latch. A memory device having an address strobe signal node and a memory element array for receiving an address strobe signal, the memory device comprising: An address latch for latching at least a portion of a first initial memory address to the memory device in response to a first transition of the address strobe signal; An address generating circuit adapted to generate a series of burst addresses that are determinable from the first initial memory address, wherein each burst address is generated in response to a corresponding transition of the address strobe signal; And At least a portion of a second initial address to the memory device in electrical communication with the address latch and the address strobe signal node in response to the address strobe signal after a predetermined number of burst access cycles have been performed. Control circuitry to enable latching Memory device comprising a. 13. The memory device of claim 12, wherein the predetermined number of burst access cycles is a programmable number. The method of claim 12, Write Enable Signal Node to Receive Write Enable Signal Include more, And burst access of said memory device is interrupted in response to a transition of said write enable signal. A memory device having a plurality of data nodes for receiving and driving a plurality of data signals, a memory element array, and a plurality of address nodes for receiving row addresses and column addresses, A row address strobe node for receiving a row address strobe signal to latch a row address in the memory device; A write control signal node for receiving a write control signal to select between read access and write access of the memory device; And First and second column address strobe nodes for receiving first and second column address strobe signals, respectively Including but not limited to: One of the first and second column address strobe signals latches the column address signal, and one of the first and second column address strobe signals that are activated during read access of the memory device is assigned to each of the data nodes. Responsive to enabling data, only a first plurality of data signals, the write control signal selecting write access, the first column address strobe node being active, and the second column address strobe node being inactive And stored in the array. A memory device having a memory element array in which a row address is selected, Means for selecting a first column address and accessing elements of a memory element array at said row and first column addresses in response to a transition of a column address strobe signal; Means for modifying said first column address within said memory device to provide a second column address and access another said array element in response to said column address strobe signal; An output buffer for providing output data from the memory device in burst read access only after a plurality of transitions of the column address strobe signal; And Control circuitry for terminating burst access of the memory device in response to a write enable signal Memory device comprising a. 17. The memory device of claim 16, further comprising burst mode enable means for enabling a burst operation mode of the memory device. 17. The memory device of claim 16, further comprising means for disabling a burst mode of operation of the memory device. 19. The memory device of claim 18, further comprising a mode control latch for latching an operation mode of the memory device when the row address is selected. The method of claim 16, A row address strobe signal node that receives a row address strobe signal to select the row address; A write enable input node for receiving the write enable signal; And The memory in response to an active state of the write enable signal when coupled to at least one of the write enable input node and the address signal input nodes when the row address strobe signal is activated following activation of the column address strobe signal; Mode control latch circuit for latching the operating mode of the device The memory device further comprises. Basically, a column address strobe signal, where the cycle of this signal defines an access cycle period, receives a plurality of signals consisting of a row address strobe signal, a write enable signal, an output enable signal, an address signal, a data signal, and a power supply signal. A memory device having an external node for Perform burst write access of the first plurality of memory elements in response to a first plurality of transitions of the first address and the column address strobe signal, and in response to a second plurality of transitions of the second address and the column address strobe signal Means for performing burst read access of the second plurality of memory elements, Transition of the write enable signal terminates the burst mode of the memory device. 22. The apparatus of claim 21, further comprising a data output circuit for driving data from the memory device with a burst read access, The first data signal from the third plurality of memory elements is a continuous series of bursts by being driven from the memory device in a subsequent burst read access after the last data signal of the second plurality of memory elements is driven from the memory device. Providing a read memory cycle. A method of reading data from a memory device having an address latch, an address counter, an address strobe node for receiving a column address strobe, an output data driver, and a memory element array, the method comprising: Applying a first column address strobe to the address strobe node to latch a first column address; Accessing a first memory element of the memory element array at the first column address; Applying a second column address strobe to the address strobe node to increment the column address in the memory device to determine a second column address; Accessing a second memory element of the memory element array at the second column address; Switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; And Maintaining a high impedance state in the output data driver until at least the step of applying the second column address strobe And data reading method from a memory device. The method of claim 23, wherein Applying a third column address strobe to the address strobe node to increment the column address to determine a third column address; And Latching an output of the memory device from the first column address in synchronization with the third column address strobe And reading data from the memory device. 24. The method of claim 23, further comprising selecting a burst mode of operation of the memory device prior to applying the first column address strobe. A method of terminating burst access of a memory device having an array of memory elements, an address generating circuit providing a plurality of addresses for accessing the array, and a read / write cycle input node for receiving a write enable signal. Toggling said write enable signal during said burst access. 27. The method of claim 26, further comprising resetting a burst length counter in response to toggling the write enable signal during the burst access. A memory device having an array of a plurality of memory elements each having an associated address; A plurality of address lines coupled to the memory device; And Address strobe signal lines electrically coupled to the memory device Including, The memory device latches an address in the memory device from the plurality of address lines in response to an address strobe signal received on the address strobe signal line, and the memory device receives the address strobe signal received on the address strobe signal line. Single In Line Memory Module, characterized in that to increment the address in the memory device in a predetermined sequence in response to a transition of. The method of claim 28, wherein the memory chip, And a data node for driving data from the single in-line memory module, wherein the driven data is switched from a first data value to a second data value in response to a single transition of the address strobe signal. Line memory module. 30. The apparatus of claim 29, wherein the first transition of the address strobe signal is used to latch a first address in the memory device, And a first data value from said first address of said memory device is driven from said data node in response to a second transition of said address strobe signal. 29. The single in-line memory module of claim 28 further comprising means for inhibiting the address strobe signal from incrementing the address. 29. The method of claim 28, wherein if a write enable signal on a write cycle control line is active when the address strobe signal line latches the address, selecting write access of the memory chip and terminating burst access of the memory chip. And a write cycle control line for the single in-line memory module. 29. The single in-line memory module of claim 28 wherein the memory chip further comprises an output enable signal node coupled to a ground potential node of the single in-line memory module. Memory devices; A plurality of address signal lines coupled to the memory device for providing an address to the memory device; An address strobe signal line coupled to the memory device; And Coupled to the address strobe signal line to receive and increment the address to provide multiple data access of the memory device in synchronization with multiple transitions of address strobe signals on the address strobe signal line after only one address is received. Address generation circuit in the memory device for Memory module comprising a. The method of claim 34, wherein Control signal lines; And Used in combination with the address strobe signal line to select between read data access and write data access of the memory device, and in combination with the control signal line to select between synchronous burst access cycles and asynchronous non-burst access cycles of the memory device. Enable signal line The memory module further comprises. 35. The method of claim 34, further comprising a write enable signal line for receiving a write enable signal, Wherein a transition of the write enable signal on the write enable signal line during the burst access cycle terminates the burst access cycle. 35. The method of claim 34, further comprising at least one data node for transmitting data to and receiving data from the memory module. Data from the memory module transitions from a first data value to a second data value in response to a single transition of a signal on the address strobe signal line, Data is driven from the memory module with a burst read access of the memory module only after a plurality of transitions of a signal on the address strobe signal line. In a computer system capable of fast storage and retrieval of data, Microprocessor; And Memory circuitry configured to store and retrieve data with burst access in response to memory address and address strobe signals received from the microprocessor Including but not limited to: The memory circuit is configured to latch the memory address and perform a first memory access in response to the first transition of the address strobe signal within the burst access, and each of the plurality of additional transitions of the address strobe signal within the burst access. And generate additional memory addresses in response to and perform memory access cycles. 39. The computer system of claim 38 wherein data read from the memory address of the memory circuit is provided to the microprocessor by the memory circuit in burst access after at least two transitions of the address strobe signal. . 40. The microprocessor of claim 39, wherein additional data values from a predetermined address sequence of the memory circuit are in response to the additional transition of the address strobe signal after the microprocessor receives data from the memory address. Computer system, characterized in that provided by. 39. The computer system of claim 38 wherein the memory circuit comprises a dynamic random access memory (DRAM) element. A microprocessor providing an address; And A memory device holding data at a location corresponding to the address, the memory providing burst access in response to the address Including but not limited to: The burst access, A plurality of periods, wherein a column address strobe signal is received by the memory in each period; A column address portion of the address received by the memory device only in a first period of the plurality of periods in response to the column address strobe signal; And And wherein data at a location corresponding to the address is provided to the output of the memory device after at least two cycles. 43. The computer system of claim 42 wherein the memory device is attached to a single in-line memory module. 43. The computer system of claim 42 wherein the column address strobe signal is provided from the computer system to the memory device in synchronization with a system clock signal. A computer system capable of high speed data storage and retrieval, Microprocessor; And Burst Extended Data Out (EDO) memory device for storing and retrieving data with burst access in response to a memory address and address strobe signal received from the microprocessor Including but not limited to: The burst EDO memory device is operable to latch the memory address and perform a first memory access in response to a first transition of the address strobe signal within the burst access, and further, a plurality of the address strobe signals within the burst access. And generate an additional memory address and perform a memory access cycle in response to each of the additional transitions. 46. The computer system of claim 45 wherein the burst access terminates in response to a transition of a write enable signal received by the burst EDO memory device. A burst access memory device, An array of memory elements; And A column addressing circuit coupled to the array of memory elements for generating a series of column addresses in burst access of the memory device in response to a column address strobe signal Including but not limited to: And said burst access memory device terminates said burst access in response to a transition of a write cycle control signal. 48. The burst of claim 47 wherein data from the burst access memory device is driven from the burst access memory device in burst read access only after at least two high to low transitions of the column address strobe signal. Access memory device. The method of claim 48, An output enable node configured to receive an output enable signal; And Data output node Include more, The data from the burst access memory device is valid at the data output node within a predetermined period after the high to low transition of the column address strobe signal in the burst read access while the output enable signal is active. A burst access memory device. A memory device having an array of memory elements and an output node, wherein the output node is for driving data from the memory device. Address generation circuitry for providing a plurality of addresses to said array for accessing said array in burst mode; And Output Enable Pins Configured to Receive Output Enable Signals Including, The output enable signal when inactive during a read cycle operates the output node to be in a high impedance state and the memory device is in both read and write burst access while the output enable signal is active. Memory device, characterized in that for operation. 51. The apparatus of claim 50, wherein the address generation circuit is configured to receive at least a first portion of an address from a source external to the memory device in response to a transition of an address latch signal, and further to a subsequent transition of the address latch signal. Responsive to the address in a predetermined address sequence. The method of claim 51, An output buffer circuit adapted to switch between a logic low data value and a logic high data value in response to a single transition of the address latch signal The memory device further comprises. 51. The method of claim 50, An output buffer circuit adapted to drive data from the memory device with a burst read access only after a plurality of transitions of the address latch signal The memory device further comprises. 51. The method of claim 50, An output driver circuit coupled to the output enable pin and the output node and bringing the output node into a high impedance state in response to the output enable pin. The memory device further comprises. 51. The method of claim 50, The output buffer circuit is configured to drive a logic low data value from the device after the falling edge of the address latch signal, and then to drive a logic high data value from the device after the rising edge of the address latch signal. There is a memory device. A memory device having an output enable pin and a data output node, wherein the output enable pin is to enable data drive from the memory device, and the data output node is to drive data from the memory device; Means for reading data from the memory device in burst mode in response to an address strobe signal; And Place the data output node in a high impedance state in response to a transition of the output enable signal on the output enable pin and despite the additional transition of the output enable signal prior to the additional transition of the address strobe signal. Means for maintaining the data output node in a high impedance state Memory device comprising a. The method of claim 56, wherein Further comprising a write enable node coupled to the reading means, Transition of the write enable signal received on the write enable node terminates the burst access of the memory device. The method of claim 56, wherein the reading means, An address latch node for receiving an address latch signal; An address latch for receiving an array of memory elements and at least a portion of the first memory address; And An address generating circuit for generating a second memory address in response to the address latch signal and an output of the address latch, wherein the second memory address is used to access the array Memory device comprising a. A method of accessing a further memory element of a memory device having an array of memory elements, one of said elements being identified and accessed, said memory device having an address strobe node for receiving an address latch, an address counter, and a column address strobe. And output data, wherein Providing an address of the additional device from within the memory device and accessing the additional device in response to a transition of an address latch signal, The address providing step, Applying a first column address strobe to the address strobe node to latch a first column address; Accessing a first memory element of the array of memory elements at the first column address; Applying a second column address strobe to the address strobe node to increment the column address in the memory device to determine a second column address; Accessing a second memory element of the array of memory elements at the second column address; Switching data driven by an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; And Maintaining a high impedance state in the output data driver until at least the step of applying the second column address strobe Memory device access method comprising a. The method of claim 59, Driving data from one element of the memory device after a plurality of transitions of the address latch signal The method of claim 1, further comprising a memory device. The method of claim 59, Applying a third column address strobe to the address strobe node to increment the column address to determine a third column address; And Latching an output of the memory device from the first column address in synchronization with the third column address strobe The method of claim 1, further comprising a memory device. 62. The method of claim 61, Selecting a burst operation mode of the memory device prior to applying the first column address strobe The method of claim 1, further comprising a memory device.