KR100776943B1 - Video capture card having a high quality and capture method of multichannel video - Google Patents

Abstract

A high quality video capture card and a multichannel video capture method are provided to solve problems which occur when a video capture IC for one channel is applied to a multichannel capture system with high quality in the conventional method. A high quality video capture card comprises a buffering controller(130), a frame buffer(140), and a PCI(Peripheral Component Interconnect) interface(150). The buffer controller(130) receives a digital video signal of one channel, extracts information for data buffering, and controls a buffering. The frame buffer(140) buffers the digital video data at one storage area matched with one channel according to a control signal of the buffer controller(130). The PCI interface(150) transmits a data transmission request signal to a PCI bus, receives a data transmission admission signal from the PCI bus, extracts the stored data from the frame buffer(140), and transmits the extracted data to the PCI bus in case that data more than a criterion is stored at the storage area.

Description

VIDEO CAPTURE CARD HAVING A HIGH QUALITY AND CAPTURE METHOD OF MULTICHANNEL VIDEO}

Fig. 1 is a block diagram showing the structure of a conventional general video capture IC (CX23880).

2 is a diagram illustrating a connection state of a plurality of video capturing ICs and a PCI bridge IC for a conventional multi-channel implementation.

3 is a timing diagram illustrating a data transmission process between a conventional PCI card (40, 50, 60) and a bridge.

4 is a block diagram illustrating a high performance video capture system of the present invention.

5 is a block diagram illustrating a video capture card of the present invention.

6 is a block diagram illustrating in detail the configuration of the buffering control unit of the present invention.

7 is a diagram illustrating a data transmission process between a frame buffer and a PC system memory through the PCI interface unit of the present invention.

8 is a diagram showing the structure of a frame buffer of the present invention.

<Description of Main Parts of Drawings>

10: video capture IC 11,120: video decoder

12: scaler 13,133,151: FIFO

14: DMA 15: PCI interface

16170: PCI bus 20: PCI bridge IC

30: PCI secondary bus 40, 50, 60: PCI card

70: bridge 80: CPU

100: hardware 110: video capture card

130: buffering control unit 131: video signal interface means

132: timing information extraction module 134: frame buffer address setting module

135: frame buffer address providing module 136: SDRAM controller

137: SDRAM arbiter 138: video data reading means

140: frame buffer 150: PCI interface unit

160: local bus 200: device driver

300: Application Software 400: PC System Memory

The present invention provides a high-performance video capture card and a multi-channel video that enable the conventional 1-channel video capture IC to be applied to a multi-channel high performance capture system by double buffering a video frame using a buffering controller and synchronous dynamic random access memory (SDRAM). To a capture method.

The technology of converting an analog video signal into a digital video signal is used in many fields. Typical examples include TV reception cards used in general PCs, picture archiving and communication systems (PACS) used for medical purposes, and machine vision used for industrial purposes. The development of this technology involves converting analog video signals into digital video signals, controlling frame buffers, efficiently transferring data using a peripheral component interconnect (PCI) bus, and writing highly difficult device drivers. Etc. are required.

Among them, in particular, a technique for managing a frame buffer has been widely used in compression, decompression, and processing of video data. More specifically, the method of controlling the frame buffer is almost essential in a video processing system such as a moving picture expert group (MPEG) 1/2, an encoder / decoder, as well as a video capture system. In particular, since the video processing system processes the video data in real time, how efficiently the bandwidth of the frame buffer is used is an important problem. To this end, many techniques such as operating frequency, data bus width, burst length, buffering technique, and separate storage of brightness and color information have been studied according to the data throughput.

In particular, with the advent of digital video recorders (DVRs), which are used as video surveillance equipment recently, not only 1 channel but also 4, 8, 16 channels, multi-channel and capture performance based on 30 to 240 frames per second (320x240 resolution) The high-performance video capture card up to) comes up. Most video capture cards use general purpose video capture ICs. The most popular ICs in recent years include the Conexant CX23880 and Philips SAA7146. Hereinafter, the configuration of a conventional high performance video capture card will be described using the CX23880 as an example, and the problems in capturing multi-channel and high performance video will be described.

Fig. 1 is a block diagram showing the structure of a conventional general video capture IC (CX23880).

As shown in FIG. 1, the IC 10 for video capturing includes an analog-to-digital converter (ADC), a video decoder 11, a scaler 12, and a video FIFO for capturing an analog video signal. in first-out, 13), direct memory access (DMA) 14, and PCI interface 15.

Looking at the data capture process through the video capture IC 10, the video decoder 11 converts an analog video input signal into a digital video signal. Thereafter, the digital video signal converted by the scaler 12 is scaled to a desired resolution and then buffered in the video FIFO 13. When the data accumulated in the video FIFO 13 reaches a specific level, the data is transmitted to the PCI bus 16 via the PCI interface 15 using the DMA 14 engine.

The video data is input to the video capturing IC 10 at a rate of 24 MBytes / sec per second (768 pixels x 625 lines x 2 Bytes x 25 Frames = 24,000,000 Bytes in the case of a phase alternation by line system (PAL)). Can be. Since the maximum bandwidth of the PCI bus 16 is 132 MBytes / sec (33 Mhz * 4 Bytes), it can cover the input speed of the video data. However, since one PCI bus 16 is shared by several devices, the video data It may occur that the PCI bus 16 is not immediately available when transmitting. To prevent this, an appropriate amount of data buffering is required. The video capturing IC 10 includes a built-in FIFO 13 capable of buffering four lines. 4 lines is 6144 Bytes (768 Pixel / Line * 2 Bytes / Pixel * 4 Line = 6144 Bytes), or 256 us (6144 Bytes / 24 MBytes / sec = 256 us). At least once within a maximum of 256 us, video data must be transmitted to the host computer using the PCI bus 16 so that no overflow occurs in the FIFO 13. If an overflow occurs in the FIFO 13 even once, the captured image may be distorted.

In addition, the maximum amount of data that can be transmitted through the PCI bus 16 during the 256 us is 33 KBytes (132 MBytes / sec * 256 us = 33792 Bytes). If some of the devices connected to the PCI bus 16 instantaneously transmit more than 33 KBytes of data, the image may be distorted. Alternatively, image distortion may occur when multiple devices are connected to the PCI bus 16 and these devices all transmit data instantaneously.

FIG. 2 is a diagram illustrating a connection state between a plurality of video capturing ICs and a PCI bus for implementing a conventional multi-channel.

Referring to FIG. 2, the possibility of implementing a high-performance video capture card capable of operating at 16 channels and 120 FPS using the video capture IC 10 will be described. In order to input a 16-channel video signal, 16 video capturing ICs 10 and a PCI bridge IC 20 interconnecting the video capturing ICs 10 and the PCI bus 16 are required. The PCI bridge IC 20 is required to be able to be connected to the PCI secondary bus (30) as much as possible in order to communicate smoothly with the 16 video capture IC (10). For example, PLX Technology's PCI6156 IC can connect up to 10 video capture ICs 10 to the PCI secondary bus 30. For convenience, only 8 video capture ICs 10 connected to one PCI bridge IC 20 are shown in FIG. 2, but in practice, 16 video capture ICs 10 are connected to two PCI bridge ICs 20. do.

In addition, other PCI cards 50 and 60 may be connected to the PCI bus 16 in addition to the PCI card 40 including the video capturing IC 10 and the PCI bridge IC 20 described above. In addition, the PCI bus 16 receives a request signal req of the PCI cards 40, 50, and 60, and transmits a response signal gnt indicating a PCI card that can occupy the PCI bus 16. A bridge (particularly an arbiter of the bridge performs the above function, 70) is connected. The bridge 70 is generally connected to the CPU 80 via a host bus.

Each video capturing IC 10 transmits a request signal to the PCI bridge IC 20, and the PCI bridge IC 20 requests a bridge 70 to capture a large amount of multi-channel real-time data as described above. When the signal req1 is transmitted and the bridge 70 transmits the response signal gnt1 to the first PCI card 40, the PCI bridge IC 20 sends a response signal to the corresponding video capturing IC 10. And transmits data from the video capturing IC to the bridge 70 via the PCI bus 16. Hereinafter, the transmission timing of the captured video data will be described with reference to FIG. 3.

3 is a timing diagram illustrating a data transmission process between a conventional PCI card (40, 50, 60) and a bridge.

Referring to FIG. 3, assuming that request signals req 1, req 2, and req 3 are transmitted from the three PCI cards 40, 50, and 60 to the bridge 70, the bridge 70 requests the request. The response signals gnt 1, gnt 2, and gnt 3 are sequentially transmitted to the PCI cards 40, 50, and 60 according to the signal transmission order. However, unlike the request signal, the transmission of the response signal means the monopoly of the PCI bus 16 of a specific PCI card, so that the response signal gnt 3 of the priority is received from the third PCI card 60 to the bridge 70. Until the data transmission is completed, the lower priority PCI cards 40 and 50 wait to receive the response signals gnt 1 and gnt 2. When there are two PCI cards 50 and 60 that are higher priority than the first PCI card 40 as shown in the drawing, the request signal and the response signal are due to the PCI bus 16 monopoly of the priority PCI cards 50 and 60. The latency between them increases with the first PCI card 40, which is subordinate, so the importance of data buffering becomes greater.

For example, the video capture IC 10 included in the first PCI card 40 is capable of buffering data as much as 256us, and the data corresponding to 128us or more in the FIFO 13 of the video capture IC 10. When the first PCI card 40 transmits the request signal req 1 to the bridge 70 when the value is full, the FIFO 13 of the video capturing IC 10 overflows when the latency exceeds 128 us. Will occur. That is, the image captured through the video capturing IC 10 is distorted and cannot perform normal transmission.

In order to prevent image distortion due to the latency, smooth data buffering using a large buffer is inevitably required. To this end, the capacity of the FIFO 13 of the video capturing IC 10 may be increased. However, the SRAM constituting the FIFO 13 is expensive, and there is a limit. This may cause an increase in the configuration of the system, which may cause a failure.

The present invention devised to solve the above problems is an object of the present invention to solve the problems that may occur when applying a conventional one-channel video capture IC to a multi-channel high-performance capture system. More specifically, it is an object to provide a high performance video capture card by buffering video frames using a buffering control unit and SDRAM.

As a technical means for achieving the above object, a first aspect of the present invention receives a digital video signal of at least one channel to extract information for data buffering, the buffering control unit for controlling the buffering process; A frame buffer for buffering digital video data in at least one storage area corresponding to the at least one channel, respectively, according to a control signal of the buffering controller; And transmitting a data transmission request signal to a PCI bus when data above a reference value is stored in at least one storage area of the at least one storage area, and reading data stored in the frame buffer when receiving a data transmission acceptance signal from the PCI bus. To provide a video capture card including a PCI interface for transmitting to the PCI bus.

Preferably, the reference value of the frame buffer is 1/2 of the capacity allocated to one storage area of the frame buffer. The frame buffer is also formed of SDRAM. The frame buffer divides each of the at least one storage area into two areas to buffer data in a ping-pong manner. The buffering controller may further include a plurality of video signal interface means for transmitting a signal for using the frame buffer, an address of a frame memory and a size of data to be transmitted, and transmitting data of a desired channel to the PCI interface unit. Video data reading means for reading the data by size, an SDRAM controller for controlling the frame buffer, a plurality of video signal interface means interworking with the frame buffer, and an SDRAM arbiter for arbitrating the video data reading means. . In addition, the video signal interface means extracts timing information from an input digital video signal, stores a timing information extraction module for determining the start of a frame, valid pixels determined through the timing information extraction module, and bursts a frame buffer. And a frame buffer addressing module configured to determine the start of a data frame based on the vertical sync and field signals extracted from the timing information extraction module and to synchronize the address of the frame buffer.

According to a second aspect of the present invention, a buffering controller receives a digital video signal through a plurality of channels, extracts information for data buffering, and controls a buffering process through a frame buffer; The PCI interface transmits a data transmission request signal to the PCI bus when data higher than a reference value is stored in the frame buffer, and reads the data stored in the frame buffer and transmits the data to the PCI bus when the data transmission acceptance signal is received from the PCI bus. It provides a PCI interface chip including a unit.

Preferably, the frame buffer is SDRAM. The buffering controller divides the frame memory into a plurality of storage regions respectively corresponding to the plurality of channels, and divides the digital video signal input through each of the plurality of channels into each of the plurality of channels among the plurality of storage regions. Store in the storage area corresponding to. The data above the reference value is 1/2 of the capacity of each of the plurality of storage areas. The buffering controller divides each of the plurality of storage areas into two areas to buffer data in a ping-pong manner.

According to a third aspect of the present invention, there is provided a method comprising: (A) buffering an input digital video signal in a storage area corresponding to each channel of a frame buffer according to a control signal of a buffering controller; (B) notifying the PCI interface unit when a channel in which data equal to or greater than a reference value is loaded is stored in the storage area of the frame buffer; (C) the PCI interface receiving the notification transmits a data transmission request signal to the PCI bus; (D) when receiving a data transmission acceptance signal from the PCI bus in response to the request signal, reading data stored in the frame buffer and transmitting the data to the PCI interface unit; And (E) transmitting the data from the PCI interface unit to the PCI bus.

Preferably, the step (D) further includes the step of buffering the data received from the frame buffer to the FIFO embedded in the PCI interface unit. In addition, the reference value is 1/2 of the storage area capacity. The frame buffer is also formed of SDRAM. In addition, the frame buffer divides the storage area into two areas to buffer data in a ping-pong manner.

DETAILED DESCRIPTION In order to fully understand the present invention, the advantages of the operability of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a block diagram illustrating a high performance video capture system of the present invention.

As shown in FIG. 4, the high performance video capture system is largely composed of three parts, the hardware 100, the device driver 200, and the application software 300. The hardware 100 converts an analog video signal into a digital video signal, buffers the converted digital video signal into a frame buffer (see reference numeral 140 in FIG. 5), and then uses a PCI bus (see reference numeral 170 in FIG. 7). To the main memory of your PC. The device driver 200 performs initialization, setting settings, and video capture of the hardware 100. The application software 300 reads and displays video data captured by the device driver 200 on a screen and processes various inputs of a user.

The present invention provides a high-speed data transmission scheme in capturing multi-channel data through the improvement of the hardware 100 among the components of the high speed video capture system. The conventional video capture system has been designed based on 1 channel, so there is no big problem even if the capacity of the internal buffer is small. However, in order to implement a high speed video capture system of 16 channels or more, it is necessary to implement a large frame buffer 140. Hereinafter, for convenience of description, the present invention will be described with reference to 16 channels. However, in defining the scope of the present invention, it is obvious that this is only a mere example. The system uses a large amount of SDRAM as the frame buffer 140 to implement real-time transmission of the captured video signal. In particular, by using the ping-pong technique in the buffering process, the data on the video decoder (refer to reference numeral 120 of FIG. 5) and the captured data do not overlap each other. This is because when the data overlap, frames may be overlapped in the case of a screen with heavy movement.

In addition, the performance of data capture is determined by how efficiently the PCI bus 170 is used. When the bandwidth of the PCI bus 170 is considered to be about 100 MBytes / sec, a capture performance of about 120 FPS (= 100 MBytes / sec / 24 MBytes / sec) can be realized. In order to maximize the bandwidth of the PCI bus 170, the arbitration of the PCI bus 170 should be reduced to the maximum and the bus size should be increased to the maximum. For this purpose, a buffer having a sufficient capacity is provided in the video capture card (refer to reference numeral 110 of FIG. 5) so that data to be transmitted is always prepared.

However, the FIFO inside the high-performance video capture card 110 (refer to reference numeral 151 of FIG. 7) is expensive SRAM, which is only 256 Bytes, which is not suitable for data buffering, and a large cost is required when the capacity is expanded. There is no way to use it. Hereinafter, the configuration of the video capture card 110 to satisfy the above conditions will be described in more detail with reference to FIGS. 5 to 8.

5 is a block diagram illustrating a video capture card of the present invention.

As shown in FIG. 5, the video capture card 110 extracts data for buffering the converted digital video signal, and a video decoder 120 for converting an analog video signal into a digital video signal. A buffering controller 130, a frame buffer 140 for buffering data according to the control signal of the buffering controller 130, and a FIFO embedded with video data stored in the frame buffer 140 (see reference numeral 151 of FIG. 7). And a PCI interface unit 150 for buffering and transmitting to the PCI bus (see reference numeral 170 of FIG. 7). The buffering control unit 130 and the PCI interface unit 150 may be manufactured as one chip.

The video decoder 120 receives an analog composite video base signal (CVBS) as an input, converts the digital signal into a digital signal, and outputs the digital signal. There are two types of output formats, in which digital video data and timing information (Vertical Sync, Horizontal Sync, Field, Blank) are separately transmitted and timing information is inserted between the digital video data. In the case in which the timing information is inserted, the number of pins of the buffering controller 130 can be saved, but there is a disadvantage in that additional logic is required to extract timing information from the buffering controller 130. The video decoder 120 may be an optional component and a digital signal may be directly input to the video capture card 110. The BT.656-format video data input to the buffering controller 130 is input to the buffering controller 130 in synchronization with a clock signal of 27 MHz. Of the data input to the buffering controller 130, all remaining data except for the vertical blanking and the horizontal blanking sections are transmitted to the frame buffer 140 as valid data. As an example, data of 720 pixels (= 720 x 2 Bytes / Pixel = 1440 Bytes) is continuously input except for a horizontal space in one line.

The buffering controller 130 generates a control signal for buffering the data converted into the digital signal through the video decoder 120 in the frame buffer 140, and temporarily stores the data buffered in the frame buffer 140. Transmission to the PCI interface unit 150. SDRAM may be used as the frame buffer 140. The SDRAM requires buffering because burst access improves performance. A 64-bit 128 depth FIFO (see 133 in FIG. 6) is used for buffering with SDRAM. A FIFO 133 of 64x128 size may be used per channel of the video signal. That is, a total of 18 FIFOs 133 are required, including 16 FIFOs 133 for the input channel and one FIFO 133 for reading the SDRAM.

Digital video data stored in the frame buffer 140 through the buffering control unit 130 is transmitted to the PCI interface unit 150 through a local bus 160 according to a request of the PCI interface unit 150. The data is transmitted from the PCI interface unit 150 to the PC system memory (see 400 in FIG. 7) through the PCI bus (see 170 in FIG. 7).

The process is summarized as an example of a signal input through one channel as follows. ① The analog video signal is converted into a digital video signal through the video decoder 120. ② The digitally converted video signal is divided into frames and input to the buffering controller 130, and is temporarily limited to the storage area A (see FIG. 8) of the frame buffer 140 according to a control signal of the buffering controller 130. Stored as. ③ When data equal to or greater than a reference value is stored in the storage area A of the frame buffer 140, the buffering controller 130 notifies the PCI interface unit 150 of the fact. (4) The buffering control unit 130 stops buffering in the saturated storage area A and sequentially stores data in the empty storage area B (see FIG. 8). That is, the frame buffer 140 divides one SDRAM into two regions or buffers data in a ping-pong format using two SDRAMs. The PCI interface unit 150 notified that the storage area A is saturated, requests the PCI bus 170 to transmit data. ⑥ When the accept signal is received from the PCI bus 170 in response to the request signal, the buffering controller 130 transmits the data saturated in the storage area A of the frame buffer 140 to the PCI interface unit 150. To pass. ⑦ The PCI interface unit 150 transmits the data received from the frame buffer 140 to the system memory 400 of the PC through the PCI bus 170. This will be described below in more detail with reference to FIG. 8.

6 is a block diagram illustrating in detail the configuration of the buffering control unit of the present invention.

Referring to FIG. 6, the buffering controller 130 includes 16 video signal interface means 131 including sub-modules of the timing information extraction module 132, the FIFO 133, and the frame buffer address setting module 134. A video data reading means 138, an SDRAM controller 136 for controlling the frame buffer 140, 16 video signal interface means 131 cooperating with the frame buffer 140, and one video And an SDRAM Arbiter 137 which mediates the data reading means 138.

In order for the multi-channel real-time video data and the capture of the host CPU to share the bandwidth of the frame buffer 140 in time division, the video data input in real time through a plurality of channels is efficiently applied to the frame buffer 140 through the buffering controller 130. Must be buffered. To this end, the timing information extraction module 132 is configured in ITU-R. Extract timing information (Horizontal Sync, Vertical Sync, Field, etc.) from the digital video signal input in 656 format, determine the start of the frame with reference to the Vertical Sync and Field signals, and determine the frame buffer. Reference is made to address generation of video data stored in 140. It also selects only effective pixels from video data captured at a resolution other than the maximum size.

The FIFO 133 has a depth of 128 bits x 64 bits and stores valid pixels determined by the timing information extraction module 132 and is used for buffering for burst access of the SDRAM. The FIFO 133 has a dual clock characteristic of operating at 27 Mhz, which is a clock of video data, and an output terminal of 133 Mhz, which is an operating frequency of the SDRAM. The FIFO 133 operates at 64 bits equal to the data bus width of the SDRAM. The depth of the FIFO 133 should be limited to an appropriate level due to the limited size of the internal memory of the buffering controller 130.

On the other hand, video data coming in real time should be stored in the position of the frame buffer 140 determined from the start of the frame. To this end, the frame buffer address setting module 134 determines the start of the frame from the timing information extraction module 132 based on the vertical sync and field signals, and synchronizes the address stored in the frame buffer 140 at this time. This address is maintained and maintained when video data is stored in the frame buffer 140.

On the other hand, when capturing a video signal of a specific channel desired, the address of the frame buffer 140 and the size to be transmitted to the PCI interface unit 150 are set, and the video data reading means 138 reads data of a predetermined size. Do this. The frame buffer address providing module 135 increases the address position of the frame buffer 140 and provides a start address of the next transmission.

The SDRAM controller 136 controls the SDRAM used as the frame buffer. The operating frequency of the SDRAM controller 136 is 133 Mhz and the data bus width is 64 bits. Meanwhile, the SDRAM arbiter 137 arbitrates 16 video signal interface means 131 and one video data read means 138 that interoperate with the frame buffer 140.

7 is a diagram illustrating a data transmission process between a frame buffer and a PC system memory through the PCI interface unit of the present invention.

Referring to FIG. 7, video data is temporarily stored in the storage area A (see FIG. 8) of the frame buffer 140 under the control of the buffering controller 130. When data equal to or greater than a reference value is stored in the storage area A of the frame buffer 140, the buffering controller 130 notifies the PCI interface unit 150 of the fact. The buffering control unit 130 stops buffering in the saturated storage area A and stores data successively in the empty storage area B. The PCI interface unit 150 notified that the storage area A is saturated, requests the PCI bus 170 to transmit data. When the permission for the request is obtained from the PCI bus 170, the buffering controller 130 transmits the data saturated in the storage area A of the frame buffer 140 through the local bus 160 to the PCI interface unit 150. To pass). The PCI interface unit 150 buffers the data received from the frame buffer 140 again through the FIFO 151 and transmits the data to the system memory 400 of the PC through the PCI bus 170.

8 is a diagram showing the structure of a frame buffer of the present invention.

Referring to FIG. 8, the frame buffer 140 includes 16 memory storage areas for loading 16 channels of video data, and A and B storage areas divided to alternately store data input for each channel for each frame. .

In order to store the YUV4: 2: 2 format data output from the video decoder 120, two bytes of storage space are required for one pixel. For example, in the case of PAL, the maximum resolution is defined as 720x576 pixels. The size of the memory for storing the maximum resolution PAL frame should be at least 720x576x2 = 829,440 Bytes. That is, the minimum space of each of the storage areas A and B for storing one frame of video data should be 829,440 Bytes or more capable of storing pixels having a resolution of 720x576.

On the other hand, each area provided with a storage space of the minimum size or more to store and read data using the ping-pong technique. In other words, read data from area B when data is written in area A so that data writing and reading does not occur simultaneously in two areas (A, B) separated for each channel. Read data from More specifically, if the data inputted at a rate of about 25 MBytes / sec (720x576x2 Bytes x 30 Frame / sec = 24883200 Bytes / sec) is buffered in the A area first, when the capacity of the A area is filled to a predetermined level or more, To save the data.

On the other hand, the frame buffer 140 is formed in a wafer different from the FIFO 133 in the buffering controller 130 is more advantageous in terms of yield.

Table 1 shows the results of measuring the maximum capture frame per second (FPS) for each resolution to confirm the actual performance of the video capture card described above.

Video format resolution FPS  NTSC 352 x 240 480 704x240 341 704x480 98  PAL 352 x 288 400 704x288 302 704x576 80

Referring to Table 1, capture performance of 30 FPS (480 total) for all 16 channels for NTSC 352x240 resolution and 25 FPS (400 FPS for all 16 channels) for PAL 352x288 resolution.

In addition, the capture performance of 341 FPS for NTSC 704x240 resolution and 302 FPS for PAL 704x288 resolution.

On the other hand, in NTSC 704x480 and PAL 704x576 mode, it is necessary to mix odd (ODD) and even (EVEN) fields to see normal images. Showed performance.

However, due to the effect of buffering using the frame buffer as a whole, it was confirmed that smooth multi-channel high-speed capture was achieved.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The present invention has the effect of providing a high-performance video capture card capable of high-speed frame capture by buffering the video frame using a buffering control unit and SDRAM.

Claims (16)

A buffering controller configured to receive digital video signals of at least one channel, extract information for data buffering, and control a buffering process; A frame buffer for buffering digital video data in at least one storage area corresponding to the at least one channel, respectively, according to a control signal of the buffering controller; And When data of more than a reference value is stored in one or more storage areas of the at least one storage area, the data transmission request signal is transmitted to the PCI bus, and when the data transmission acceptance signal is received from the PCI bus, the data stored in the frame buffer is read out. Video capture card including a PCI interface for transmitting to the PCI bus. The method of claim 1, And a reference value of the frame buffer is 1/2 of a capacity allocated to one storage area of the frame buffer. The method of claim 1, And the frame buffer is formed of SDRAM. The method of claim 1, And the frame buffer divides each of the at least one storage area into two areas to buffer data in a ping-pong manner. The method of claim 1, The buffering control unit A plurality of video signal interface means for transmitting signals for use of the frame buffer; Video data reading means for setting an address of a frame memory and a size of data to be transmitted to the PCI interface unit, and reading data of a desired channel by the transmission size; SDRAM controller for controlling the frame buffer, and And a plurality of video signal interface means interworking with the frame buffer, and an SDRAM arbiter for mediating the video data reading means. The method of claim 5, The video signal interface means A timing information extraction module for extracting timing information from an input digital video signal and determining the start of a frame; A FIFO for storing valid pixels determined through the timing information extraction module and for assisting burst access of the frame buffer; and And a frame buffer addressing module configured to determine the start of a data frame based on the vertical sync and field signals extracted from the timing information extraction module, and to synchronize the address of the frame buffer. A buffering controller configured to receive a digital video signal through a plurality of channels, extract information for data buffering, and control a buffering process through a frame buffer; The PCI interface transmits a data transmission request signal to the PCI bus when data higher than a reference value is stored in the frame buffer, and reads the data stored in the frame buffer and transmits the data to the PCI bus when the data transmission acceptance signal is received from the PCI bus. PCI interface chip containing a part. The method of claim 7, wherein The frame buffer is a PCI interface chip. The method of claim 7, wherein The buffering controller divides the frame memory into a plurality of storage regions respectively corresponding to the plurality of channels. And a digital video signal input through each of the plurality of channels in a storage area corresponding to each of the plurality of channels among the plurality of storage areas. The method of claim 9, And the data above the reference value is 1/2 of the capacity of each of the plurality of storage areas. The method of claim 9, The buffering controller divides each of the plurality of storage regions into two regions and buffers data in a ping-pong manner. (A) buffering the input digital video signal in a storage area corresponding to each channel of the frame buffer according to a control signal of the buffering controller; (B) notifying the PCI interface unit when a channel in which data equal to or greater than a reference value is loaded is stored in the storage area of the frame buffer; (C) the PCI interface receiving the notification transmits a data transmission request signal to the PCI bus; (D) when receiving a data transmission acceptance signal from the PCI bus in response to the request signal, reading data stored in the frame buffer and transmitting the data to the PCI interface unit; And (E) transmitting the data from the PCI interface unit to the PCI bus. The method of claim 12, The step (D) further comprises the step of buffering the data received from the frame buffer back to the FIFO embedded in the PCI interface unit. The method of claim 12, And the reference value is one half of the storage area capacity. The method of claim 12, And the frame buffer is formed of SDRAM. The method of claim 12, The frame buffer divides the storage area into two areas and buffers data in a ping-pong manner.

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