WO1996020446A1

WO1996020446A1 - Main memory system with multiple data paths

Info

Publication number: WO1996020446A1
Application number: PCT/US1995/016976
Authority: WO
Inventors: Brett L. Williams
Original assignee: Micron Technology, Inc.
Priority date: 1994-12-23
Filing date: 1995-12-22
Publication date: 1996-07-04
Also published as: JP2001523360A; JP2007328910A; KR100290495B1; JP3738314B2; JP2005011485A; KR100329944B1

Abstract

A system with a microprocessor has a main memory which is divided into a first burst access memory subsystem tightly coupled to a microprocessor data bus for optimum performance, and a second memory subsystem which is loosely coupled to the microprocessor through a data buffer to provide high memory capacity without heavily loading the microprocessor bus. The second memory subsystem may be burst access or page mode memory. A portion of the second memory subsystem may serve as a video frame buffer.

Description

Ϋ MAIN MEMORY SYSTEM WITH MULTIPLE DATA PATHS

FIELD QF THE INVENTION

This invention relates to microprocessor system architectures. In particular memory subsystem architectures, memory to microprocessor interface design, computer motherboard design and processor daughter board design. BACKGROUND OF THE INVENTION

As personal computers have become more advanced, they in turn have required faster and more dense memory devices, but with the same low cost of the standard DRAM. Fast page mode DRAMs are the most popular standard DRAM today. In fast page mode operation, a row address strobe (/RAS) is used to latch a row address portion of a multiplexed DRAM address. Multiple occurrences of the column address strobe (/CAS) each latch a column addresses to randomly access data within the selected row while /RAS is active. On the falling edge of /CAS an address is latched, and the DRAM outputs are enabled. When /CAS transitions high the DRAM outputs are placed in a high impedance state (tri-state). With advances in the production of integrated circuits, the internal circuitry of the DRAM operates faster than ever. This high speed circuitry has allowed for faster page mode cycle times. A problem exists in the reading of a DRAM when the device is operated with minimum fast page mode cycle times. /CAS may be low for as little as 15 nanoseconds, and the data access time from /CAS to valid output data (tCAC) may be up to 15 nanoseconds; therefore, in a worst case scenario there is no time to latch the output data external to the memory device. For devices that operate faster than the specifications require, the data may still only be valid for a few nanoseconds. On a heavily loaded microprocessor memory bus. trying to latch an asynchronous signal that is valid for only a few nanoseconds is very difficult. Even providing a new address every 35 nanoseconds requires large address drivers which create significant amounts of electrical noise within the system. To increase the data throughput of a memory system, it has been common practice to interleave multiple memory devices by placing them on a common bus. For example, two fast page mode DRAMs may be connected to common address and data buses. One DRAM stores data for odd addresses, and the other for even addresses. A disadvantage of this approach is the extra time required in a memory cycle for one memory device to turn off and then for another to turn on. Also, in order to achieve a particular data bandwidth, a minimum number of interleaved devices are required where the memory capacity requirements may be satisfied with fewer devices. There is a demand for faster, higher density, random access memory integrated circuits which provide a strategy for integration into today's personal computer systems. In an effort to meet this demand, numerous alternatives to the standard DRAM architecture have been proposed. One method of providing a longer period of time when data is valid at the outputs of a DRAM without increasing the fast page mode cycle time is called

Extended Data Out (EDO) mode. In an EDO DRAM the data lines are not tri-stated between read cycles in a fast page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low pulse occurs, or until /RAS or the output enable (/OE) goes high. Determining when valid data will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS falls, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by the various DRAM manufacturers. While EDO DRAM allows for higher frequency operation of the memory by providing a longer window of valid data output in a page mode operation, this very feature makes it largely incompatible with the interleaved memory architecture described above. Methods to further shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM)for example has an additional pin for receiving a system clock signal. Since the system clock is connected to each device in a memory system, it is highly loaded, and it is always toggling circuitry in every device. SDRAMs also have a clock enable pin, a chip select pin and a data mask pin. Other signals which appear to be similar in name to those found on standard DRAMs have dramatically different functionality on a SDRAM. The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.

In order for existing computer systems to use an improved device having a nonstandard pinout. those systems must be extensively modified. Additionally, existing computer system memory architectures are designed such that control and address signals may not be able to switch at the frequencies required to operate the new memory device at high speed due to large capacitive loads on the signal lines. The Single In-Line Memory Module (SIMM) provides an example of what has become an industry standard form of packaging memory in a computer system. On a SIMM, all address lines connect to all DRAMs. Further, the row address strobe (/RAS) and the write enable (/WE) are often connected to each DRAM on the SIMM. These lines inherently have high capacitive loads as a result of the number of device inputs driven by them. SIMM devices also typically ground the output enable (/OE) pin making /OE a less attractive candidate for providing extended functionality to the memory devices. There is a great degree of resistance to any proposed deviations from the standard SIMM design due to the vast number of computers which use SIMMs. Industry's resistance to radical deviations from the standard, and the inability of current systems to accommodate the new memory devices will delay their widespread acceptance. Therefore only limited quantities of devices with radically different architectures will be manufactured initially. This limited manufacture prevents the reduction in cost which typically can be accomplished through the manufacturing improvements and efficiencies associated with a high volume product.

A typical microprocessor system configuration such as might be found in a personal computer or workstation includes a microprocessor coupled to a memory controller and to a fast Static Random Access Memory (SRAM). A high capacity main memory is coupled to the microprocessor bus through the memory controller, address buffers and data buffers. The main memory is typically DRAM which combines a relatively high data bandwidth and random access, with high density data storage. The data buffers may be transceivers, registers, registered transceivers, latches, etc. The buffers provide a level of isolation which is required in order to limit the loading on the local microprocessor bus to levels that the microprocessor signal drivers can handle.

With the advent of multimedia devices and software applications, an increased number of peripheral devices have become widely available. For the purposes of this application, a peripheral may be but is not limited to an internal add in circuit board, or an external device in communication with a host system. These devices are also indirectly coupled to the microprocessor and main memory. These peripheral devices may include mass data storage devices such as CD ROM and magnetic hard drives; floppy disk drives; input/output ports for keyboard and mouse devices; sound cards; fax and modem devices; display devices; and others. Signal drive limitations dictate that not all of these peripheral subsystems be directly coupled together. Unfortunately, buffering, multiplexing and isolating the subsystems from the microprocessor bus causes delays which degrade system performance.

For maximum performance, the system resources most often required by the microprocessor should be the resources that the microprocessor can access with the least time delay. A primary factor in system performance is the microprocessor to memory interface bandwidth. For this reason, the memory subsystem is typically designed to be highly accessible while interface and peripheral devices are accessible via a system bus such as the PCI bus (Peripheral Component Interconnect), the VL bus (Video Electronics 5

Standards Association (VESA) Local Bus), or the ISA (Industry Standard Architecture) bus.

Microprocessors require instructions and data to perform system tasks. The instructions and data are stored in main memory which is typically DRAM. Instructions and data most frequently used by the microprocessor can be stored in an internal or external SRAM cache to significantly increase system performance. Cache memories provide fast access to data, but do not increase the memory capacity of the system since the data in the cache is a copy of data in main memory. Fast SRAM devices are unfortunately among the most costly memory devices for a given memory density. High cost and limited device densities prevent fast SRAMs from being used for most main memory applications. A relatively small amount of cache memory can significantly improve the performance of a conventional system due to a high probability that information required by the processor will be located in the cache. The increase in "hit rate" of a cache memory, however, tends to taper off well before the cache capacity approaches the main memory capacity, making large SRAM caches uneconomical. Though DRAM provides a more economical main memory solution, there is still a requirement for a substantial number of DRAM chips for optimal system performance. This in turn suggests that these chips be buffered from the microprocessor bus. This buffering, in combination with the relatively slow initial access time of DRAMs compared to SRAMs limits system performance.

There exists a need for a new system architecture which will improve the microprocessor to main memory bandwidth and eliminate the need for a SRAM cache in moderate to high performance systems and enhance performance in systems utilizing an SRAM cache. Improvements in main memory access times and bandwidth continue to improve performance of conventional system architectures. However, the ability of present system architectures to take advantage of these higher bandwidth memory devices is limited due to signal loading, buffer delays, and asynchronous timing between the memory and the microprocessor. There is additionally a need to provide 6/20446 __^-_n,_,

PCT/US9S/16976

6 increased memory bandwidth to system elements other than the microprocessor.

SUMMARY OF THE INVENTION An integrated circuit memory device with a standard DRAM pinout is designed for high speed data access and for compatibility with existing memory systems. A high speed burst mode of operation is provided where multiple sequential accesses occur following a single column address, and read data is output relative to the /CAS control signal. In the burst mode of operation the address is incremented internal to the device eliminating the need for external address lines to switch at high frequencies. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at high speeds. Only one control line per memory chip (/CAS) must toggle at the operating frequency in order to clock the internal address counter and the data input/output latches. The load on each /CAS is typically less than the load on the other control signals (/RAS, /WE and /OE) since each /CAS typically controls only a byte width of the data bus. Internal circuitry of the memory device is largely compatible with existing Extended Data Out (EDO) DRAMs. This similarity allows the two part types to be manufactured on one die with a limited amount of additional circuitry. The ability to switch between a standard non-burst mode and a high speed burst mode allows the device to be used to replace standard devices, and eliminates the need to switch to more complex high speed memory devices. Internal address generation provides for faster data access times than is possible with either fast page mode or EDO DRAMs. The high speed operation of this Burst EDO device eliminates the need to interleave memory devices in order to attain a high data throughput. In contrast to standard DRAM devices which may operate at 30 megahertz with data valid periods of only a few nanoseconds, this Burst EDO device can foreseeable operate at 100 megahertz with five nanosecond data valid periods. The device is compatible with existing memory module pinouts. Memory modules include, but are not limited to Single ln-Line Memory Modules (SIMMs), Multi-Chip Modules (MCMs) and Dual ln-Line Memory Modules (DIMMs). This combination of features allows for significant system performance improvements with a minimum of design alterations.

In one embodiment of the present invention, a new system architecture has a main memory which is divided into two main memory subsystems. A first portion of the main memory is made up of burst access DRAM which is tightly coupled to a microprocessor data bus for optimum performance, and a second portion of the main memory is loosely coupled to the microprocessor data bus through a data buffer. The tightly coupled portion provides the processor with high bandwidth, high density data and information storage which may be synchronized to the processor clock. The second portion provides additional memory capacity without a proportional increase in processor bus loading. In a preferred embodiment, both subsystems are removable providing for easy capacity/performance upgrades to the memory subsystems. In an alternate preferred embodiment, only the loosely coupled system is removable, and the tightly coupled system is mounted directly to a computer mother board providing controlled signal propagation characteristics for maximized performance.

The second portion may also provide higher bandwidth memory access to peripheral devices and subsystems. A portion of the second portion may be used for a display buffer which may require very high bandwidth data access for refreshing display information. In a preferred embodiment, a display buffer has access to the loosely coupled system while the microprocessor is accessing the tightly coupled system. In this embodiment there is little or no performance penalty associated with the location of the display frame buffer in main memory. Use of main memory for a display buffer eliminates the additional costs associated with a separate display buffer. The use of Video RAM in particular can add significantly to the cost of a computer system. Other benefits of a main memory display buffer include the flexibility of multiple display resolution options where memory that is not used for the display is available to the system as additional main memory.

The most often required information should be stored in the first main memory portion for rapid access by the microprocessor. For systems that ^{6 20446} PCIYUS95/16976

8 utilize a SRAM cache, the most frequently required information will be available to the microprocessor from the cache. In the event of a cache miss, the information will likely be available in the tightly coupled portion of the main memory. For the small percentage of time that information is required from the second portion of main memory, the performance penalty related to the loosely coupled nature of the second portion will not cause a significant reduction in overall system performance for most applications.

In a graphical user interface environment multiple applications may be open (the user has initiated operation of the application) concurrently. In some cases, an application may be operating in the background while another is operating in the foreground. For each application that is open, more main memory is required. In a preferred embodiment of the invention, the tightly coupled main memory is assigned the lowest main memory address space, with the loosely coupled memory assigned to a higher address space. For example, in a system having 144 megabytes of memory, the first 16 megabytes of main memory address space is directed to tightly coupled main memory, while the additional 128 megabytes is directed to loosely coupled main memory at higher address values. As the operating system allocates memory, the lower address memory is used first. If the user only opens a few applications, the application code and data may all be stored in the tightly coupled memory, and the system performance will be optimized in terms of speed. If the user opens up many applications, some application code may end up being located in the loosely coupled main memory. When the loosely coupled main memory is accessed by the microprocessor, the system may exhibit decreased performance, however, the flexibility of having many applications open simultaneously may outweigh the requirement to operate at maximum computational speed. This system provides the flexibility of a high memory capacity computer with the speed which may be achieved through the use of a limited tightly coupled main memory. The system allows for multiple types of memory being present in the system concurrently. The first tightly coupled portion of memory for example may be Burst EDO memory, while the second loosely coupled portion is EDO 9 memory. The memory controller is programmed to access the first portion in a Burst EDO format at a first access rate, and the second portion in an EDO format at a second access rate. This allows the user to have high memory capacity, and high speed access to at least a portion of the memory. The second portion of main memory may be further subdivided into multiple memory banks. A first bank of the second portion might be EDO memory which is primarily additional capacity for information that does not fit into the first tightly coupled portion. A second bank of the second portion might be Burst EDO memory which in addition to providing additional system memory capacity, is also used as a display frame buffer with sufficient bandwidth to support high resolution information displays. SDRAM or other burst access memory devices may also be used for the first memory portion.

The system on power up or reset can determine the type and amount of memory present in each memory bank, and adjust memory access signal timing parameters accordingly. Alternately, the user may be required to fill specific memory banks with specific types of memory. If a particular memory bank can be one of several types of memory the user has a greater ability to control the system price/performance characteristics by selecting the most economical and/or highest performance memory subsystem for his particular computer usage requirements.

BRIEF DESCRIPTION OF THE DRAWINGS The features of the invention as well as objects and advantages will be best understood by reference to the appended claims, detailed description of particular embodiments and accompanying drawings where: Figure 1 is an electrical schematic diagram of a Burst EDO memory device;

Figure 2 is a table showing linear versus interleaved addressing formats;

Figure 3 shows a preferred pinout for the device of figure 1 ; Figure 4 is a timing diagram for a method of accessing the device of figure 1 ; 10 Figure 5 is a further timing diagram for accessing the device of figure

1;

Figure 6 is an electrical schematic diagram of a Single ln-Line Memory Module; Figure 7 is a front view of another memory module utilizing the device of figure 1 ;

Figure 8 shows a preferred pinout for the memory module of figure 6; Figure 9 is a schematic diagram of a system designed in accordance with the present invention; Figure 10 is a schematic diagram of an alternate embodiment of a system designed in accordance with the present invention; and

Figure 11 is a timing diagram of a method of determining which type of memory is present in a system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 is a schematic representation of a sixteen megabit Burst access Extended Data Out Dynamic Random Access Memory (BEDO DRAM). The device is organized as a 2 Meg x 8 BEDO DRAM having an eight bit data input/output path 10 providing data storage for 2,097,152 bytes of information in the memory array 12. In a preferred embodiment the device of figure 1 has an industry standard pinout for eight bit wide EDO DRAMs. An active-low row address strobe (/RAS) signal 14 is used to latch a first portion of a multiplexed memory address, from address inputs 16. in latch 18. The latched row address 20 is decoded in row decoder 22. The decoded row address is used to select a row of the memory array 12. A column address strobe (/CAS) signal 24 is used to latch a second portion of a memory address from address inputs 16 into column address counter 26. The latched column address 28 is decoded in column address decoder 30. The decoded column address is used to select a column of the memory array 12.

In a burst read cycle, data within the memory array located at the row and column address selected by the row and column address decoders is read out of the memory array and sent along data path 32 to output latches 34. Data 10 driven from the burst EDO DRAM may be latched external to the 1 1 device in synchronization with /CAS after a predetermined number of /CAS cycle delays (latency). For a two cycle latency design, the first /CAS falling edge is used to latch the initial address for the burst access. The first burst data from the memory is driven from the memory after the second /CAS falling edge, and remains valid through the third /CAS falling edge. Once the memory device begins to output data in a burst read cycle, the output drivers 34 will continue to drive the data lines without tri-stating the data outputs during /CAS high intervals dependent on the state of the output enable 42 and write enable 36 (/OE and /WE) control lines, thus allowing additional time for the system to latch the output data. Once a row and a column address are selected, additional transitions of the /CAS signal are used to advance the column address within the column address counter in a predetermined sequence. The time at which data will be valid at the outputs of the burst EDO DRAM is dependent only on the timing of the /CAS signal provided that /OE is maintained low, and /WE remains high. The output data signal levels may be driven in accordance with, but is not limited to, standard CMOS, TTL, LVTTL, GTL, or HSTL output level specifications.

The address may be advanced linearly, or in an interleaved fashion for maximum compatibility with the overall system requirements. Figure 2 is a table which shows linear and interleaved addressing sequences for burst lengths of 2, 4 and 8 cycles. The "V" for starting addresses Al and A2 in the table represent address values that remain unaltered through the burst sequence. The column address may be advanced with each /CAS transition, each pulse, or multiple of /CAS pulses in the event that more than one data word is read from the array with each column address. When the address is advanced with each transition of the /CAS signal, data is also driven from the part after each transition following the device latency which is then referenced to each edge of the /CAS signal. This allows for a burst access cycle where the highest switching control line (/CAS) toggles only once (high to low or low to high) for each memory cycle. This is in contrast to standard DRAMs which require /CAS to go low and then high for each cycle, and synchronous DRAMs which require a full clock cycle (high and low transitions) for each 12 memory cycle. For maximum compatibility with existing EDO DRAM devices, the invention will be further described in reference to a device designed to latch and advance a column address on falling edges of the /CAS signal. It may be desirable to latch and increment the column address after the first /CAS falling edge in order to apply both the latched and incremented addresses to the array at the earliest opportunity in an access cycle. For example, a device may be designed to access two data words per cycle (prefetch architecture). The memory array for a prefetch architecture device may be split into odd and even array halves. The column address least significant bit is then used to select between odd and even halves while the other column address bits select a column within each of the array halves. In an interleaved access mode with column address 1, data from columns 0 and 1 would be read and the data from column 1 would be output followed by the data from column 0 in accordance with standard interleaved addressing as described in SDRAM specifications. In a linear access mode column address 1 would be applied to the odd array half, and incremented to address 2 for accessing the even array half to fulfill the two word access. One method of implementing this type of device architecture is to provide a column address incrementing circuit between the column address counter and the even array half. The incrementing circuit would increment the column address only if the initial column address in a burst access cycle is odd, and the address mode is linear. Otherwise the incrementing circuit would pass the column address unaltered. For a design using a prefetch of two data accesses per cycle, the column address would be advanced once for every two active edges of the /CAS signal. Prefetch architectures where more than two data words are accessed are also possible.

Other memory architectures applicable to the current invention include a pipelined architecture where memory accesses are performed sequentially, but each access may require more than a single cycle to complete. In a pipelined architecture the overall throughput of the memory will approach one 13 access per cycle, but the data out of the memory may be offset by a number of cycles due to the pipeline length and/or the desired latency from /CAS.

In the burst access memory device, each new column address from the column address counter is decoded and is used to access additional data within the memory array without the requirement of additional column addresses being specified on the address inputs 16. This burst sequence of data will continue for each /CAS falling edge until a predetermined number of data accesses equal to the burst length has occurred. A /CAS falling edge received after the last burst address has been generated will latch another column address from the address inputs 16 and a new burst sequence will begin. Read data is latched and output with each falling edge of /CAS after the first /CAS latency.

For a burst write cycle, data 10 is latched in input data latches 34. Data targeted at the first address specified by the row and column addresses is latched with the /CAS signal when the first column address is latched (write cycle data latency is zero). Other write cycle data latency values are possible; however, for today's memory systems, zero is preferred. Additional input data words for storage at incremented column address locations are latched by /CAS on successive /CAS pulses. Input data from the input latches 34 is passed along data path 32 to the memory array where it is stored at the location selected by the row and column address decoders. As in the burst read cycle previously described, a predetermined number of burst access writes will occur without the requirement of additional column addresses being provided on the address lines 16. After the predetermined number of burst writes has occurred, a subsequent /CAS pulse will latch a new beginning column address, and another burst read or write access will begin.

The memory device of figure 1 may include the option of switching between burst EDO and standard EDO modes of operation. In this case, the write enable signal /WE 36 may be used at the row address latch time (/RAS falling, /CAS high) to determine whether memory accesses for that row will be burst or page mode cycles. If /WE is low when /RAS falls, burst access cycles are selected. If /WE is high at /RAS falling, standard extended data 14 out (EDO) page mode cycles are selected. Both the burst and EDO page mode cycles allow for increased memory device operating frequencies by not requiring the data output drivers 34 to place the data lines 10 in a high impedance state between data read cycles while /RAS is low. DRAM control circuitry 38, in addition to performing standard DRAM control functions, controls the I/O circuitry 34 and the column address counter/latch 26 in accordance with the mode selected by /WE when /RAS falls. In a burst mode only DRAM, or in a device designed with an alternate method of switching between burst and non-burst access cycles, the state of /WE when /RAS falls may be used to switch between other possible modes of operation such as interleaved versus linear addressing modes. Alternately, /WE may be a "don't care" if the state of /WE at /RAS falling is not used to select a mode of operation.

The write enable signal is used in burst access cycles to select read or write burst accesses when the initial column address for a burst cycle is latched by /CAS. /WE low at the column address latch time selects a burst write access. /WE high at the column address latch time selects a burst read access. The level of the /WE signal must remain high for read and low for write burst accesses throughout the burst access. A low to high transition within a burst write access will terminate the burst access, preventing further writes from occurring. A high to low transition on /WE within a burst read access will likewise terminate the burst read access and will place the data output 10 in a high impedance state. Transitions of the /WE signal may be locked out during critical timing periods within an access cycle in order to reduce the possibility of triggering a false write cycle. After the critical timing period the state of /WE will determine whether a burst access continues, is initiated, or is terminated. Termination of a burst access resets the burst length counter and places the DRAM in a state to receive another burst access command. Both /RAS and /CAS going high during a burst access will also terminate the burst access cycle placing the data drivers in a high impedance output state, and resetting the burst length counter. Read data may remain valid at the device outputs if /RAS alone goes high while /CAS is 15 active for compatibility with hidden refresh cycles, otherwise /RAS high alone may be used to terminate a burst access. A minimum write enable pulse width is only required when it is desired to terminate a burst read and then begin another burst read, or terminate a burst write prior to performing another burst write with a minimum delay between burst accesses. In the case of burst reads, /WE will transition from high to low to terminate a first burst read, and then /WE will transition back high prior to the next falling edge of /CAS in order to specify a new burst read cycle. For burst writes, /WE would transition high to terminate a current burst write access, then back low prior to the next falling edge of /CAS to initiate another burst write access.

A basic implementation of the device of figure 1 may include a fixed burst length of 4, a fixed /CAS latency of 2 and a fixed interleaved sequence of burst addresses. This basic implementation requires very little additional circuitry to the standard EDO page mode DRAM, and may be mass produced to provide the functions of both the standard EDO page mode and burst EDO DRAMs. This device also allows for the output enable pin (/OE) to be grounded for compatibility with many SIMM module designs. When not disabled (tied to ground), /OE is an asynchronous control which will prevent data from being driven from the part in a read cycle if it is inactive (high) prior to /CAS falling and remains inactive beyond /CAS rising. If these setup and hold conditions are not met, then the read data may be driven for a portion of the read cycle. It is possible to synchronize the /OE signal with /CAS, however this would typically increase the /CAS to data valid delay time and doesn't allow for the read data to be disabled prior to /RAS high without an additional /CAS low pulse which would otherwise be unnecessary. In a preferred embodiment, if /OE transitions high at any time during a read cycle the outputs will remain in a high impedance state until the next falling edge of /CAS despite further transitions of the /OE signal.

Programmability of the burst length, /CAS latency and address sequences may be accomplished through the use of a mode register 40 which latches the state of one or more of the address input signals 16 or data signals 10 upon receipt of a write-/CAS-before-/RAS (WCBR) programming cycle. 16

In such a device, outputs 44 from the mode register control the required circuits on the DRAM. Burst length options of 2, 4, 8 and full page as well as /CAS latencies of 1, 2 and 3 may be provided. Other burst length and latency options may be provided as the operating speeds of the device increase, and computer architectures evolve. A preferred embodiment of the device of figure 1 provides programmability of the address sequence by latching the state of the least significant address bit during a WCBR cycle with the burst length and /CAS latency for this particular embodiment being fixed. Other possible alterations in the feature sets of this DRAM include having a fixed burst mode only, selecting between standard fast page mode (non-EDO) and burst mode, and using the output enable pin (/OE) 42 in combination with /RAS to select between modes of operation. Also, a WCBR refresh cycle could be used to select the mode of operation rather than a control signal in combination with /RAS. A more complex memory device may provide additional modes of operation such as switching between fast page mode, EDO page mode, static column mode and burst operation through the use of various combinations of /WE and /OE at /RAS falling time. One mode from a similar set of modes may be selected through the use of a WCBR cycle using multiple address or data lines to encode the desired mode. Alternately, a device with multiple modes of operation may have wire bond locations, programmable fuses, or nonvolatile memory elements which may be used to program the mode of operation of the device.

A preferred embodiment of a sixteen bit wide burst EDO mode DRAM designed in accordance with the teachings of this invention has two column address strobe input pins /CASH and /CASL. For read cycles only one /CAS signal needs to toggle. The second /CAS may remain high or toggle with the other /CAS. During burst read cycles, all sixteen data bits will be driven out of part during a read cycle even if one /CAS remains inactive. In a typical system application, a microprocessor reads all data bits on a data bus in each read cycle, but may only write certain bytes of data in a write cycle.

Allowing one of the /CAS control signals to remain static during read cycles helps to reduce overall power consumption and noise within the system. For 17 burst write access cycles, each of the /CAS signals (CASH and /CASL) acts as a write enable for an eight bit width of the data. The two /CAS's are combined in an AND function to provide a single internal /CAS which will go low when the first external /CAS falls, and returns high after the last external /CAS goes high. All sixteen data inputs are latched when the first of the /CAS signals transitions low. If only one /CAS signal transitions low, then the eight bits of data associated with the /CAS that remained high are not stored in the memory.

The present invention has been described with reference to several preferred embodiments. Just as fast page mode DRAMs and EDO DRAMs are available in numerous configurations including xl, x4, x8 and xl6 data widths, and 1 Megabit. 4 Megabit, 16 Megabit and 64 Megabit densities; the memory device of the present invention may take the form of many different memory organizations. It is believed that one who is skilled in the art of integrated circuit memory design can, with the aide of this specification design a variety of memory devices which do not depart from the spirit of this invention. It is therefore believed that detailed descriptions of the various memory device organizations applicable to this invention are not necessary. A preferred pinout for the Burst EDO memory device is shown in figure 3. It should be noted that the pinout may be identical to the pinout for a standard EDO DRAM. The common pinout allows this new device to be used in existing memory designs with minimum design changes. The common pinout also allows for ease of new designs by those of skill in the art who are familiar with the standard EDO DRAM pinout. Variations of the described invention which maintain the standard EDO DRAM pinout include driving the /CAS pin with a system clock signal to synchronize data access of the memory device with the system clock. For this embodiment, it may be desirable to use the first /CAS active edge after /RAS falls to latch the row address, a later edge may be used to latch the first column address of a burst access cycle. After row and column addresses are latched within the device, the address may be incremented internally to provide burst access cycles in synchronization with the system clock. Other pin function alternatives include 18 driving the burst address incrementing signal on the /OE pin since the part does not require a data output disable function on this pin. Other alternate uses of the /OE pin also allow the device to maintain the standard EDO pinout, but provide increased functionality such as burst mode access. The /OE pin may be used to signal the presence of a valid column starting address, or to terminate a burst access. Each of these embodiments provides for a high speed burst access memory device which may be used in current memory systems with a minimum amount of redesign.

Figure 4 is a timing diagram for performing a burst read followed by a burst write of the device of figure 1. In figure 4, a row address is latched by the /RAS signal. /WE is low when /RAS falls for an embodiment of the design where the state of the /WE pin is used to specify a burst access cycle at /RAS time. Next, /CAS is driven low with /WE high to initiate a burst read access, and the column address is latched. The data out signals (DQ's) are not driven in the first /CAS cycle. On the second falling edge of the /CAS signal, the internal address generation circuitry advances the column address and begins another access of the array, and the first data out is driven from the device after a /CAS to data access time (tCAC). Additional burst access cycles continue, for a device with a specified burst length of four, until the fifth falling edge of /CAS which latches a new column address for a new burst read access. /WE falling in the fifth /CAS cycle terminates the burst access, and initializes the device for additional burst accesses. The sixth falling edge of /CAS with /WE low is used to latch a new burst address, latch input data and begin a burst write access of the device. Additional data values are latched on successive /CAS falling edges until the burst access is terminated.

Figure 5 is a timing diagram depicting burst write access cycles followed by burst read cycles. As in figure 4, the /RAS signal is used to latch the row address, however, for this embodiment of the invention /WE is a don't care at /RAS falling time. The first /CAS falling edge in combination with /WE low begins a burst write access with the first data being latched. Additional data values are latched with successive /CAS falling edges, and the PCMJS95/16976

19 memory address is advanced internal to the device in either an interleaved or sequential manner. On the fifth /CAS falling edge a new column address and associated write data are latched. The burst write access cycles continue until the /WE signal goes high in the sixth /CAS cycle. The transition of the /WE signal terminates the burst write access. The seventh /CAS low transition latches a new column address and begins a burst read access (/WE is high). The burst read continues until the burst access is terminated.

It should be noted from figure's 4 and 5, that for burst read cycles the data remains valid on the device outputs as long as the /OE pin is low, except for brief periods of data transition. Also, since the /WE pin is low prior to or when /CAS falls, the data input/output lines are not driven from the part during write cycles, and the /OE pin is a "don't care". Only the /CAS signal and the data signals toggle at relatively high frequency, and no control signals other than /CAS are required to be in an active or inactive state for one /CAS cycle time or less. This is in contrast to SDRAMs which often require row address strobes, column address strobes, data mask, and read/write control signals to be valid for one clock cycle or less for various device functions. Typical DRAMs also allow for the column address to propagate through to the array to begin a data access prior to /CAS falling. This is done to provide fast data access from /CAS falling if the address has been valid for a sufficient period of time prior to /CAS falling for the data to have been accessed from the array. In these designs an address transition detection circuit is used to restart the memory access if the column address changes prior to /CAS falling. This method actually requires additional time for performing a memory access since it must allow for a period of time at the beginning of each memory cycle after the last address transition to prepare for a new column address. Changes in the column address just prior to /CAS falling may increase the access time by approximately five nanoseconds. An embodiment of the present invention will not allow the column address to propagate through to the array until after /CAS has fallen. This eliminates the need for address transition detection circuitry, and allows for a fixed array access relative to /CAS. While the column address may be prohibited from propagating through to the array until a falling /CAS transition, the counter may be advanced on rising /CAS edges to provide a valid column address in preparation for the next falling /CAS edge.

Figure 6 is a schematic representation of a single in-line memory module (SIMM) designed in accordance with the present invention. The SIMM has a standard SIMM module pinout for physical compatibility with existing systems and sockets. Functional compatibility with EDO page mode SIMMs is maintained when each of the 2 Meg x 8 memory devices 10, 12, 14 and 16 are operated in an EDO page mode. Each of the /CAS signals 18, 20, 22 and 24 control one byte width of the 32 bit data bus 26, 28, 30 and 32. A /RAS 34 signal is used to latch a row address in each of the memory devices, and may be used in combination with /WE 36 to select between page mode and burst mode access cycles for devices capable of operating in both of these modes. Address signals 38 provide a multiplexed row and column address to each memory device on the SIMM. In burst mode, only active /CAS control lines are required to toggle at the operating frequency of the device, or at half the frequency if each edge of the /CAS signal is used as described above. The data lines are required to be switchable at half of the frequency of the /CAS lines or at the same frequency, and the other control and address signals switch at lower frequencies than /CAS and the data lines. As shown in figure 6, each /CAS signal and each data line is connected to a single memory device allowing for higher frequency switching than the other control and address signals. Each of the memory devices 10, 12, 14 and 16 is designed in accordance with the present invention allowing for a burst mode of operation providing internal address generation for sequential or interleaved data access from multiple memory address locations with timing relative to the /CAS control lines after a first row and column address are latched.

Figure 7 shows a front view of another SIMM designed in accordance with the present invention. Each device on the SIMM is a 4 Megabit DRAM organized as 1 Meg x 4. In this configuration, a single /CAS controls two memory devices to provide access to a byte width of the data bus. The eight devices shown form a 4 Megabyte SIMM in a 32 bit width. For an 8 21

Megabyte SIMM in a 32 bit width, there are eight additional devices on the back side (not shown).

Figure 8 shows a preferred pinout for a memory module designed in accordance with the device of figure 7. This pinout is compatible with pinouts for Fast Page Mode SIMMs and EDO SIMMs. A presence detect pin is provided for indication of EDO operation on pin 66, and in accordance with standard EDO part types, an /OE input is provided on pin 46.

Alternate embodiments of the SIMM modules of figure's 6,7 and 8 include the use of two /RAS signals with each controlling a sixteen bit width of the data bus in accordance with standard SIMM module pinouts. Four more 2M x 8 EDO Burst Mode DRAMs may be added to the device of figure 6 to provide for a 4M x 32 bit SIMM. Sixteen bit wide DRAMs may also be used, these will typically have two /CAS signals each of which controls an eight bit data width. The incorporation of parity bits, or error detection and correction circuitry provide other possible SIMM module configurations. Methods of performing error detection and/or correction are well known to those of skill in the art, and detailed descriptions of such circuits are not provided in this application. Additional SIMM designs using the novel memory device of the present invention may be designed by one of skill in the art with the aid of this specification. The invention has been described with reference to SIMM designs, but is not limited to SIMMs. The invention is equally applicable to other types of memory modules including Dual ln- Line Memory Modules (DIMMs) and Multi-Chip Modules (MCMs).

Figure 9 is a schematic representation of a data processing apparatus designed in accordance with the present invention. For the purposes of this specification a microprocessor may be. but is not limited to, a microprocessor, a microcontroller, a digital signal processor, or an arithmetic processor, or a central processing unit (CPU). In figure 9, microprocessor 1 12 is connected to microprocessor local bus 114 comprised of address and control signals 1 16 and data signals 1 18. The microprocessor has access to a number of resources through timing and control circuitry 120. For example, the timing and control circuit receives address and control signals from the 22 microprocessor, and provides control signals to static random access memory cache 117, tightly coupled noncaching Burst access DRAM 119 and loosely coupled DRAM 132.

Microprocessor memory access speed and memory bandwidth are critical parameters for microprocessor system performance. To maximize these parameters, when an SRAM cache is utilized, it is typically connected to the microprocessor local bus 114 without intermediate data buffers or latches. Main memory which is typically DRAM is required to provide large amounts of data storage capacity. Since the microprocessor will have limited bus drive capabilities, a main memory made up of more than a few memory chips is required to be isolated from the microprocessor through address and data buffers. In the system of figure 9, the microprocessor address bus is coupled to the loosely coupled main memory 132 through control circuitry 120, and optionally through additional buffers 130. Typically, microprocessor command and address signals will need to be reformatted within control circuitry 120. Some or all of the reformatted address and control signals (126 for the loosely coupled memory and 127 for the tightly coupled memory )may also require buffering through buffer 130 to drive the load of the associated memory. Buffered address and control signals for the loosely coupled memory are shown as signals 128. An example of the address reformatting required within control circuitry 120 is multiplexing a 32 bit address from the microprocessor down to a 12 bit row and a 12 bit column address over a 12 bit multiplexed address bus for a 16 megabyte loosely coupled memory. Reformatting of the control signals includes generation of /RAS and /CAS in response to a memory access request from the microprocessor.

Microprocessor data bus 118 is coupled to the loosely coupled main memory data bus 134 through data transceivers 136. A data transceiver is a bi¬ directional data buffer, which allows memory data to be transferred both to and from the microprocessor. A tightly coupled noncache portion of main memory 119 is more directly coupled to the microprocessor for high speed data transfers. Microprocessor address and control signals are coupled to the tightly coupled main memory through the control circuitry which in a 23 preferred embodiment provides multiplexed address signals and memory specific timing control signals 127 to the tightly coupled main memory. Again, additional buffers between the control circuitry and the tightly coupled memory may be added to reduce the loading on the control circuitry, but are not preferred since they may cause additional delay. In a preferred embodiment, the tightly coupled memory is made up of eight 2 Meg x 8 Burst EDO DRAMs which are soldered to a circuit board which is common with the microprocessor. The number of memory circuits may be other than eight, but will preferably provide a data width equal to the processor data width, in this case a 64 bit data bus width. Likewise, SDRAM or other burst access memory devices may be utilized in place of Burst EDO DRAMs. A system with a limited number of memory circuits directly connected to a system circuit board in this manner will provide a high performance memory to microprocessor interface. If the system is designed to accept multiple configurations of tightly coupled memory, the maximum performance of the memory interface may have to be degraded to allow for variations in bus loading and signal noise. After an initial access delay, the Burst EDO DRAM can provide the microprocessor with data each clock cycle during a burst access. This is in contrast to the loosely coupled main memory which will typically require idle clock cycles (wait states) between data accesses in a page mode operation.

The control circuitry 120 further provides the microprocessor with access to other system components located on a local system bus 140. Local bus 140 may be a PCI bus (Peripheral Component Interconnect), a VL Bus( Video Electronics Standards Association (VESA) Local Bus), or an architectural equivalent. The VL bus has found primary use in computers utilizing the Intel 486 generation microprocessor. The PCI bus is primarily used in Intel Pentium class microprocessors, although it may also become widely used in computers utilizing the IBM PowerPC microprocessor. Likewise, computers which utilize future generations of microprocessors will likely have new local bus standards which do not depart from the scope and spirit of the current inventive architecture. The local bus has access to the 24 loosely coupled main memory through the control circuitry 120 and an additional set of data transceivers 138. Control circuitry 120 may also control access of the tightly coupled memory from peripheral devices via the local system bus 140. Additional control circuitry 150 may be utilized to provide an interface to an ISA (Industry Standard Architecture) bus 154. This bus provides compatibility with previous generations of computers and peripherals designed for them. Additional peripheral devices 152 such as a keyboard, mouse, CD ROM Drive, Floppy Disk Drive, Hard Drive, etc. may also interface to the local bus through control circuitry 150. Computer add in cards 158 designed according to the ISA bus interface are accessed by the microprocessor, or have access to system resources through the ISA bus. BIOS (Basic Input Output System) ROM 156 may also be accessed via the ISA bus. Interface signals 148 control access of the PCI bus by devices on the ISA bus, and other peripheral devices. A video frame buffer card 144 is commonly interfaced to the local bus for increased system performance as display buffer bandwidth continues to increase. Other PCI cards 146 may be present on the PCI bus. In this system architecture, the system components which are most often accessed by the microprocessor are located on the microprocessor local bus to provide high overall system performance. Other frequently accessed devices such as the video buffer are accessed via the local system bus. Finally, devices which have slow access times, and/or which may be less critical to the overall system performance are located on the ISA bus. The local bus and the ISA bus will typically be integrated into a system mother board. While the processor, cache memory and main memory are also typically located on the system mother board, it is possible for some or all of these system components to be located on a daughter board in order to provide an easy performance upgrade by replacing the daughter board with a higher performance processor subsystem. Multiple processor systems are also possible where in a preferred embodiment each processor has its own tightly coupled main memory subsystem and either its own loosely coupled memory subsystem, or a shared loosely coupled memory subsystem. 25

In operation, when a tightly coupled Burst EDO main memory portion is present, the microprocessor reads data by supplying address and control signals to the memory through the memory control circuit. In response to an initial address, a read command and an access cycle strobe, the memory begins to access a first data word at the initial address. A second access cycle strobe advances the address within the memory in a second access period of the burst access, and initiates a read access of data from a second address. For a latency of two. the first data is driven from the memory after the second access cycle strobe signal occurs. Typically the first data is latched in the microprocessor in response to a third access cycle strobe which occurs at the beginning of a third access cycle period of the burst access. The third access cycle strobe also causes the second data value to be driven from the memory. The third access cycle strobe also causes a third address to be generated within the memory, and a third data access begins. Burst data is latched in the microprocessor in response to the third, fourth, fifth and sixth access cycle strobes for a four word burst access. In this manner four data values are received in the microprocessor in response to a single address and a plurality of access cycle strobes. The microprocessor may provide a second address to the memory with the fifth access cycle strobe signal if the memory is designed to perform four word burst sequences and additional data values are required from the memory. In this case, a second four word burst sequence is begun while the microprocessor is receiving data from the first four word burst. The relationship of the burst access to a 66 megahertz system clock may be for example: 1st cycle, latch address and control information in the control circuitry 120; 2nd cycle, generate a row address and a /RAS signal for the tightly coupled memory on signal lines 127; 3rd cycle, generate column address on lines 127; 4th cycle, generate first access cycle strobe on 127; 5th cycle, generate second access cycle strobe on 127; 6th cycle, generate third access cycle strobe and latch first data value in the microprocessor over 1 18; successive cycles, generate access cycle strobe and latch data in the microprocessor. For four word burst accesses, the timing may be described as being 6-1-1-1 where the first data value is latched after six system clock 26 cycles, and the three successive data values are latched on successive system clock cycles. A typical SRAM cache in contrast may supply data in a 3-1-1-1 sequence. The size limitations of a SRAM cache will typically limit cache hits to approximately 80%, while a relatively large tightly coupled memory may provide close to a 100% hit rate. For a system without tightly coupled memory, a cache miss will typically result in a 7-2-2-2 access sequence from the loosely coupled memory. A loosely coupled main memory alone will have a 100% hit rate, and provide an average access cycle time of (7+2+2+2)/4=3.25 system clock cycles. A tightly coupled main memory with a 100% hit rate will provide an average access cycle time of 9/4=2.25 system clock cycles. Likewise, it can be seen that a system having a SRAM cache with a loosely coupled main memory will have an average access cycle time of [(.8x6) + (.2xl3)]/4 = 1.85 system clock cycles. Finally, a tightly coupled system with a SRAM cache will have an average access time of 1.65 system clock cycles for an 80% cache hit rate and a 20% tightly coupled memory hit rate. These values represent both read and write access times for the SRAM cache and for loosely coupled main memory. Tightly coupled Burst EDO memory write cycles will however be faster since there will typically be no latency relative to the access cycle signal. This translates into a 4-1-1-1 write cycle sequence for tightly coupled memory burst writes. Incorporation of a tightly coupled main memory provides for medium to high performance systems without the use of a SRAM cache, or very high performance with a SRAM cache.

The Burst EDO memory devices of the present invention are particularly well suited for use in a tightly coupled main memory application since they can operate with shorter cycle times than conventional DRAMs. Placing a conventional DRAM memory directly on the processor bus would be of little benefit since the cycle times would be long enough (likely two system clock cycles) that the addition of a data buffer would not add significantly to the access times, while the absence of the data buffers will load the processor data bus. The Burst EDO DRAMs on the other hand may not be able to operate in a 6-1-1-1 access sequence for example, at relatively PCI7US95/16976

27 high clock frequencies if a data buffer is included since the delay of the buffer is a more substantial percentage of a minimum cycle time.

In a preferred embodiment of the present invention, the loosely coupled memory 132 of Fig. 9 will operate with one of two or more different types of memory. For example, the memory may be made up of Burst EDO, Fast Page Mode, or EDO memory devices. The system for example, may be adapted to receive memory modules having Fast Page Mode, EDO or Burst EDO memory devices where the modules have identical or nearly identical pinouts to allow expansion of the system to add or upgrade the loosely coupled memory.

Flash memory and SDRAM memory are also suitable for use in the loosely coupled memory, however they would typically not be interchangeable with other types of memory devices, and would therefore provide a more limited variety of system configurations. Flash memory in particular may be beneficial for use in portable computers where it has certain performance advantages over magnetic hard disk drive technologies. In this configuration, a loosely coupled nonvolatile memory bank can perform the functions of an internal solid state hard drive where available memory (not required as disk space) can act as a lower performance random access memory expansion to the high performance tightly coupled memory subsystem.

Figure 10 is a schematic diagram of an alternate embodiment of the current invention. Elements which may have common function and description with elements of figure 9 are numbered accordingly. In figure 10, loosely coupled main memory 132 has memory data bus 134 coupled to control circuitry 120 which provides data path control and buffering from the loosely coupled memory to a CPU 112 over a processor bus 114. Control circuitry 120 also provides access to the loosely coupled main memory from other system components over system bus 140. Display device 160 is also explicitly shown in figure 10 coupled to a video control circuit 144 which may include a display frame buffer. The display device may be, but is not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), or a field emission display (FED). 28

Figure 11 is a timing diagram of a method of determining which type of memory is present in a system, in accordance with the teachings of this invention. For the purposes of providing a specific example, the data values shown correspond to a system where the data width is four bits. In practice, a typical system data bus may have 8, 16, 32, 64 or some other data width. Likewise while the timing diagram may be viewed with reference to the system of figure 9, the method described is equally useful for a wide variety of system configurations in accordance with the teachings of the present invention which are capable of utilizing memory devices which may operate in one or more of at least two different access modes. In figure 11, two data values are written into memory using a page mode write format. This format will correctly store data into Fast Page Mode. EDO, or Burst EDO memory devices. If the memory is Burst EDO, the second column address presented (Cn+1) will simply be ignored by the memory device or devices being written to since the second address will be internally generated. After writing the two data values (0110 and 1001) which should be chosen to be easily distinguishable from each other and from a bus that is not driven, the memory is read in a Burst EDO format. The waveform labeled DATA FPM is a representation of the data bus for a system where the memory is operating in a Fast Page Mode. The waveform labeled DATA EDO is a representation of the data bus for a system where the memory is operating in an EDO mode. The waveform labeled DATA BEDO is a representation of the data bus for a system where the memory is operating in a Burst EDO mode. The vertical lines tl, t2, t3, t4 and t5 represent some possible times when data may be sampled in order to differentiate between the possible types of memory present in the system. At time t5 in particular, each memory type provides a different response to the read operation. Fast Page Mode memory will not be driving the data bus at time t5 since /CAS is high. When the bus is not driven, it will typically float or be terminated to a level that will be digitally interpreted as being either high, low, or a pattern of high and low values. In any case the data is not likely to match the pattern written. For systems utilizing a narrow data bus, or if the bus characteristics are unknown, it may 29 be desirable to repeat the method with various data patterns to guarantee that the bus is not tending to provide signal levels that would be interpreted as a match of the data that was written. For wide data buses, the likelihood of an undriven bus matching a random or suitably varying pattern of data bits is very remote, and multiple patterns may not be deemed necessary. A possible pattern for a 32 bit data bus for example may be 0110 1001 1111 0001 1100 0011 0000 1110. At time t5, EDO memory will drive data onto the data bus from column address Cn since the read address is not changing from cycle to cycle. For the example of figure 1 1, this value is 0110. At time t5, Burst EDO memory with a latency of two will provide data from column address Cn+1 since the Burst EDO memory will automatically increment the internal address in a burst read access cycle. In this manner, the memory type whether Fast Page Mode, EDO, or Burst EDO can be determined at time t5. A more comprehensive method will perform more than two write and three read cycles in order to allow for Burst EDO memory devices with latencies of other than two. For example, if four write cycles are followed by five read cycles, and the data is sampled with /CAS high after the fifth read cycle, then the data will be bus dependent for Fast Page Mode memory, still equal to the first data value for EDO memory, and either equal to the fourth, third or second data value for Burst EDO memory with latency equal to two three or four respectively.

An additional method in accordance with the present invention is to write the data in a burst mode format maintaining the column address at Cn while toggling /CAS and providing multiple data patterns. A read cycle at address Cn+x, where Cn+x is within a range of addresses that would have been written to in a Burst EDO memory device, is then performed as part of a burst or page mode read sequence. The data pattern read from address Cn+x will match the pattern written to Cn+x after a latency if the memory is Burst EDO memory. Fast Page Mode and EDO memory will provide whatever data was present at Cn+x prior to the burst mode write. Alternately, a single read cycle to address Cn, where the data is sampled near the end of the /CAS low period, will provide valid data out for either Fast Page Mode or EDO 30 memory, but not for Burst EDO memory since the latency will not have been met.

In each of the above methods for determining a memory type present in system, the step of placing the memory in a particular mode should be performed if it is known that the memory itself may have multiple modes of operation. The memory may be tested after following the appropriate procedure for placing the memory in each of the possible desired modes of operation in order to determine what modes of operation the memory will support. Also, linear versus sequential addressing modes must be taken into account if the memory may have the ability to switch between these addressing modes. Any SRAM cache should be disabled prior to performing the methods described, or additional steps may be required to guarantee that data being read is not cached data only. Also, a known background data pattern may be written to an address range where the method will be used in order to avoid possible false data matches to uninitialized memory locations. The present invention teaches a system having multiple memory banks where some or all memory banks may have one of several types of memory. For systems designed in accordance with this teaching, each bank may be individually tested as described above. The memory controller of the system is programmed to access each bank in accordance with the type of memory present.

While the present invention has been described with reference to preferred embodiments, numerous modifications and variations of the invention will be apparent to one of skill in the art without departing from the scope of the invention.

Claims

What is claimed is:

1. A computer system comprising: a microprocessor; a memory controller coupled to an address path of the microprocessor; a data buffer coupled to a data path of the microprocessor; and a main memory comprising: a first main memory portion, occupying a first address space of the microprocessor, coupled to the memory controller and directly connected to the data path of the microprocessor; and a second main memory portion, occupying a second address space of the microprocessor, coupled to the memory controller, having a memory data path coupled to the data path of the microprocessor through the data buffer.

2. The system of claim 1, further comprising: a cache memory overlying a portion of the first and second address space of the microprocessor, the cache memory directly connected to the data path of the microprocessor, wherein data stored in the cache memory is also stored in the main memory.

3. The system of claim 1 , wherein the data buffer is integrated within the memory controller.

4. The system of claim 1. wherein the second main memory portion is interchangeably comprised of Burst EDO or EDO DRAM devices.

5. The system of claim 1. wherein the first main memory portion comprises a Burst EDO DRAM device.

6. The system of claim 1, wherein the first main memory portion comprises a synchronous DRAM device. ^W° ^96/20446 PCI7US95/16976

32

7. The system of claim 1, further comprising: a peripheral component interconnect (PCI) bus; and a PCI bus interface circuit coupled to the microprocessor and to the 5 PCI bus.

8. The system of claim 7, wherein the PCI bus interface circuit is integrated within the memory controller.

0 9. The system of claim 8, further comprising: a display; and a display control circuit coupled to the second main memory portion and to the display, wherein a portion of the second main memory portion is adapted to store information to be displayed by the display. 5

10. A computer system comprising: an address bus; a data bus: a microprocessor coupled to the address bus and the data bus; 0 a memory controller coupled to the address bus and to the microprocessor; a multiplexed address bus coupled to the memory controller; a first random access memory, providing a first data storage capacity, coupled to the multiplexed address bus. the memory controller and directly 5 coupled to the data bus, the first dynamic random access memory capable of burst access and accessible by the microprocessor; a bidirectional data driver coupled to the data bus; a second random access memory, providing an additional data storage capacity, coupled to the memory controller and the bidirectional data driver. 0 wherein memory from the second dynamic random access memory is accessible by the microprocessor through the bidirectional data driver; a peripheral device; and 33 a system bus coupled to the address bus and the data bus through the memory controller, and coupled to the peripheral device, wherein the peripheral device has access to the first random access memory through the memory controller.

11. A method of operating a computer having a processor, comprising steps of: storing information in a first noncache main memory portion of the computer which is directly coupled to the processor; 0 storing information in a second main memory portion of the computer which is coupled to the processor through a data buffer; requesting information from the first main memory portion; waiting a plurality of wait state cycles of the processor to receive requested information from the first main memory portion; 5 receiving requested information within the processor; and receiving additional information from the first main memory portion, after the step of receiving requested information; wherein no processor wait states are required between the step of receiving requested information, and the step of receiving additional information. 0

12. The method of claim 1 1, further comprising steps of: requesting information from the second main memory portion; waiting a plurality of wait state cycles of the processor to receive requested information from the second main memory portion; 5 receiving requested information from the second main memory portion within the processor; and receiving additional information from the second main memory portion, after the step of receiving requested information from the second main memory portion; wherein at least one processor wait state is required 0 between the step of receiving requested information from the second main memory portion, and the step of receiving additional information from the second main memory portion.

13. The method of claim 12, further comprising steps of: requesting information from the second main memory portion; receiving the third information value within the processor from a cache memory; and receiving a fourth information value from the cache memory, after the step of receiving the third information value; wherein no processor wait states are required between the step of receiving the third information value, and the step of receiving the fourth information value.