KR100329604B1 - Method for fabricating metal oxide semiconductor field effect transistor - Google Patents
Method for fabricating metal oxide semiconductor field effect transistor Download PDFInfo
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- KR100329604B1 KR100329604B1 KR1019950008137A KR19950008137A KR100329604B1 KR 100329604 B1 KR100329604 B1 KR 100329604B1 KR 1019950008137 A KR1019950008137 A KR 1019950008137A KR 19950008137 A KR19950008137 A KR 19950008137A KR 100329604 B1 KR100329604 B1 KR 100329604B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000005669 field effect Effects 0.000 title abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000460 chlorine Substances 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 4
- 239000011737 fluorine Substances 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- 230000005684 electric field Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052801 chlorine Inorganic materials 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract 2
- 229910021332 silicide Inorganic materials 0.000 description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 13
- 238000002844 melting Methods 0.000 description 7
- 230000008018 melting Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910008284 Si—F Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910008051 Si-OH Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910006358 Si—OH Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
Description
본 발명은 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하 MOSFET라 칭함)의 제조방법에 관한것으로서, 특히 게이트전극을 다결정실리콘층과 텅스텐 실리사이드층 패턴으로 형성할 때, 염소 분위기에서 열처리하여 F(Fluorine)의 게이트산화막으로의 침투를 방지하여 F에 의한 게이트산화막의 특성 악화를 방지하고, 반도체기판 표면 결함을 보상하여 소자동작의 신뢰성을 향상시킬 수 있는 MOSFET의 제조방법 에 관한것이다.The present invention relates to a method for manufacturing a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOSFET), in particular, when the gate electrode is formed of a polysilicon layer and a tungsten silicide layer pattern, heat-treated in a chlorine atmosphere to The present invention relates to a method for fabricating a MOSFET capable of preventing the penetration of (Fluorine) into the gate oxide film, thereby preventing the gate oxide film from deteriorating by F, and compensating for semiconductor substrate surface defects to improve the reliability of device operation.
반도체소자가 고집적화되어 감에 따라 MOSFET의 게이트 전극도 폭이 줄어들고 있으나, 게이트전극의 폭이 N배 줄어들면 게이트전극의 전기 저항이 N배 증가되어 반도체소자의 동작속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 모스 전계효과 트랜지스터 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드가 저저항 게이트로서 실용화되었으며, 폴리실리콘층상에 텅스텐등과 같은 고융점금속층을 적층하여 저저항 게이트를 형성하기도 한다.As the semiconductor device is highly integrated, the width of the gate electrode of the MOSFET is also reduced. However, when the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is increased by N times, thereby reducing the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon, which is a laminated structure of the polysilicon layer and the silicide, was utilized as a low-resistance gate by using the characteristics of the polysilicon layer / oxide layer showing the most stable MOS field effect transistor characteristics. A low resistance gate may be formed by laminating a high melting point metal layer such as tungsten on the layer.
그러나 상기와 같은 고융점금속을 적층한 게이트전극은 고융점 금속층 형성 공정시 스파이크 현상에 의해 고융점 금속이 게이트 절연막내로 침투하여 계면준위나 고정 전하를 증가시키고, 게이트전극 형성후의 고온열처리 공정에서 고융점금속이 산화되는 등의 문제점이 있으며, 이를 해결하기 위하여 고융점금속을 고순도화하고, 고융점금속막 형성방법을 개선하거나, H2O/H2혼합가스 분위기에서 열처리하여 산화를 방지하는 방법등이 연구되고 있다.However, in the gate electrode in which the high melting point metal is stacked, the high melting point metal penetrates into the gate insulating film by the spike phenomenon in the high melting point metal layer forming process, thereby increasing the interface level or the fixed charge, and in the high temperature heat treatment process after forming the gate electrode. There are problems such as oxidation of the melting point metal, and in order to solve this problem, the high melting point metal is highly purified, the method of forming a high melting point metal film is improved, or the heat treatment is performed in a H 2 O / H 2 mixed gas atmosphere to prevent oxidation Etc. are being studied.
또한 일반적으로 N 또는 P형 반도체기판에 P 또는 N형 불순물로 형성되는 PN 접합은 불순물을 이온주입한 후, 열처리로 활성화시켜 형성한다.In general, PN junctions formed of P or N type impurities on an N or P type semiconductor substrate are formed by ion implantation of impurities and then activation by heat treatment.
최근에는 반도체소자가 고집적화되어 소자의 밀도 및 스위칭 스피드가 증가되고, 소비전력을 감소시키기 위하여 반도체소자의 디자인률이 0.5㎛ 이하로 감소된다. 이에 따라 확산영역으로 부터의 측면 확산에 의한 숏채널 효과(short channel effect)를 방지하기 위하여 접합 깊이를 얕게 형성하며, 소오스/드레인전극을 저농도 불순물영역을 갖는 엘.디.디(lightly doped drain; 이하 LDD라 칭함) 구조로 형성하여 열전하 효과도 방지한다.In recent years, semiconductor devices have been highly integrated, so that the density and switching speed of the devices are increased, and the design rate of the semiconductor devices is reduced to 0.5 μm or less in order to reduce power consumption. Accordingly, in order to prevent short channel effects due to side diffusion from the diffusion region, the junction depth is shallow, and the source / drain electrodes have a lightly doped drain having a low concentration impurity region; Also referred to as LDD) structure to prevent the thermal charge effect.
종래 MOSFET의 제조방법에 관하여 살펴보면 다음과 같다.Looking at the manufacturing method of the conventional MOSFET as follows.
먼저, N 또는 P형 반도체기판 상에 게이트산화막을 형성하고, 상기 게이트산화막 상에 다결정실리콘층과 W 실리사이드을 순차적으로 도포한후, 패턴닝하여 다결정실리콘층 및 W 실리사이드을 패턴으로된 일련의 게이트전극을 형성한다.First, a gate oxide film is formed on an N or P-type semiconductor substrate, and a polysilicon layer and W silicide are sequentially coated on the gate oxide film, and then patterned to form a series of gate electrodes having a polysilicon layer and W silicide as a pattern. Form.
상기와 같은 종래 기술에 따른 MOSFET의 제조방법은 7SiH4+ 2WF6→ 2WSi2+ 3SiF4+ 14H2반응에 의해 W 실리사이드를 형성하는데, 이때 F 성분과 H2성분이 게이트전극과 게이트산화막으로 침투하여 Si-F, F-O 또는 O-F-O 등의 결합이 생성되어 게이트산화막의 두께를 약 20% 정도 증가시키거나, 결함이 되는 댕글링 본드(dangling bond)를 형성하여, 댕글링 본드에 의해 부분 전계가 집중되어 게이트산화막의 절연 특성이 악화되고, 누설전류가 증가되어 공정수율 및 소자동작의 신뢰성이 떨어지는 문제점이 있다.The method of manufacturing a MOSFET according to the prior art as described above forms W silicide by a reaction of 7SiH 4 + 2WF 6 → 2WSi 2 + 3SiF 4 + 14H 2, wherein the F component and the H 2 component penetrate into the gate electrode and the gate oxide film. Si-F, FO or OFO bonds are formed to increase the thickness of the gate oxide film by about 20%, or to form a dangling bond that is defective, and the partial electric field is concentrated by the dangling bond. As a result, the insulation characteristics of the gate oxide film are deteriorated, and the leakage current is increased, thereby decreasing process yield and reliability of device operation.
본발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본발명의 목적은 게이트전극의 일부가 되는 W 실리사이드 형성시 기판으로 침투한 F를 외부로 방출시켜 게이트산화막의 절연 특성을 향상시키고, 누설전류를 감소시켜 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 MOSFET의 제조방법을 제공함에 있다.The present invention is to solve the above problems, the object of the present invention is to release the F penetrated into the substrate to the outside when forming the W silicide to be a part of the gate electrode to the outside to improve the insulating characteristics of the gate oxide film, and to improve the leakage current The present invention provides a method for manufacturing a MOSFET that can reduce process yield and improve device reliability.
상기와 같은 목적들을 달성하기 위한 본발명에 따른 MOSFET 제조방법의 특성은, 반도체기판상에 게이트산화막을 형성하는 공정과, 상기 게이트산화막상에 다결정실리콘층층을 형성하는 공정과, 상기 다결정실리콘층상에 W 실리사이드층을 형성하는 공정과, 상기 구조의 반도체기판을 염소가스 분위기에 예정된 조건에서 열처리공정을 통해 노출시켜 F성분을 제거하는 공정과, 상기 W 실리사이드층과 다결정실리콘층을 패턴닝하여 게이트전극을 형성하는 공정을 구비함에 있다.The characteristics of the MOSFET manufacturing method according to the present invention for achieving the above object, the process of forming a gate oxide film on a semiconductor substrate, the process of forming a polysilicon layer layer on the gate oxide film, on the polycrystalline silicon layer Forming a W silicide layer, exposing the semiconductor substrate of the structure to a chlorine gas atmosphere through a heat treatment process to remove the F component, and patterning the W silicide layer and the polysilicon layer to form a gate electrode It has in the process of forming a.
이하, 본발명에 따른 MOSFET의 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a MOSFET according to the present invention will be described in detail with reference to the accompanying drawings.
제 1A도 및 제 1B도는 본발명에 따른 MOSFET의 제조 공정도이다.1A and 1B are manufacturing process diagrams of a MOSFET according to the present invention.
먼저, 제 1 도전형, 예를들어 N 또는 P형 반도체기판(1)상에 소정두께, 예를들어 70∼15OÅ 정도 두께의 게이트산화막(2)을 형성하고, 상기 게이트산화막(2) 상에 다결정실리콘층(3)과 W 실리사이드층(4)을 순차적으로 형성한다. 이때 F가 다결정실리콘층(3)과 게이트산화막(2)을 뚫고 들어가면서 완전한 SiO2산화막을 깨뜨려 산소를 추출시키게 되고 이로 인해 SiO2→ Si-O, Si-OH 등을 형성하면서 게이트산화막(2)과 다결정실리콘층(3)에 F가 Si-F, F-0 또는 0-F-0 형태로 포함되어진다.First, a gate oxide film 2 having a predetermined thickness, for example, about 70 to 150 Å thick, is formed on a first conductive type, for example, an N or P type semiconductor substrate 1, and then on the gate oxide film 2. The polysilicon layer 3 and the W silicide layer 4 are sequentially formed. At this time, as F penetrates through the polysilicon layer 3 and the gate oxide film 2, it breaks the complete SiO 2 oxide film and extracts oxygen, thereby forming SiO 2 → Si-O, Si-OH, and the like. F is included in the polycrystalline silicon layer 3 in the form of Si-F, F-0 or 0-F-0.
그다음 상기 구조의 반도체기판(1)을 예정된 온도, 예를들어 900∼1000℃ 정도의 온도에서 염소가스 분위기에서 열처리하여 상기 구조에 포함되어있는 F를 염소와 결합시켜 외부로 방출시킨다. 상기 열처리시에는 TCA(C2H3Cl3)나 DCE(C2H2Cl2)를 산소와 혼합하여, 900∼1000℃ 정도의 온도에서 30분∼3 시간 동안 열처리하면,Then, the semiconductor substrate 1 of the structure is heat-treated in a chlorine gas atmosphere at a predetermined temperature, for example, about 900 to 1000 ° C., and F contained in the structure is combined with chlorine to be released to the outside. In the heat treatment, TCA (C 2 H 3 Cl 3 ) or DCE (C 2 H 2 Cl 2 ) is mixed with oxygen and heat treated at a temperature of about 900 to 1000 ° C. for 30 minutes to 3 hours.
C2H3Cl3+ 202→ 3HCl +2CO2 C 2 H 3 Cl 3 + 20 2 → 3HCl + 2 CO 2
C2H2Cl2+ 202→ 2HCl +2CO2 C 2 H 2 Cl 2 + 20 2 → 2HCl + 2 CO 2
열처리시 생성된 Cl 성분이 침투하여 상기 구조 내부의 F와 결합하며, 상기 F-Cl 결합은 920℃ 이상의 온도에서 외부로 방출된다.The Cl component generated during the heat treatment penetrates and bonds with the F inside the structure, and the F-Cl bond is released to the outside at a temperature of 920 ° C or higher.
따라서 격자결함의 원인이 되는 댕글링 본드가 제거된다.Thus, the dangling bonds causing the lattice defects are eliminated.
또한 Si-Cl이 결합에너지가 9.22eV로 산화막에 비해 매우 높으므로 기판의 실리콘 성분과 결합된 Cl에 의해 게이트산화막의 절연특성이 향상되며, 기판 표면의 결함도 보상하여 특성이 향상된다 (제 1A 도 참조).In addition, since Si-Cl has a bonding energy of 9.22 eV, which is much higher than that of the oxide film, the insulating property of the gate oxide film is improved by Cl combined with the silicon component of the substrate, and the defects on the surface of the substrate are also compensated for. See also).
그후, 상기 W 실리사이드층(4)과 다결정실리콘층(3)을 패턴닝하여 서로 중첩되어 있는 다결정실리콘층(3) 패턴과 W 실리사이드층(4) 패턴으로 구성되는 게이트전극을 형성한 후, 상기 게이트전극 양측의 반도체기판(1)에 소오스/드레인전극(5)을 형성하여 MOSFET를 완성한다.(제 1B 도 참조).Thereafter, the W silicide layer 4 and the polysilicon layer 3 are patterned to form a gate electrode composed of a polysilicon layer 3 pattern and a W silicide layer 4 pattern overlapping each other. A source / drain electrode 5 is formed on the semiconductor substrate 1 on both sides of the gate electrode to complete the MOSFET (see FIG. 1B).
제 1C 도와 제 1D 도는 본 발명에 따라 TCA 처리를 한 경우에 있어서, TCA 처리를 하지 않은 종래의 방법과 게이트 산화막의 누설전류 및 게이트 전압 쉬프트(Shift) 값을 비교하여 도시한 그래프이다.1C and 1D are graphs comparing the leakage current and gate voltage shift values of the gate oxide film with the conventional method without TCA treatment in the case of TCA treatment according to the present invention.
상기 도면에서 A는 종래의 방법에 따른 경우이고, B는 본 발명에 따른 경우이다. 도면에 도시된 바와같이, 본 발명에 따라 TCA 처리를 한 경우에는 종래의 방법에 따른 경우보다 낮은 누설전류를 나타내고 있으며(제 1C 도), 또한 게이트 전압 쉬프트값도 A의 경우가 B의 경우보다 훨씬 큰 양을 나타내고 있다.(제1D 도)In the figure, A is the case according to the conventional method, B is the case according to the present invention. As shown in the figure, the TCA treatment according to the present invention shows a lower leakage current than in the conventional method (FIG. 1C), and the gate voltage shift value in the case of A is higher than that of B. It shows much larger quantity (Fig. 1D).
이상에서 설명한 바와 같이, 본발명에 따른 MOSFET의 제조방법은 게이트산화막상에 다결정실리콘층과 W 실리사이드층을 순차적으로 형성하고, 상기 구조의 반도체기판을 TCA나 DCE를 포함하는 가스분위기에서 900℃ 이상의 온도에서 열처리하여 W 실리사이드 형성시 포함된 F를 염소성분과 결합시키고, 상기 F-Cl을 외부로 방출시켜 결합의 원인을 제거한 후, 게이트전극을 형성하였으므로, F에 의한 댕글링 본드가 제거되고 반도체기판 표면의 결함이 염소 성분에 의해 보상되어 누설전류가 감소되고, 게이트산화막의 절연 특성이 향상되어 공정수율 및 소자동작의 신뢰성이 향상되는 이점이 있다.As described above, in the MOSFET manufacturing method according to the present invention, the polysilicon layer and the W silicide layer are sequentially formed on the gate oxide film, and the semiconductor substrate having the structure is 900 ° C or higher in a gas atmosphere containing TCA or DCE. Since the F included during the formation of the W silicide by heat treatment at a temperature was combined with the chlorine component, the F-Cl was released to remove the cause of the bonding, and the gate electrode was formed, so the dangling bond by F was removed and the semiconductor was removed. Defects on the surface of the substrate are compensated by the chlorine component to reduce the leakage current, and the insulating property of the gate oxide film is improved, thereby improving process yield and device operation reliability.
제 1A 도 및 제 1B 도는 본발명에 따른 모스 전계효과 트랜지스터의 제조공정도.1A and 1B are a manufacturing process diagram of a MOS field effect transistor according to the present invention.
제 1C 도 및 제 1D 도는 본발명의 제조방법에 따른 경우에 있어 게이트 산화막에서의 누설전류 및 게이트 전압 쉬프트값을 종래의 방법에 따른 경우와 비교한 그래프1C and 1D are graphs comparing the leakage current and the gate voltage shift value in the gate oxide film with the conventional method in the case of the manufacturing method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 게이트산화막1 semiconductor substrate 2 gate oxide film
3 : 다결정실리콘층 4 : W 실리사이드층3: polycrystalline silicon layer 4: W silicide layer
5 : 소오스/드레인전극5 source / drain electrodes
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