KR100326533B1 - Plasma Display Panel Of High Frequency And Fabrication Method Thereof - Google Patents

Abstract

The present invention relates to a plasma display panel having a structure capable of reducing the writing voltage of the plasma display panel and a method of manufacturing the same.

The high frequency plasma display panel of the present invention is characterized by comprising a dielectric pattern having a peak and a valley on the first substrate, and a scan electrode and a data electrode arranged to intersect at the valley between the dielectric patterns.

According to the present invention, by reducing the thickness of the dielectric layer between the data electrode and the discharge space by using the convex dielectric pattern, the writing voltage can be lowered, thereby reducing the circuit cost.

Description

High frequency plasma display panel and its manufacturing method {Plasma Display Panel Of High Frequency And Fabrication Method Thereof}

The present invention relates to a plasma display device, and more particularly, to a plasma display panel having a structure capable of reducing a writing voltage of a plasma display panel using high frequency.

Recently, a plasma display panel (hereinafter referred to as PDP), which is easy to manufacture a panel as a large-area flat panel display, is drawing attention as a large flat panel display needs. The PDP generally uses a gas discharge phenomenon to display an image using visible light generated by vacuum ultraviolet rays generated during gas discharge to emit phosphors. These PDPs are expected to be large wall-mounted TVs (Television) because they have advantages such as ease of manufacture, large area, and wide viewing angle. On the other hand, PDP has the disadvantage of low luminous luminance and luminous efficiency.

The PDP is usually composed of discharge cells corresponding to matrix pixels. Each of these discharge cells is selected by the address discharge, and the vacuum ultraviolet rays generated by the sustain discharge discharge the phosphor to emit visible light. In this case, the PDP adjusts the sustain discharge period, that is, the number of sustain discharges, to display the gray scale required for displaying an image. The number of sustain discharges is an important factor in determining the luminous luminance and luminous efficiency of the PDP. However, when the sustain discharge is generated using the existing low frequency AC voltage, the sustain discharge is generated only once at a short time for each applied voltage pulse, and most of the other time is consumed as a step for forming wall charges and preparing for the next discharge. The light emission luminance and light emission efficiency of the PDP were inevitably low.

In order to solve the low luminous luminance and luminous efficiency problems of the PDP, a method of applying a high frequency voltage as a sustain voltage has recently been introduced. When a high frequency voltage of several MHz to several hundred MHz is applied, a vibrating electric field is generated inside the discharge cell, and electrons are continuously vibrated to ionize and excite the discharge gas as it vibrates, thereby continuously discharging the electrons for most of the discharge time. Discharge, that is, high frequency discharge occurs. The high frequency discharge has a physical effect such as a positive column having a very high discharge efficiency when the distance between the electrodes is long in the glow discharge. Accordingly, there is an advantage that can significantly improve the discharge efficiency of the PDP when using a high frequency discharge.

1 and 2, a perspective view and a cross-sectional view of a high frequency PDP is shown.

1 and 2, the PDP using high frequency includes a high frequency electrode 12 formed on the upper substrate 10, an address electrode 16 and a scanning electrode 20 disposed on the lower substrate 14. The upper substrate 10 and the lower substrate 14 are spaced apart in parallel by the partition 26, and the upper substrate 10 is formed with a high frequency electrode 12 to which a high frequency voltage is applied. The first dielectric layer 13 is coated on the upper substrate 10 on which the high frequency electrode 12 is formed. The address electrode 16 and the scan electrode 20 are formed on the lower substrate 14 in a direction crossing each other. Here, the scan electrode 20 is formed in parallel with the high frequency electrode 12. The second dielectric layer 18 is formed between the address electrode 16 and the scan electrode 20, and the third dielectric layer 22 and the passivation layer 24 are sequentially formed on the second dielectric layer 18 on which the scan electrode 20 is formed. Is formed. The partition wall 26 is formed on the upper part of the protective film 24, and the fluorescent substance 28 is apply | coated to the surface of the partition wall 26. As shown in FIG. In this case, the partition wall 26 is set higher because the distance between the two electrodes, that is, the high frequency electrode 12 and the scan electrode 20, must be sufficiently secured for the high frequency discharge. Accordingly, in order to prevent crosstalk between discharge cells, the partition wall 26 is formed in a lattice shape to separate the discharge space in units of discharge cells. Then, the discharge gas is filled in the discharge space therein. Each of the discharge cells having a matrix form in the PDP generates an address discharge when a data signal is supplied to the address electrode 16 and a scan signal is supplied to the scan electrode 20. All particles vibrate in a state in which ions do not move between the high frequency electrode 12 and the scan electrode 20 and only electrons are not attracted to the two electrodes 12 and 20 by the high frequency voltage supplied to the high frequency electrode 12. Will be In this manner, the vibrating electrons ionize and excite the discharge gas continuously, and emit visible light by emitting vacuum ultraviolet rays and emitting phosphor 28 while the excited atoms and molecules transition to the ground state.

As the address electrode 16 and the scan electrode 20 are sequentially formed on the same lower substrate 14 in the high frequency PDP structure, the second and third dielectric layers 18 are disposed on the address electrode 16 as shown in FIG. 3. , 22). As a result, the high frequency PDP has a structure in which the thickness t of the dielectric layers 18 and 22 on the address electrode 16 is about twice as thick as that of the conventional low frequency AC type PDP. In this case, since the voltage applied to the discharge space from the address electrode 16 is absorbed more by the thick dielectric layers 18 and 22, the voltage applied to the discharge space is inevitably lowered. Accordingly, in order to generate a reliable address discharge in the discharge space, a higher data voltage is applied to the address electrode 16 or a higher scan voltage is applied to the scan electrode 20 in consideration of the amount absorbed by the thick dielectric layers 18 and 22. Must be approved. As a result, the conventional high frequency PDP has a problem in that the circuit cost becomes large because the lighting voltage for address discharge must be applied structurally.

Accordingly, an object of the present invention is to provide a high frequency PDP and a method of manufacturing the same, which can reduce the writing voltage for address discharge by reducing the thickness of the dielectric layer between the discharge space and the address electrode.

It is another object of the present invention to provide a high frequency PDP and a method of manufacturing the same which can reduce the writing voltage by reducing the discharge distance between the two electrodes by making the height of the scan electrode and the address electrode the same.

1 is a perspective view showing a conventional high frequency plasma display panel.

FIG. 2 is a cross-sectional view of the plasma display panel shown in FIG. 1. FIG.

3 is a cross-sectional view showing a discharge cell formed in the plasma display panel shown in FIG.

4 is a cross-sectional view illustrating a high frequency plasma display panel according to an exemplary embodiment of the present invention.

5A through 5E are cross-sectional views illustrating a method of manufacturing the plasma display panel shown in FIG. 4 in stages.

6 is a cross-sectional view showing a high frequency plasma display panel according to another embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

10: upper substrate 12: high frequency electrode

13: upper dielectric layer 14, 30: lower substrate

16, 34, 46: address electrodes 18, 36, 48: first dielectric layer

20, 38: scanning electrode 22, 40: second dielectric layer

24: protective layer 26, 42: partition wall

28: phosphor 32, 44: dielectric pattern

In order to achieve the above object, the high frequency PDP according to the present invention includes a dielectric pattern having a peak and a valley on the first substrate, and a scan electrode and a data electrode arranged to intersect at the valley between the dielectric patterns. do.

A method of manufacturing a high frequency PDP according to the present invention includes forming a dielectric pattern having a peak and a valley on a first substrate, and sequentially forming a data electrode and a scan electrode to intersect at the valley between the dielectric patterns. It is characterized by.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a cross-sectional view of a lower plate of the high frequency PDP according to an embodiment of the present invention. The lower plate of the high frequency PDP shown in FIG. 4 is a dielectric pattern 32 and a data electrode formed sequentially on the lower substrate 30. 34 and the first dielectric layer 36, the scan electrode 38 formed on the first dielectric layer 36 orthogonal to the data electrode 34, and the first dielectric layer 36 formed on the scan electrode 38. The second dielectric layer 40 and the partition 42 formed on the second dielectric layer 40 are provided.

In the high frequency PDP of FIG. 4, the dielectric pattern 32 is formed on the lower substrate 30 at regular intervals in a convex shape. The data electrode 34 is formed to have a uniform thickness on the lower substrate 30 on which the dielectric pattern 32 is formed. In this case, since the lower dielectric pattern 32 has a convex shape at regular intervals, the data electrode 34 has a hill and valley structure. The first dielectric layer 36 coated on the front surface including the data electrode 34 having the mountain / valley structure also has a mountain / valley structure having the same shape as the data electrode 34. In this case, the valley portion of the first dielectric layer 36 becomes more concave than the valley portion of the data electrode 34. The scan electrode 38 is formed in a direction perpendicular to the data electrode 34 on the valley portion of the first dielectric layer 36 that is smoother. The second dielectric layer 40 is formed to have a flat surface on the second dielectric layer 40 on which the scan electrode 38 is formed. In this case, the thickness t 'of the first and second dielectric layers 36 and 40 formed on the acid portion of the data electrode 34 may be thinner than in the related art. Thus, as the thickness t 'of the first and second dielectric layers 36 and 40 on the data electrode 34 becomes thinner than before, the amount of voltage absorption transmitted from the data electrode 34 to the discharge space 41 is increased. Since it decreases, the lighting voltage can be lowered by that much. The partition wall 42 is formed on the second dielectric layer 40 where the acid electrodes of the data electrode 34 and the first dielectric layer 36 are positioned.

5A through 5E are cross-sectional views illustrating a method of manufacturing a PDP lower plate shown in FIG. 4 in steps.

First, as shown in FIG. 5A, the dielectric pattern 32 is formed on the lower substrate 30. The dielectric pattern 32 is formed by repeating the screen printing method using a mask in which a stripe pattern is formed. In this case, when the screen printing method is repeated, the dielectric at the edge portion collapses, and as a result, the dielectric pattern 32 is formed on the lower substrate 30 in a convex shape. Next, as illustrated in FIG. 5B, the data electrode 34 is formed on the lower substrate 30 on which the dielectric pattern 32 is formed. The data electrode 34 is generally formed in a direction crossing the dielectric pattern 32 on the lower substrate 30 on which the dielectric pattern 32 is formed by a sputtering method. In this case, the data electrode 34 has a peak and valley structure corresponding to the convex dielectric pattern 32. Subsequently, as shown in FIG. 5C, the first dielectric layer 36 is coated over the data electrode 34. The first dielectric layer 36 is generally coated on the entire surface including the data electrode 34 by a screen printing method. In this case, the first dielectric layer 36 also has the same acid / valley structure as the data electrode 34. As shown in FIG. 5D, the scan electrode 38 is formed on the valley of the first dielectric layer 36 in a direction orthogonal to the data electrode 34. The scan electrode 38 is usually formed by a sputtering method. Finally, as shown in FIG. 5E, the second dielectric layer 40 is coated over the entire surface of the first dielectric layer 36 on which the scan electrodes 38 are formed. This second dielectric layer 40 is usually formed by a screen printing method.

6 is a cross-sectional view of a lower plate of the high frequency PDP according to another embodiment of the present invention. The lower plate of the high frequency PDP shown in FIG. 6 may have a dielectric pattern having a different shape from that of the dielectric pattern 32 shown in FIG. 44).

In the lower plate of the high frequency PDP shown in FIG. 6, the convex shape dielectric pattern 44 is formed to have a smaller size than the dielectric pattern 32 shown in FIG. 4 so that two are included at regular intervals in the discharge cell. In this case, two dielectric patterns 44 adjacent to the discharge cells are adjacent to each other. The data electrode 46 is formed to have a uniform thickness across the dielectric pattern 44 on the lower substrate 30 on which the dielectric pattern 44 is formed. In this case, corresponding to the convex shape of the dielectric pattern 44, the data electrode 46 has a hill and valley structure. In particular, the data electrode 46 has a flat valley located in the center portion of the discharge cell corresponding to the shape of the dielectric pattern 44 and has a concave valley located between the discharge cells. The first dielectric layer 48 coated on the front surface including the data electrode 46 having the acid / valley structure also has an acid / valley structure. The scan electrode 38 is formed in a direction perpendicular to the data electrode 46 in a flat valley of the first dielectric layer 48. The second dielectric layer 40 is formed to have a flat surface on the first dielectric layer 48 on which the scan electrode 38 is formed. In this case, it can be seen that the thicknesses t 'of the first and second dielectric layers 48 and 40 which are positioned at both sides of the scan electrode 38 and formed on the mountain portions of the data electrode 46 are thinner than in the related art. . As a result, the amount of absorbed data voltage transmitted from the data electrode 46 to the discharge space 41 is reduced, thereby lowering the data voltage or the scan voltage, that is, the writing voltage. In particular, since the acid portions of the data electrodes 46 positioned at both sides of the scan electrode 38 have a height similar to that of the scan electrode 38, the discharge distance between the two electrodes 38 and 46 can be reduced. In other words, since the distance between the scan electrode 38 in the valley portion and the data electrode 46 in the peak portion becomes the discharge distance, the discharge distance can be reduced by appropriately adjusting the size of the dielectric pattern 44. As such, when the discharge distance between the two electrodes 38 and 46 is reduced, the discharge voltage is reduced by that amount, thereby reducing the writing voltage.

As described above, according to the high frequency PDP and the manufacturing method thereof according to the present invention, the writing voltage can be lowered by reducing the distance between the data electrode and the discharge space by using the convex dielectric pattern. In addition, according to the high frequency PDP and the method of manufacturing the same according to the present invention, the writing voltage can be reduced by reducing the discharge distance between the data electrode and the scan electrode by using the convex dielectric pattern. Accordingly, the high frequency PDP according to the present invention can reduce the circuit cost.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

In the lower plate of the high frequency plasma display panel, A dielectric pattern having peaks and valleys on the first substrate, And a scan electrode and a data electrode arranged to intersect at the valleys between the dielectric patterns. The method of claim 1, A first dielectric layer overcoated between the scan electrode and the data electrode; And a second dielectric layer overcoated on the scan electrode. The method of claim 1, The dielectric pattern is a convex shape, characterized in that spaced apart by a predetermined distance formed high frequency plasma display panel. The method of claim 3, wherein And controlling a discharge distance between the scan electrode and the data electrode by adjusting the width of the dielectric pattern. In the manufacturing method of the lower plate of the high frequency plasma display panel, Forming a dielectric pattern having a peak and a valley on the first substrate; And sequentially forming a data electrode and a scan electrode to intersect at the valleys between the dielectric patterns. The method of claim 5, Coating a first dielectric layer between the data electrode and the scan electrode on the entire surface; A method of manufacturing a plasma display panel using a high frequency, the method further comprising the step of coating the second dielectric layer over the scan electrode. The method of claim 5, The dielectric pattern is a high frequency plasma display panel manufacturing method, characterized in that formed by a screen printing method using a stripe mask pattern.