KR100324329B1 - Low voltage precharge dynamic circuit - Google Patents

Abstract

The present invention relates to a low voltage precharge dynamic circuit. In the related art, a threshold voltage of a MOS transistor is lowered in order to prevent a decrease in operating speed when a low voltage circuit is implemented. Such a MOS transistor has a precharge or an evaluation operation. There was a problem that the sub-threshold leakage current flows. Accordingly, the present invention provides a semiconductor device comprising: a first PMOS transistor having a clock signal applied to a gate and a first power supply voltage applied to a source; A first NMOS transistor having a clock signal applied to the gate and a first ground voltage applied to the source; A plurality of enMOS transistors, each having an input signal applied to a gate and sequentially connected in series between a drain of the first PMOS transistor and a drain of the first NMOS transistor, to form a pull-down network; A first switch switched to apply a first power supply voltage or a second power supply voltage to the substrate of the first PMOS transistor according to a clock signal; A second switch which is switched to apply a first ground voltage or a second ground voltage to the substrate of the first NMOS transistor according to a clock signal; The output signal is output from the drain side of the first PMOS transistor so that the substrate voltage of the precharged MOS transistor is switched to select a different voltage source according to the precharge / evaluation state, thereby causing sub-threshold leakage. There is an effect that can prevent the current flowing.

Description

LOW VOLTAGE PRECHARGE DYNAMIC CIRCUIT}

The present invention relates to a low voltage precharge dynamic circuit, and more particularly, to a low voltage precharge dynamic circuit capable of reducing a sub-threshold leakage current flowing in a precharge or evaluation state.

1 is a circuit diagram illustrating a conventional low voltage precharge dynamic circuit, in which a clock signal Clk is applied to a gate, a substrate and a source are commonly connected, and a power supply voltage VDD is applied to the source. PMO transistor (Mp); An n-MOS transistor Mn to which a clock signal Clk is applied to a gate, a substrate and a source are commonly connected, and a ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn, the input signals in (0) to in (N) are respectively applied to the gates to sequentially connect the plurality of yens. Morph transistors (Mn1 to MnN); An output signal out is output at the drain side of the PMOS transistor Mp, and the operation of such a conventional apparatus will be described.

First, when the clock signal Clk is input at a low potential in order to charge, the PMOS transistor Mp is turned on and the NMOS transistor Mn is turned off to supply the power voltage VDD through the PMOS transistor Mp. The level is output as an output signal out.

In this case, in order to prevent a decrease in the operating speed, the PMOS transistors Mp and the NMOS transistors Mn and Mn1 to MnN have characteristics of low threshold voltages, and thus, the MOS transistors Mn1 used as pull-down networks. ˜MnN is turned on in the sub-threshold region so that leakage current flows through the NMOS transistors Mn and Mn1 to MnN during a long precharge.

If the clock signal Clk is input with a high potential for evaluating, the plurality of yen used as a pull-down network with the PMOS transistor Mp turned off and the nMOS transistor Mn turned on. When the MOS transistors Mn1 to MnN are turned on by the input signals in (0) to in (N), the ground voltage VSS level is output as the output signal out.

At this time, since the PMOS transistor Mp has a low threshold voltage, the PMOS transistor Mp is turned on in the sub-threshold voltage region, so that a leakage current flows through the PMOS transistor Mp.

2 is a circuit diagram illustrating a conventional low voltage precharge dynamic circuit, in which a clock signal Clk is applied to a gate, a substrate and a source are commonly connected, and a power supply voltage VDD is applied to the source. PMO transistor (Mp); An n-MOS transistor Mn to which a clock signal Clk is applied to a gate, a substrate and a source are commonly connected, and a ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn, a plurality of Ps sequentially connected in series by applying input signals in (0) to in (N) to the gate, respectively. A morph transistor Mp; An output signal out is output at the drain side of the nMOS transistor Mn, and the conventional apparatus configured as described above operates symmetrically with FIG. 1, which will be described in detail.

First, when the clock signal Clk is input at a low potential for evaluating, the PMOS used as the pull-up network in a state where the PMOS transistor Mp is turned on and the NMOS transistor Mn is turned off When the transistors Mp1 to Mpn are turned on, a signal having a power supply voltage VDD level is output to the output signal out.

In this case, since the nMOS transistor Mn has a low threshold voltage, the nMOS transistor Mn is turned on in the sub-threshold voltage region, and thus a leakage current flows through the nMOS transistor Mn. .

On the contrary, when the clock signal Clk is input at a high potential to precharge, the PMOS transistor Mp is turned off and the nMOS transistor Mn is turned on, and the ground voltage VSS is applied through the nMOS transistor Mn. ) Level is output as an output signal out.

At this time, the PMO transistors Mp, Mp1-MpN and NMOS transistor Mn have low threshold voltages in order to prevent the operation speed from being reduced. As a result, the PMO transistors Mp1, which are used as pull-up networks, are used. ˜MpN is turned on in the sub-threshold region so that leakage current flows through the PMOS transistors Mp and Mp1 to Mpp when precharged for a long time.

That is, as described above, the conventional device lowers the threshold voltage of the MOS transistor in order to prevent a decrease in the operating speed when the low voltage circuit is implemented. The MOS transistor has a sub-threshold leakage current during the precharge or evaluation operation. There was a problem flowing.

Accordingly, the present invention devised in view of the above-mentioned problems allows the sub-threshold leakage current to flow by selecting different voltage sources according to the precharge / evaluation state by using the substrate voltage of the precharged transistor as a switch. The aim is to provide a low voltage precharge dynamic circuit that can be prevented.

1 is a circuit diagram showing the configuration of a conventional low voltage precharge dynamic circuit.

2 is a circuit diagram showing the configuration of another embodiment of a conventional low voltage precharge dynamic circuit.

Figure 3 is a circuit diagram showing the configuration of an embodiment of the present invention low voltage precharge dynamic circuit.

FIG. 4 is a circuit diagram showing a signal flow when the clock signal Clk is low potential in FIG.

FIG. 5 is a circuit diagram showing a signal flow when the clock signal Clk has a high potential in FIG.

6 is a circuit diagram showing the configuration of another embodiment of the present invention low voltage precharge dynamic circuit.

Fig. 7 is a circuit diagram showing the configuration of another embodiment of the present invention low voltage precharge dynamic circuit.

Fig. 8 is a circuit diagram showing the configuration of another embodiment of the present invention low voltage precharge dynamic circuit.

***** Description of the symbols for the main parts of the drawings *****

Mp, Mp1-MpN: Pymotransistor Mn, Mn1-MnN: En-mo transistor

SW1, SW2: switch

The present invention for achieving the above object comprises a first PMOS transistor, the clock signal is applied to the gate, the first power supply voltage is applied to the source; A first NMOS transistor having a clock signal applied to the gate and a first ground voltage applied to the source; A plurality of enMOS transistors, each having an input signal applied to a gate and sequentially connected in series between a drain of the first PMOS transistor and a drain of the first NMOS transistor, to form a pull-down network; A first switch switched to apply a first power supply voltage or a second power supply voltage to the substrate of the first PMOS transistor according to a clock signal; A second switch which is switched to apply a first ground voltage or a second ground voltage to the substrate of the first NMOS transistor according to a clock signal; Characterized in that the output signal is output from the drain side of the first PMOS transistor.

Hereinafter, the operation and effects of the embodiment of the low voltage precharge dynamic circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram showing an embodiment of a low voltage precharge dynamic circuit according to the present invention, in which a clock signal Clk is applied to a gate and a first power supply voltage VDD is applied to a source. A transistor Mp; An n-MOS transistor Mn to which a clock signal Clk is applied to the gate and a first ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the nMOS transistor Mn, input signals in (0) to in (N) are respectively applied to the gates and sequentially connected in series to form a pull-down network. A plurality of enMOS transistors (Mn1 to MnN) to form; A first switch SW1 switched to apply a first power supply voltage VDD or a second power supply voltage VPP to a substrate of the PMOS transistor Mp in response to a clock signal Clk; A second switch SW2 that is switched to apply a first ground voltage VSS or a second ground voltage VBB to the substrate of the NMOS transistor Mn according to a clock signal Clk; The operation of the present invention configured to output the output signal out at the drain side of the PMOS transistor Mp will be described.

First, the first power supply voltage VDD is set to a voltage lower than the second power supply voltage VPP by a predetermined level, and the first ground voltage VSS is set to a voltage higher than the second ground voltage VBB by a predetermined level.

At this time, when the clock signal Clk is input at a low potential to charge, the first switch SW1 is switched to apply the first power supply voltage VDD to the substrate voltage of the PMOS transistor Mp, and the second switch. SW2 is switched so as to apply the second ground voltage VBB to the substrate voltage of the n-mo transistor Mn and is configured as shown in FIG.

Accordingly, the PMOS transistor Mp is turned on and the NMOS transistor Mn is turned off to output the first power voltage VDD level as an output signal out through the PMOS transistor Mp. The substrate voltage of the MOS transistor Mp becomes the first power supply voltage VDD so that the precharge is not disturbed.

In this case, in order to prevent a decrease in operating speed, the PMOS transistors Mp and the NMOS transistors Mn and Mn1 to MnN have low threshold voltages, and the substrate voltage of the NMOS transistor Mn is reduced. 2 The ground voltage VBB is used to make the threshold voltage of the NMOS transistor Mn higher than the threshold voltage of the NMOS transistors Mn1 to MnN used as the pull-down network, thereby suppressing the sub-threshold leakage current that can flow during precharging. do.

If the clock signal Clk is input at a high potential for evaluating, the first switch SW1 is switched to apply the second power supply voltage VPP to the substrate voltage of the PMOS transistor Mp. The second switch SW2 is switched to apply the first ground voltage VSS to the substrate voltage of the nMOS transistor Mn, and is configured as shown in FIG. 5.

At this time, when the PMOS transistor Mp is turned off and the MOS transistor Mn is turned on, when a plurality of NMOS transistors Mn1 to MnN used as a pull-down network are turned on by the input signal, the ground voltage VSS. The level is output as an output signal out, and the substrate voltage of the n-mo transistor Mn becomes the first ground voltage VSS so that pull-down is not prevented.

At this time, the substrate voltage of the PMOS transistor Mp is set as the second power supply voltage VPP, thereby increasing the threshold voltage of the PMOS transistor Mp, thereby reducing the sub-threshold leakage current that can flow through the PMOS transistor Mp. Suppress

FIG. 6 is a circuit diagram illustrating another embodiment of the low voltage precharge dynamic circuit of the present invention, in which a clock signal Clk is applied to a gate and a first power supply voltage VDD is applied to a source. PMOS transistor (Mp); An n-MOS transistor Mn to which a clock signal Clk is applied to the gate and a first ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn, a plurality of Ps sequentially connected in series by applying input signals in (0) to in (N) to the gate, respectively. Morph transistors Mp1 to MpN); A first switch SW1 switched to apply a first power supply voltage VDD or a second power supply voltage VPP to a substrate of the PMOS transistor Mp in response to a clock signal Clk; A second switch SW2 that is switched to apply a first ground voltage VSS or a second ground voltage VBB to the substrate of the NMOS transistor Mn according to a clock signal Clk; The operation of the present invention configured to output the output signal out at the drain side of the n-MOS transistor Mn will be described.

First, the first power supply voltage VDD is set to a voltage lower than the second power supply voltage VPP by a predetermined level, and the first ground voltage VSS is set to a voltage higher than the second ground voltage VPP by a predetermined level.

At this time, when the clock signal Clk is input at a low potential for evaluating, the first switch SW1 is switched to apply the second power supply voltage VPP to the substrate voltage of the PMOS transistor Mp. The second switch SW2 is switched to apply the first ground voltage VSS to the substrate voltage of the n-mo transistor Mn.

Accordingly, in a state in which the PMOS transistor Mp is turned on and the NMOS transistor Mn is turned off, the plurality of PMOS transistors Mp1 to Mpn used as pull-up networks are input signals in (0) to in ( N)), the second power supply voltage VPP level is outputted as an output signal out through the PMOS transistors Mp and Mp1 to MpN, and the substrate voltage of the NMOS transistor Mn is zero. 1 The sub voltage that can flow during evaluation by setting the ground voltage (VSS) level and making the threshold voltage of the NMOS transistor Mn higher than the threshold voltage of the PMOS transistors Mp1 to MpN used as a pull-up network. Suppresses threshold leakage current.

If the clock signal Clk is input at high potential for precharging, the first switch SW1 is switched to apply the first power supply voltage VDD to the substrate voltage of the PMOS transistor Mp, and the second switch SW1 is applied to the substrate voltage of the PMOS transistor Mp. The switch SW2 is switched to apply the second ground voltage VBB to the substrate voltage of the n-mo transistor Mn.

At this time, the PMOS transistor Mp is turned off and the NMOS transistor Mn is turned on so that the second ground voltage VBB level is output as the output signal out, and the substrate voltage of the PMOS transistor Mp is increased. The first power supply voltage VDD is used so that the pullup is not disturbed.

At this time, the substrate voltage of the n-MOS transistor Mn is set as the second ground voltage VBB, and the threshold voltage of the n-MOS transistor Mn is increased to thereby flow through the n-MOS transistors Mn, Mn1 to MnN. Suppresses threshold leakage currents.

FIG. 7 is a circuit diagram illustrating another embodiment of the low-voltage precharge dynamic circuit of the present invention, in which a clock signal Clk is applied to a gate and a first power supply voltage VDD is applied to a source. PMOS transistor (Mp); The second clock signal Clk is applied to the gate, the source and the substrate are commonly connected, the first power supply voltage VDD is applied to the connection point thereof, and the drain is connected to the substrate of the first PMOS transistor Mp. PMOS transistor (MpS1); The clock bar signal / Clk is applied to the gate, the source and the substrate are commonly connected, the second power supply voltage VPP is applied to the connection point, and the drain is connected to the substrate of the first PMOS transistor Mp. A third PMOS transistor (MpS2); A first enMOS transistor Mn to which a clock signal Clk is applied to the gate and a first ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn, the input signals in (0) to in (N) are respectively applied to the gates to sequentially connect the plurality of yens. Morph transistors (Mn1 to MnN); The second clock signal Clk is applied to the gate, the source and the substrate are commonly connected, the first ground voltage VSS is applied to the connection point thereof, and the drain is connected to the substrate of the first NMOS transistor Mn. NMOS transistor (MnS1); The clock bar signal / Clk is applied to the gate, the source and the substrate are commonly connected, and the second ground voltage VBB is applied to the connection point thereof, and the drain is connected to the substrate of the first NMOS transistor Mn. A third NMOS transistor (MnS2); The output signal out is output from the drain side of the first PMOS transistor Mp, and the operation of the embodiment of the present invention configured as described above is the same as in FIG.

8 is a circuit diagram showing a configuration of another embodiment of the present invention. As shown in FIG. 8, the general configuration is the same as that of FIG. A pull-up network is formed by substituting the PMOS transistors Mp1 to MpN, and the output signal (out) is generated on the drain side of the NMOS transistor Mn. do.

As described in detail above, the present invention can prevent the sub-threshold leakage current from flowing by selecting different voltage sources according to the precharge / evaluation state using a switch of the precharged substrate transistor voltage. It works.

Claims (20)

A PMOS transistor Mp having a clock signal Clk applied to the gate and a first power supply voltage VDD applied to the source; An n-MOS transistor Mn to which a clock signal Clk is applied to the gate and a first ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn, an input signal (in (0) to in (N)) is respectively applied to a gate and sequentially connected in series to form a pull-down network. A plurality of enMOS transistors (Mn1 to MnN) to form; A first switch SW1 switched to apply a first power supply voltage VDD or a second power supply voltage VPP to a substrate of the PMOS transistor Mp in response to a clock signal Clk; A second switch SW2 switched to apply a first ground voltage VSS or a second ground voltage VBB to the substrate of the enMOS transistor Mn according to a clock signal Clk; And a low voltage precharge dynamic circuit configured to output an output signal out at the drain side of the PMOS transistor Mp. The low voltage precharge dynamic circuit according to claim 1, wherein the NMOS transistors (Mn, Mn1 to MnN) have a low threshold voltage. The low voltage precharge dynamic circuit according to claim 1, wherein the PMOS transistor Mp has a low threshold voltage. The low voltage precharge dynamic circuit according to claim 1, wherein the first power supply voltage (VDD) is a predetermined level lower than the second power supply voltage (VPP). The low voltage precharge dynamic circuit of claim 1, wherein the first ground voltage VSS is a predetermined level higher than the second ground voltage VBB. The low voltage of claim 1, wherein the first switch SW1 is switched to apply the first power supply voltage VDD to the substrate voltage of the PMOS transistor Mp when the clock signal Clk is input at a low potential. Precharge dynamic circuit. The low voltage of claim 1, wherein the first switch SW1 is switched to apply the second power supply voltage VPP to the substrate voltage of the PMOS transistor Mp when the clock signal Clk is input at a high potential. Precharge dynamic circuit. 2. The low voltage of claim 1, wherein the second switch SW2 is switched to apply the second ground voltage VBB to the substrate voltage of the NMOS transistor Mn when the clock signal Clk is input at a low potential. Precharge dynamic circuit. 2. The low voltage of claim 1, wherein the second switch SW2 is switched to apply the first ground voltage VSS to the substrate voltage of the NMOS transistor Mn when the clock signal Clk is input at a high potential. Precharge dynamic circuit. A PMOS transistor Mp having a clock signal Clk applied to the gate and a first power supply voltage VDD applied to the source; An n-MOS transistor Mn to which a clock signal Clk is applied to the gate and a first ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn, a plurality of Ps sequentially connected in series by applying input signals in (0) to in (N) to the gate, respectively. Morph transistors Mp1 to MpN); A first switch SW1 switched to apply a first power supply voltage VDD or a second power supply voltage VPP to a substrate of the PMOS transistor Mp in response to a clock signal Clk; A second switch SW2 that is switched to apply a first ground voltage VSS or a second ground voltage VBB to the substrate of the NMOS transistor Mn according to a clock signal Clk; And a low voltage precharge dynamic circuit configured to output an output signal out at the drain side of the enMOS transistor Mn. 11. The low voltage precharge dynamic circuit according to claim 10, wherein the n-MOS transistor (Mn) has a low threshold voltage. The low voltage precharge dynamic circuit according to claim 10, wherein the PMOS transistors Mp and Mp1 to MpN have low threshold voltage characteristics. 11. The low voltage precharge dynamic circuit according to claim 10, wherein the first power supply voltage (VDD) is a predetermined level lower than the second power supply voltage (VPP). The low voltage precharge dynamic circuit of claim 10, wherein the first ground voltage VSS is at a predetermined level higher than the second ground voltage VBB. The low voltage of claim 10, wherein the first switch SW1 is switched to apply the first power supply voltage VDD to the substrate voltage of the PMOS transistor Mp when the clock signal Clk is input at a low potential. Precharge dynamic circuit. The low voltage of claim 10, wherein the first switch SW1 is switched to apply the second power supply voltage VPP to the substrate voltage of the PMOS transistor Mp when the clock signal Clk is input at a high potential. Precharge dynamic circuit. The low voltage of claim 10, wherein the second switch SW2 is switched to apply the second ground voltage VBB to the substrate voltage of the NMOS transistor Mn when the clock signal Clk is input at a low potential. Precharge dynamic circuit. The low voltage of claim 10, wherein the second switch SW2 is switched to apply the first ground voltage VSS to the substrate voltage of the NMOS transistor Mn when the clock signal Clk is input at a high potential. Precharge dynamic circuit. A first PMOS transistor Mp having a clock signal Clk applied to the gate and a first power supply voltage VDD applied to the source; The second clock signal Clk is applied to the gate, the source and the substrate are commonly connected, the first power supply voltage VDD is applied to the connection point thereof, and the drain is connected to the substrate of the first PMOS transistor Mp. PMOS transistor (MpS1); The clock bar signal / Clk is applied to the gate, the source and the substrate are commonly connected, the second power supply voltage VPP is applied to the connection point, and the drain is connected to the substrate of the first PMOS transistor Mp. A third PMOS transistor (MpS2); A first enMOS transistor Mn to which a clock signal Clk is applied to the gate and a first ground voltage VSS is applied to the source; Between the drain of the PMOS transistor Mp and the drain of the NMOS transistor Mn, the input signals in (0) to in (N) are respectively applied to the gates to sequentially connect the plurality of yens. Morph transistors (Mn1 to MnN); The second clock signal Clk is applied to the gate, the source and the substrate are commonly connected, the first ground voltage VSS is applied to the connection point thereof, and the drain is connected to the substrate of the first NMOS transistor Mn. NMOS transistor (MnS1); The clock bar signal / Clk is applied to the gate, the source and the substrate are commonly connected, and the second ground voltage VBB is applied to the connection point thereof, and the drain is connected to the substrate of the first NMOS transistor Mn. A third NMOS transistor (MnS2); And a low voltage precharge dynamic circuit configured to output an output signal out at the drain side of the first PMOS transistor Mp. 20. The pull-up network of claim 19, wherein the plurality of enmo transistors Mn1 to MnN forming a pull-down network are replaced with a plurality of PMOS transistors Mp1 to MpN to form a pull-up network, and the drain side of the enmo transistor Mn. Low voltage precharge dynamic circuit, characterized in that configured to generate an output signal.