KR100318428B1 - Input buffer of semiconductor memory device reduces current consumption - Google Patents

Abstract

The present invention includes a first node (A), a second node (B) and the output stage; A first PMOS transistor (P1) receiving an input signal having a TTL level from the outside of the chip as a gate terminal and connected between the first node and the second node;

A first NMOS transistor N2 receiving the input signal as a gate terminal and connected between the second node and a ground power supply terminal; A second NMOS transistor N3 receiving a control signal CS through a gate terminal and connected between the second node and a ground power supply terminal; An inverter (31) connected to an input terminal of the second node to output an output signal to the output terminal; And a third NMOS transistor N1 which transmits a voltage level lowered by its threshold voltage from a supply voltage to the first node when the input buffer is enabled in response to the control signal CS. The present invention relates to an input buffer of a semiconductor memory device, and has an effect of realizing a low power memory device by reducing constant current consumption generated in an input buffer of a semiconductor memory device.

Description

Input buffer of semiconductor memory device reduces current consumption

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer of a semiconductor memory device, and more particularly, in the case of a product requiring low power consumption by developing a low power consumption device, a constant current flowing in a chip even when a power supply in a steady state is applied to apply the same. The present invention relates to an input buffer of a semiconductor memory device capable of significantly reducing (static current, Icc).

In general, an input buffer is used in a semiconductor memory device to receive an external signal such as an address signal, a control signal, or a command. The main operation of the input buffer is to buffer a TTL level voltage into a CMOS level voltage signal. It is done.

1 is a conventional input buffer circuit diagram, through which a general input buffer will be described.

Referring to FIG. 1, a conventional input buffer includes a PMOS transistor MP1 and an NMOS transistor MN2 to which a control signal CS is applied as a gate, a PMOS transistor MP2 and an NMOS transistor MN1 to receive an input signal as a gate. And an inverter 1.

The control signal CS is input at a logic 'low' level when enabling the input buffer. When the 0.8V voltage, which is the low level of the TTL level, is input to the input signal, the NMOS transistor MN1 is turned off and the PMOS transistor MP2 is turned on so that the output node N1 is at a logic 'high' level. When the 2.4V voltage 'high' of the TTL level is input to the input signal, the NMOS transistor MN1 is turned on and the PMOS transistor MP2 is turned off so that the output node N1 is at a logic 'low' level. The signal of the node N1 is inverted through the inverter 1 and finally output to the inside of the memory element.

On the other hand, when the TTL logic 'high' level is applied, the NMOS transistor N2 should be turned on and the PMOS transistor P2 should remain turned off, and the input buffer is turned into a low active signal (logic 'low' level). Since the PMOS transistor MP1 receiving the control signal CS, which is the enable signal, is turned on, the potential of the drain terminal of the PMOS transistor MP1 is almost equal to that of the supply voltage Vcc, and the logic 'high' of the TTL level is approximately 2.4V. Since PMOS transistor MP2 does not remain turned off, it is turned on weakly (where Vcc is usually 5V or 3.3V). As a result, a current path is formed from the supply power supply terminal Vcc to the ground power supply terminal Vss so that a constant current flows.

In the memory device, especially SRAM (Static Random Access Memory), such input buffers are usually used about 20, in consideration of this, there is a problem that unnecessary power is consumed very much. In some cases, there is a risk of malfunction.

FIG. 2 shows a graph of the current characteristics of the input buffer shown in FIG. 1, which shows the current flowing through each transistor with respect to the power supply voltage Vcc and the constant current Icc.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide an input buffer of a semiconductor memory device capable of realizing a low power memory device by reducing a constant current.

Another object of the present invention is to provide an input buffer of a semiconductor memory device which reduces constant current and achieves stable operation.

The input buffer of the semiconductor memory device of the present invention for achieving the above object, the first node, the second node and the output stage; A first PMOS transistor receiving an input signal having a TTL level from the outside of the chip as a gate terminal and connected between the first node and the second node; A first NMOS transistor receiving the input signal through a gate terminal and connected between the second node and a ground power supply terminal; A second NMOS transistor receiving a control signal through a gate terminal and connected between the second node and the ground power supply terminal; An inverter connected to the second node and outputting an output signal to the output terminal; And a power supply terminal connected to the first node and receiving an inverted signal of the control signal through a gate terminal by inverters P2 and N4, and down by a threshold voltage of its own when the input buffer is enabled. And a third NMOS transistor for transmitting the voltage level to the first node.

Preferably, the semiconductor memory device of the present invention further includes a second PMOS transistor connected to a power supply terminal and the second node and receiving the output of the inverter as a gate terminal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a circuit diagram illustrating a configuration of a low power input buffer according to an embodiment of the present invention.

Referring to FIG. 3, the PMOS transistor P1, which receives the TTL level input signal from the outside of the chip as the gate terminal, is connected between the first node A and the node B, and is connected between the node B and the ground power supply terminal Vss. The first NMOS transistor N2, which receives the input signal through the gate terminal, is connected to the second NMOS transistor N3, which receives the control signal CS through the gate terminal between the node B and the ground power supply terminal Vss. This connection structure is provided, and the node B is configured with an inverter 31 connected to its input terminal and outputting an output signal to the output terminal. The configuration is the same as the corresponding configuration of the prior art shown in FIG.

The present invention constitutes a third NMOS transistor N1 connected between the supply power supply Vcc and the first node A in this configuration, and the third NMOS transistor N1 is turned on when the input buffer is enabled. The inverted signal of the control signal CS is input to the gate terminal to be turned off when the input buffer is disabled. The PMOS transistors P2 and NMOS transistor N4 are inverters which invert the control signal CS and output them to the gate terminal of the third NMOS transistor N1. A second NMOS transistor P3 is connected between the power supply terminal Vcc and the node B to receive the output of the inverter 31 as the gate terminal.

With this configuration, the input buffer of the present invention performs a stable operation while reducing the constant current, and this operation will be described in detail below.

(1) When control signal CS is logic 'low'

At this time, the input buffer is enabled and the output signal is determined according to the logic level of the input signal.

First, when the input signal is input to the TTL level logic 'high' (approximately 2.4V), the first NMOS transistor N2 is turned on and the PMOS transistor P1 is turned off so that the node B is at a logic 'low' level. . At this time, conventionally, since the potential of the first node A was almost at the supply voltage Vcc level, the PMOS transistor P1 was weakly turned on without maintaining the turn-off state. However, in the present invention, the third NMOS transistor N1 is turned on. Since the first node A has the voltage level of the supply potential Vcc -V _TN (threshold voltage of the third NMOS transistor N1), the PMOS transistor P1 is not weakly turned on. Therefore, it is possible to prevent the constant current from occurring. In this embodiment, the threshold voltage of the third NMOS transistor N1 should be composed of a transistor having a value of about 0.8 to 1.2V, but this can be suitably configured in view of the characteristics of the circuit.

Next, when the input signal is input to the TTL level logic 'low' (approximately 0.8V), the first NMOS transistor N2 is turned off and the first PMOS transistor P1 is turned on so that the node B is logic 'high'. 'Becomes the level. At this time, since the first node A has a voltage level of Vcc-V _TN , the second node B can not reach the supply voltage Vcc, and the second node B is prevented by the second NMOS transistor P3. Is compensated for by full Vcc. As a result, the second node B allows a full swing between the supply voltage and the ground voltage according to the input signal.

(2) When control signal CS is logic 'high'

At this time, the third NMOS transistor N1 is turned off to disable the input buffer (standby state), and the second NMOS transistor N3 is turned on so that the second node B is at a stable low level.

4 is a graph showing the current characteristics of the input buffer of the present invention, which shows the current flowing through each transistor with respect to the power supply voltage Vcc and the constant current Iss, and a lower constant current Icc is generated compared to the second degree. It can be seen.

The present invention made as described above has the effect of realizing a low power memory device by reducing the current consumption generated in the input buffer of the memory device.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a conventional input buffer circuit diagram,

2 is a graph of the current characteristics of FIG.

3 is an input buffer circuit diagram according to an embodiment of the present invention;

4 is a graph of the current characteristics of FIG.

* Explanation of symbols for main parts of the drawings

P1, P2, P3: PMOS Transistor

N1, N2, N3, N4: NMOS transistor

31: inverter

Claims (3)

In the input buffer of the semiconductor memory device, A first node A, a second node B, and an output terminal; A first PMOS transistor (P1) receiving an input signal having a TTL level from the outside of the chip as a gate terminal and connected between the first node and the second node; A first NMOS transistor N2 connected between the second node and a ground power terminal and receiving the input signal as a gate terminal; A second NMOS transistor N3 receiving a control signal CS through a gate terminal and connected between the second node and the ground power supply terminal; An inverter 31 having its input terminal connected to the second node and outputting an output signal to the output terminal; And It is connected between a supply power supply terminal and the first node, and receives the inverted signal of the control signal to the gate terminal by the inverter (P2, N4), and down by its threshold voltage at the supply voltage when the input buffer is enabled A third NMOS transistor N1 transferring a voltage level to the first node. Input buffer of the semiconductor memory device comprising a. The method of claim 1, In order to compensate for the logic high voltage level of the second node, the output of the inverter 31 is input to the gate terminal and further comprises a second PMOS transistor (P3) connected between a supply power supply terminal and the second node. Input buffer of semiconductor memory device. The method of claim 1, The third NMOS transistor has a threshold voltage of 0.8 to 1.2V input buffer of the semiconductor memory device.