KR100318316B1 - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
- Publication number
- KR100318316B1 KR100318316B1 KR1019990011585A KR19990011585A KR100318316B1 KR 100318316 B1 KR100318316 B1 KR 100318316B1 KR 1019990011585 A KR1019990011585 A KR 1019990011585A KR 19990011585 A KR19990011585 A KR 19990011585A KR 100318316 B1 KR100318316 B1 KR 100318316B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- layer
- contact hole
- interlayer insulating
- plug
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 72
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000004140 cleaning Methods 0.000 abstract description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
- 239000007789 gas Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Abstract
본 발명은 커패시터의 제조방법에 관한 것으로서 게이트전극 및 불순물영역을 포함하는 트랜지스터가 형성된 반도체기판 상에 층간절연층을 형성하는 공정과, 상기 층간절연층을 선택식각하여 상기 불순물영역을 노출시키는 제 1 접촉홀을 형성하고 상기 접촉홀 내에 플러그를 형성하는 공정과, 상기 층간절연층 상에 희생층을 형성하고 상기 플러그가 노출되도록 패터닝하여 제 2 접촉홀을 형성하는 공정과, 상기 제 2 접촉홀의 내부 표면에 반도체층을 형성하고 상기 희생층을 제거하는 공정과, 상기 반도체층을 결정화하면서 표면에 돌출부를 형성하고 상기 다결정실리콘층의 표면에 형성된 자연산화막을 H2가스를 공급하여 실리콘으로 환원시켜 제거하는 공정과, 상기 다결정실리콘층에 불순물을 고농도로 도핑하여 하부전극을 형성하는 공정을 구비한다. 따라서, 자연산화막을 H2가스를 흘려 환원시켜 제거하므로 반구형(hemispical grain)의 돌출부가 세정 공정 중에 부러지거나 떨어지지 않아 인접하는 커패시터의 하부전극과 단락되는 것을 방지한다.The present invention relates to a method of manufacturing a capacitor, comprising: forming an interlayer insulating layer on a semiconductor substrate on which a transistor including a gate electrode and an impurity region is formed; and firstly exposing the impurity region by selectively etching the interlayer insulating layer. Forming a contact hole and forming a plug in the contact hole; forming a sacrificial layer on the interlayer insulating layer and patterning the plug to expose the plug; and forming a second contact hole; Forming a semiconductor layer on the surface and removing the sacrificial layer; and forming a protrusion on the surface while crystallizing the semiconductor layer, and removing the natural oxide film formed on the surface of the polycrystalline silicon layer by supplying H 2 gas to reduce the silicon And doping impurities in the polysilicon layer at a high concentration to form a lower electrode. The rain. Therefore, the natural oxide film is removed by flowing H 2 gas, thereby preventing the hemispherical grain protrusion from being broken or falling during the cleaning process, thereby preventing the natural oxide film from being shorted with the lower electrode of the adjacent capacitor.
Description
본 발명은 반도체장치의 커패시터 제조방법에 관한 것으로서, 특히, 커패시턴스을 증가시킬 수 있는 커패시터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a capacitor capable of increasing capacitance.
반도체장치의 고집적화에 따라 셀(cell) 면적이 축소되어도 커패시터가 일정한 커패시턴스를 갖도록 축전 밀도를 증가시키기 위한 많은 연구가 진행되고 있다. 커패시턴스를 증가시키기 위해서는 커패시터를 적층(stacked) 또는 트렌치(trench) 등의 3차원 구조로 형성하여 유전체의 표면적을 증가시켰다.Many studies have been conducted to increase the storage density so that the capacitor has a constant capacitance even if the cell area is reduced due to the high integration of the semiconductor device. In order to increase the capacitance, the capacitor was formed into a three-dimensional structure such as stacked or trenched to increase the surface area of the dielectric.
또한, 유전체의 표면적을 증가시키기 위해 하부전극의 표면에 반구형의 돌출부를 형성하였다.In addition, hemispherical protrusions were formed on the surface of the lower electrode to increase the surface area of the dielectric.
하부전극의 표면에 반구형의 돌출부를 형성하는 방법은 반도체기판 상에 트랜지스터의 소오스영역으로 사용되는 불순물이 고농도로 도핑된 불순물영역을 노출시키는 제 1 접촉홀을 갖는 층간절연층을 형성하고, 이 제 1 접촉홀 내에 플러그를 형성한다. 그리고, 층간절연층 상에 플러그를 노출시키는 제 2 접촉홀을 갖는 희생층을형성하고, 이 제 2 접촉홀 내에 불순물이 도핑되지 않거나 저농도로 도핑된 비정질실리콘층을 형성한다. 희생층을 습식 방법에 의해 선택적으로 제거한 후 비정질실리콘층을 SiH4가스를 흘리면서 열처리하여 다결정실리콘층으로 결정화시키면서 표면에 반구형(hemispical grain)의 돌출부를 형성한다.The method of forming a hemispherical protrusion on the surface of a lower electrode forms an interlayer insulating layer having a first contact hole exposing an impurity region doped with a high concentration of impurities used as a source region of a transistor on a semiconductor substrate. 1 Plug into the contact hole. A sacrificial layer having a second contact hole for exposing the plug is formed on the interlayer insulating layer, and an amorphous silicon layer doped with impurities or lightly doped with impurities is formed in the second contact hole. After the sacrificial layer is selectively removed by a wet method, the amorphous silicon layer is heat treated while flowing SiH 4 gas to crystallize into a polycrystalline silicon layer to form a hemispherical grain protrusion on the surface.
반구형의 돌출부가 형성된 다결정실리콘층을 H2O＋H2O2＋NH3OH 또는 H2O＋H2O2＋NH3OH＋HF 등의 용액으로 세정하여 표면에 형성되는 자연산화막을 제거한다. 그리고, 다결정실리콘층에 인(P) 등의 불순물을 고농도로 도핑하는 데, 이 도핑된 다결정실리콘층은 커패시터의 하부전극이 된다. 상기에서 반구형의 돌출부가 형성된 다결정실리콘층의 표면에 형성된 자연산화막은 불순물이 도핑되는 것을 방지하므로 제거한다.The polysilicon layer on which the hemispherical protrusions are formed is washed with a solution such as H 2 O + H 2 O 2 + NH 3 OH or H 2 O + H 2 O 2 + NH 3 OH + HF to remove the natural oxide film formed on the surface. The polysilicon layer is heavily doped with impurities such as phosphorus (P), and the doped polysilicon layer becomes a lower electrode of the capacitor. The natural oxide film formed on the surface of the polysilicon layer in which the hemispherical protrusion is formed is removed because it prevents the doping of impurities.
상술한 바와 같이 종래 기술은 비정질실리콘을 열처리하여 다결정실리콘층으로 결정화하면서 표면에 반구형(hemispical grain)의 돌출부가 형성되도록하여 하부전극을 표면적을 증가에 따라 유전층의 표면적을 증가시키므로 커패시터의 커패시턴스를 증가시켰다.As described above, the prior art heat-treats amorphous silicon to crystallize into a polysilicon layer so that protrusions of hemispherical grains are formed on the surface, thereby increasing the surface area of the dielectric layer as the lower electrode increases the surface area, thereby increasing the capacitance of the capacitor. I was.
그러나, 상술한 종래의 커패시터의 제조방법은 희생층과 접촉하는 부분에서 첨점을 이루고 제 2 접촉홀의 가운데로 경사진 부분이 얇아진 부분과 표면에 형성된 반구형(hemispical grain)의 돌출부가 세정 공정 중에 부러지거나 떨어져 인접하는 커패시터의 하부전극과 단락되는 문제점이 있었다.However, in the above-described conventional method of manufacturing a capacitor, the thinning portion formed in the contact with the sacrificial layer and the inclined portion in the middle of the second contact hole and the hemispherical grain protrusion formed on the surface are broken during the cleaning process. There was a problem of shorting away from the lower electrode of the adjacent capacitor.
따라서, 본 발명의 목적은 인접하는 하부전극들이 전기적으로 단락되는 것을 방지할 수 있는 커패시터의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor that can prevent the adjacent lower electrodes from being electrically shorted.
상기 목적을 달성하기 위한 본 발명에 따른 커패시터의 제조방법은 게이트전극 및 불순물영역을 포함하는 트랜지스터가 형성된 반도체기판 상에 층간절연층을 형성하는 공정과, 상기 층간절연층을 선택식각하여 상기 불순물영역을 노출시키는 제 1 접촉홀을 형성하고 상기 접촉홀 내에 플러그를 형성하는 공정과, 상기 층간절연층 상에 희생층을 형성하고 상기 플러그가 노출되도록 패터닝하여 제 2 접촉홀을 형성하는 공정과, 상기 제 2 접촉홀의 내부 표면에 반도체층을 형성하고 상기 희생층을 제거하는 공정과, 상기 반도체층을 결정화하면서 표면에 돌출부를 형성하고 상기 다결정실리콘층의 표면에 형성된 자연산화막을 H2가스를 공급하여 실리콘으로 환원시켜 제거하는 공정과, 상기 다결정실리콘층에 불순물을 고농도로 도핑하여 하부전극을 형성하는 공정을 구비한다.A method of manufacturing a capacitor according to the present invention for achieving the above object is a step of forming an interlayer insulating layer on a semiconductor substrate on which a transistor including a gate electrode and an impurity region is formed, and selectively etching the interlayer insulating layer to the impurity region Forming a first contact hole for exposing the light source and forming a plug in the contact hole, forming a sacrificial layer on the interlayer insulating layer and patterning the plug to expose the second contact hole; Forming a semiconductor layer on the inner surface of the second contact hole and removing the sacrificial layer; forming a protrusion on the surface while crystallizing the semiconductor layer, and supplying H 2 gas to the natural oxide film formed on the surface of the polysilicon layer; Reducing to silicon and removing the lower electrode by doping impurities to the polysilicon layer at a high concentration. It includes a step of forming.
도 1a 내지 도 1e는 본 발명에 따른 커패시터의 제조방법을 도시하는 공정도1A to 1E are process diagrams illustrating a method of manufacturing a capacitor according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명에 따른 커패시터의 제조방법을 도시하는 공정도이다.1A to 1E are process diagrams illustrating a method of manufacturing a capacitor according to the present invention.
도 1a를 참조하면, 소오스 및 드레인영역으로 사용되는 N형의 불순물이 고농도로 도핑된 불순물영역(13)을 포함하는 트랜지스터(도시되지 않음)가 형성된 P형의 반도체기판(11) 상에 산화실리콘 또는 질화실리콘 등을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 증착하여 층간절연층(15)을 형성한다. 그리고, 층간절연층(15)을 포토리쏘그래피 방법으로 패터닝하여 불순물영역(13),즉, 소오스영역을 노출시키는 제 1 접촉홀(17)을 형성한다.Referring to FIG. 1A, silicon oxide is formed on a P-type semiconductor substrate 11 having a transistor (not shown) including an impurity region 13 doped with a high concentration of N-type impurities used as a source and a drain region. Alternatively, silicon nitride or the like is deposited by chemical vapor deposition (hereinafter, referred to as CVD) to form an interlayer insulating layer 15. The interlayer insulating layer 15 is patterned by a photolithography method to form the first contact hole 17 exposing the impurity region 13, that is, the source region.
층간절연층(15) 상에 불순물이 도핑된 다결정실리콘을 제 1 접촉홀(17)을 채우도록 CVD 방법으로 증착한다. 이 때, 다결정실리콘은 제 1 접촉홀(17)에 의해 노출된 불순물영역(13)과 접촉된다. 그리고, 다결정실리콘을 층간절연층(15)의 표면이 노출되고 제 1 접촉홀(17)에만 잔류되도록 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법으로 에치 백하여 플러그(19)를 형성한다.Impurity doped polysilicon is deposited on the interlayer insulating layer 15 by CVD to fill the first contact hole 17. At this time, the polysilicon is in contact with the impurity region 13 exposed by the first contact hole 17. The plug 19 is etched back by etching the polysilicon using a reactive ion etching method so that the surface of the interlayer insulating layer 15 is exposed and remains only in the first contact hole 17. Form.
도 1b를 참조하면, 층간절연층(15) 및 플러그(19) 상에 층간절연층(15)을 형성하는 물질과 식각 선택비가 다른 질화실리콘 또는 산화실리콘 등을 CVD 방법으로 증착하여 희생층(21)을 형성한다. 희생층(21)을 포토리쏘그래피 방법으로 패터닝하여 플러그(19)를 노출시키는 제 2 접촉홀(23)을 형성한다.Referring to FIG. 1B, a sacrificial layer 21 is formed by depositing silicon nitride or silicon oxide having a different etching selectivity from a material forming the interlayer insulating layer 15 and the plug 19 on the interlayer insulating layer 15 and the plug 19 by a CVD method. ). The sacrificial layer 21 is patterned by photolithography to form a second contact hole 23 exposing the plug 19.
제 2 접촉홀(23)의 내부 표면을 포함하는 희생층(21) 상에 CVD 방법에 의해 비정질실리콘을 증착하여 반도체층(25)을 형성한다. 상기에서 비정질실리콘으로 이루어진 반도체층(25)은 불순물이 도핑되지 않거나 저농도로 도핑되며 제 2 접촉홀(23)에 의해 노출된 플러그(19)와 접촉되게 형성된다.The semiconductor layer 25 is formed by depositing amorphous silicon on the sacrificial layer 21 including the inner surface of the second contact hole 23 by the CVD method. The semiconductor layer 25 made of amorphous silicon is formed in contact with the plug 19 which is not doped with impurities or is lightly doped and exposed by the second contact hole 23.
도 1c를 참조하면, 비정질실리콘으로 이루어진 반도체층(25)을 희생층(21)의 상부 표면이 노출되도록 RIE 방법 등으로 에치백하여 제 2 접촉홀(23) 내에만 잔류되도록 한다. 상기에서 제 2 접촉홀(23) 바닥면 상에 형성된 반도체층(25)이 손상되는 것을 방지하기 위해 제 2 접촉홀(23) 내에 포토레지스트 또는 유기물질을 채운 상태에서 에치백한 후에 제거한다. 이 때, 제 2 접촉홀(23) 내에 잔류하는 반도체층(25)은 희생층(21)과 접촉하는 부분이 제 2 접촉홀(23)의 가운데 부분 보다 식각 속도가 빠르다. 그러므로, 반도체층(25)은 상부 표면이 희생층(21)과 접촉하는 부분에서 첨점을 이루고 제 2 접촉홀(23)의 가운데 부분 쪽으로 경사지게 형성된다.Referring to FIG. 1C, the semiconductor layer 25 made of amorphous silicon is etched back by RIE or the like so as to expose the upper surface of the sacrificial layer 21 so as to remain only in the second contact hole 23. In order to prevent the semiconductor layer 25 formed on the bottom surface of the second contact hole 23 from being damaged, the second contact hole 23 is removed after being etched back while the photoresist or organic material is filled. At this time, in the semiconductor layer 25 remaining in the second contact hole 23, the portion in contact with the sacrificial layer 21 has a faster etching speed than the center portion of the second contact hole 23. Therefore, the semiconductor layer 25 is formed at the point where the upper surface is in contact with the sacrificial layer 21 and is inclined toward the center portion of the second contact hole 23.
희생층(21)을 습식 방법에 의해 층간절연층(15)과 선택적으로 제거한다.The sacrificial layer 21 is selectively removed from the interlayer insulating layer 15 by a wet method.
도 1d를 참조하면, 비정질실리콘의 반도체층(25)을 SiH4가스를 흘리면서 열처리한다. 이 때, 비정질실리콘의 반도체층(25)은 결정화되어 다결정실리콘층(27)으로 변화되면서 표면에 반구형(hemispical grain)으로 돌출부(28)가 형성된다. 상기에서 비정질실리콘으로 이루어진 반도체층(25)은 불순물이 도핑되지 않거나 저농도로 도핑되어 있으므로 표면에 반구형(hemispical grain)의 돌출부(28) 형성이 용이하다.Referring to FIG. 1D, the semiconductor layer 25 of amorphous silicon is heat treated while flowing SiH 4 gas. At this time, the semiconductor layer 25 of amorphous silicon is crystallized and changed into the polysilicon layer 27, and the protrusions 28 are formed in a hemispherical grain on the surface. Since the semiconductor layer 25 made of amorphous silicon is not doped with impurities or is lightly doped, it is easy to form a hemispherical grain protrusion 28 on the surface.
돌출부(28)를 포함하는 다결정실리콘층(27)의 표면에 형성된 자연산화막(29)을 H2의 건식 방법에 의해 제거한다. 즉, 진공 상태에서 800∼1000℃ 정도의 온도에서 1∼10분 정도 가열한 후 H2가스를 흘리면 자연산화막(29)의 산소 원자(O2)와 반응하여 H2O 상태로 증발하므로 자연산화막(29)은 실리콘으로 환원된다. 따라서, 돌출부(28)를 포함하는 다결정실리콘층(27)의 표면에 자연산화막(29)이 제거된다.The natural oxide film 29 formed on the surface of the polysilicon layer 27 including the protrusions 28 is removed by a dry method of H 2 . That is, after heating for about 1 to 10 minutes at a temperature of about 800 to 1000 ℃ in a vacuum state and flowing H 2 gas reacts with oxygen atoms (O 2 ) of the natural oxide film 29 and evaporates to H 2 O state, so that the natural oxide film 29 is reduced to silicon. Therefore, the native oxide film 29 is removed from the surface of the polysilicon layer 27 including the protrusions 28.
도 1e를 참조하면, 돌출부(28)를 갖는 다결정실리콘층(27)에 인(P) 등의 불순물을 고농도로 도핑하여 커패시터의 하부전극(31)을 형성한다. 상기에서 하부전극(31)은 표면이 반구형(hemispical grain)의 돌출부(28)를 가지므로 표면적이 증가된다.Referring to FIG. 1E, a polysilicon layer 27 having a protrusion 28 is doped with impurities such as phosphorus (P) at a high concentration to form a lower electrode 31 of a capacitor. Since the lower electrode 31 has a hemispherical grain-shaped protrusion 28, the surface area is increased.
도시되지는 않았지만, 이 후에, 하부전극(31) 표면에 유전층과 상부전극을 형성한다.Although not shown, a dielectric layer and an upper electrode are formed on the surface of the lower electrode 31 thereafter.
상술한 바와 같이 본 발명은 비정질실리콘을 열처리하여 다결정실리콘층으로 결정화시키면서 표면에 돌출부를 형성하고 돌출부를 포함하는 다결정실리콘층 표면에 형성된 자연산화막을 가열하면서 H2가스를 흘려 환원시키므로 세정되도록 한다.As described above, the present invention heats amorphous silicon to crystallize it into a polysilicon layer, thereby forming a protrusion on the surface and cleaning the natural oxide film formed on the surface of the polysilicon layer including the protrusion by flowing H 2 gas and reducing the same.
따라서, 본 발명은 자연산화막을 H2가스를 흘려 환원시켜 제거하므로 반구형(hemispical grain)의 돌출부가 세정 공정 중에 부러지거나 떨어지지 않아 인접하는 커패시터의 하부전극과 단락되는 것을 방지하는 잇점이 있다.Therefore, the present invention has the advantage of preventing the natural oxide film is reduced by flowing H 2 gas to prevent the hemispherical grain protruding portion is not broken or falling during the cleaning process and short-circuit with the lower electrode of the adjacent capacitor.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990011585A KR100318316B1 (en) | 1999-04-02 | 1999-04-02 | Method for fabricating capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990011585A KR100318316B1 (en) | 1999-04-02 | 1999-04-02 | Method for fabricating capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000065369A KR20000065369A (en) | 2000-11-15 |
| KR100318316B1 true KR100318316B1 (en) | 2001-12-22 |
Family
ID=19578629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990011585A KR100318316B1 (en) | 1999-04-02 | 1999-04-02 | Method for fabricating capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100318316B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322527A (en) * | 1989-06-20 | 1991-01-30 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07221034A (en) * | 1994-01-31 | 1995-08-18 | Nec Corp | Manufacture of semiconductor device |
| JPH1074701A (en) * | 1996-08-30 | 1998-03-17 | Nec Corp | Semiconductor manufacturing apparatus and manufacture of semiconductor device |
| KR19990011930A (en) * | 1997-07-25 | 1999-02-18 | 윤종용 | Cleaning composition for manufacturing semiconductor device and manufacturing method of semiconductor device using same |
-
1999
- 1999-04-02 KR KR1019990011585A patent/KR100318316B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0322527A (en) * | 1989-06-20 | 1991-01-30 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07221034A (en) * | 1994-01-31 | 1995-08-18 | Nec Corp | Manufacture of semiconductor device |
| JPH1074701A (en) * | 1996-08-30 | 1998-03-17 | Nec Corp | Semiconductor manufacturing apparatus and manufacture of semiconductor device |
| KR19990011930A (en) * | 1997-07-25 | 1999-02-18 | 윤종용 | Cleaning composition for manufacturing semiconductor device and manufacturing method of semiconductor device using same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000065369A (en) | 2000-11-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5324673A (en) | Method of formation of vertical transistor | |
| US6365452B1 (en) | DRAM cell having a vertical transistor and a capacitor formed on the sidewalls of a trench isolation | |
| TWI390666B (en) | Method for fabricating soi device | |
| US6319772B1 (en) | Method for making low-leakage DRAM structures using selective silicon epitaxial growth (SEG) on an insulating layer | |
| JP2000058652A (en) | Manufacture of contact hole for semiconductor device | |
| JPH08139278A (en) | Manufacture of semiconductor device | |
| US6489646B1 (en) | DRAM cells with buried trench capacitors | |
| US5926711A (en) | Method of forming an electrode of a semiconductor device | |
| KR0171072B1 (en) | Semiconductor memory cell & its fabrication method | |
| KR100318316B1 (en) | Method for fabricating capacitor | |
| KR100824136B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| US20060014389A1 (en) | Method of manufacturing semiconductor device | |
| KR100656715B1 (en) | Semiconductor memory device, and fabrication method thereof | |
| KR940006670B1 (en) | Manufacturing method of semiconductor device | |
| KR100360184B1 (en) | Method for manufacturing semiconductor integrated circuit device | |
| US10546923B2 (en) | Semiconductor assemblies having semiconductor material regions with contoured upper surfaces; and methods of forming semiconductor assemblies utilizing etching to contour upper surfaces of semiconductor material | |
| KR0151257B1 (en) | Method for manufacturing a semiconductor memory device | |
| KR100217919B1 (en) | Fabricating method for capacitor stroage electrode in semiconductor device | |
| KR0162597B1 (en) | Method for fabricating a capacitor of semiconductor device | |
| KR100275947B1 (en) | Method of fabricating capacitor for semiconductor device | |
| KR100275938B1 (en) | Method of fabricating capacitor | |
| KR0168771B1 (en) | Storage electrode fabrication method of semiconductor | |
| KR100361518B1 (en) | Method of fabricating a capacitor in a semiconductor device | |
| KR20000065368A (en) | Method for fabricating capacitor | |
| KR100190193B1 (en) | Capacitor stroage electrode fabrication method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20091126 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |