KR100318272B1 - Method for forming fine pattern of semiconductor device - Google Patents
Method for forming fine pattern of semiconductor device Download PDFInfo
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- KR100318272B1 KR100318272B1 KR1019990060294A KR19990060294A KR100318272B1 KR 100318272 B1 KR100318272 B1 KR 100318272B1 KR 1019990060294 A KR1019990060294 A KR 1019990060294A KR 19990060294 A KR19990060294 A KR 19990060294A KR 100318272 B1 KR100318272 B1 KR 100318272B1
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000010408 film Substances 0.000 claims abstract description 77
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000000059 patterning Methods 0.000 claims abstract description 18
- 239000010409 thin film Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims 2
- 238000003079 width control Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
본 발명은 라인과 같은 패턴의 선폭 제어가 용이한 반도체 소자의 미세 패턴 형성방법을 개시하며, 개시된 본 발명의 반도체 소자의 미세 패턴 형성방법은, 반도체 기판 상에 패터닝용 박막, 하드 마스크막, 실리콘막 및 산화막을 차례로 형성하는 단계; 상기 실리콘막을 노출시키는 콘택홀이 형성되도록, 상기 산화막을 패터닝하는 단계; 상기 콘택홀의 측벽에 스페이서를 형성하는 단계; 상기 콘택홀에 의해 노출된 실리콘막 부분에 실리콘 에피층을 성장시키는 단계; 상기 스페이서 및 산화막을 제거하는 단계; 상기 실리콘 에피층을 마스크로해서 상기 실리콘막과 하드 마스크막을 식각하는 단계; 및 상기 하드 마스크막을 마스크로해서, 상기 패터닝용 박막을 식각하는 단계를 포함하여 이루어진다.The present invention discloses a method for forming a fine pattern of a semiconductor device, the line width control of a pattern such as a line is easy, and the disclosed method for forming a fine pattern of a semiconductor device of the present invention, a thin film for patterning, a hard mask film, silicon on a semiconductor substrate Sequentially forming a film and an oxide film; Patterning the oxide film to form a contact hole exposing the silicon film; Forming a spacer on sidewalls of the contact hole; Growing a silicon epitaxial layer on a portion of the silicon film exposed by the contact hole; Removing the spacers and the oxide film; Etching the silicon layer and the hard mask layer using the silicon epitaxial layer as a mask; And etching the patterning thin film using the hard mask layer as a mask.
Description
본 발명은 반도체 소자의 미세 패턴 형성방법에 관한 것으로, 보다 상세하게는, 라인과 같은 패턴의 선폭 제어가 용이한 반도체 소자의 미세 패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device in which line width control of a pattern such as a line is easy.
종래의 미세 패턴 형성방법은, 단순히, 축소 노광 장치에서 사용되는 광원을 짧은 파장의 것을 선택하는 방법으로 진행되어 왔다. 예를들어, 종래에는 지-라인 (G-line : λ=435㎚) 또는 아이-라인(I-line : λ=365㎚)의 광원이 주로 사용되어 왔는데, 상기한 광원들을 이용한 축소 노광 장치는 그 분해능이 고집적 소자에서 요구되는 미세 선폭의 패턴을 형성할 수 없으므로, 최근에는 축소 노광 장치의 광원으로서 케이알에프(KrF : λ=248㎚) 또는 에이알에프(ArF : λ=193㎚) 등을 이용하게 되었고, 더 나아가, 전자빔, 이온빔 및 X-ray와 같은 비광학적 광원도 이용하게 되었다.The conventional fine pattern forming method has simply progressed to a method of selecting a light source having a short wavelength as a light source used in the reduced exposure apparatus. For example, conventionally, a light source of G-line (G-line (λ = 435 nm) or I-line (λ = 365 nm) has been mainly used. Since the resolution cannot form the pattern of the fine line width required in the highly integrated device, in recent years KF (KrF: λ = 248 nm) or ALF (ArF: λ = 193 nm) or the like is used as a light source of a reduced exposure apparatus. In addition, non-optical light sources such as electron beams, ion beams and X-rays have also been used.
그러나, 상기한 방법은 그 적용 범위가 넓어지기는 하겠지만, 장비에 소요되는 투자 비용이 크므로, 그 이용에 어려움이 있다.However, the above method, although the scope of application will be widened, it is difficult to use, because the investment cost for the equipment is large.
한편, 상기한 방법 이외에, 식각 마스크로 이용되는 감광막을 플로우시키거나 또는 에슁(ashing)시켜, 최종적으로 얻게 되는 패턴의 폭을 줄이는 방법도 이용되고 있다.On the other hand, in addition to the above-described method, a method of reducing the width of the pattern finally obtained by flowing or ashing the photosensitive film used as an etching mask is also used.
먼저, 전자의 방법은, 도 1a에 도시된 바와 같이, 도전막(1) 상에 개구부를 갖는 감광막 패턴(2)을 형성하고, 그런다음, 도 1b에 도시된 바와 같이, 소정 온도에서 상기 감광막 패턴을 플로우시켜, 감소된 개구부 폭을 갖는 감광막 패턴(2a)을 형성시킴으로써, 후속에서 상기 감광막 패턴(2a)을 마스크로하는 식각 공정을 통해얻어지는 패턴의 폭이 감소되도록 한다. 여기서, 도면부호 A는 초기 개구부의 폭을 나타내고, B는 플로우에 의해 감소된 개구부의 폭을 나타낸다.First, the former method forms a photosensitive film pattern 2 having an opening on the conductive film 1, as shown in FIG. 1A, and then, as shown in FIG. 1B, the photosensitive film at a predetermined temperature. The pattern is flowed to form a photoresist pattern 2a having a reduced opening width so that the width of the pattern obtained through an etching process using the photoresist pattern 2a as a mask is subsequently reduced. Here, reference numeral A denotes the width of the initial opening, and B denotes the width of the opening reduced by the flow.
후자의 방법은, 도 2a에 도시된 바와 같이, 도전막(1) 상에 감광막 패턴(12)을 형성하고, 그런다음, 도 2b에 도시된 바와 같이, O2가스를 이용한 에슁 공정을 통해 감광막 패턴(12a)의 폭을 감소시킴으로써, 상기 감소된 폭을 갖는 감광막 패턴(12a)을 마스크로 하는 식각 공정을 통해 얻어지는 패턴의 폭이 감소되도록 한다. 여기서, 도면부호 A는 초기 감광막 패턴의 폭을 나타내고, B는 에슁에 의해 감소된 감광막 패턴의 폭을 나타낸다.The latter method, as shown in Figure 2a, a conductive film (1) to form a photoresist pattern 12 on the, then, as shown in Figure 2b, O photosensitive film through eswing process using a second gas By reducing the width of the pattern 12a, the width of the pattern obtained through the etching process using the photosensitive film pattern 12a having the reduced width as a mask is reduced. Here, reference numeral A denotes the width of the initial photosensitive film pattern, and B denotes the width of the photosensitive film pattern reduced by etching.
그러나, 감광막의 플로우를 이용하는 방법은 널리 이용되는 방법이며, 아울러, 그 신뢰성이 우수하기는 하지만, 콘택홀 이외의 패턴, 예를들어, 라인과 같은 패턴을 형성하는데는 그 적용이 곤란한 문제점이 있고, 그리고, 감광막의 에슁을 이용하는 방법은 라인과 같은 패턴을 형성하는데는 적용 가능하지만, 에슁에 의해 얻어지는 감광막 패턴의 폭의 제어가 어려움은 물론, 에슁에 의해 얻어지는 감광막 패턴의 두께가 얇아지는 것에 기인하여 후속의 식각 공정이 안정하지 못하다는 문제점이 있다. 결과적으로, 라인과 같은 패턴을 형성하기 위한 종래의 방법은 현재로서는 선폭의 제어가 어려우며, 아울러, 그 재현성이 나쁘다는 문제점이 있다.However, the method of using the flow of the photoresist film is a widely used method, and although the reliability thereof is excellent, there is a problem that its application is difficult to form patterns other than contact holes, for example, lines. In addition, the method of using the edge of the photosensitive film is applicable to forming a line-like pattern, but it is difficult to control the width of the photosensitive film pattern obtained by the edge, as well as the thickness of the photosensitive film pattern obtained by the edge is reduced. There is a problem that the subsequent etching process is not stable. As a result, the conventional method for forming a pattern such as a line has a problem that it is difficult to control the line width at present, and the reproducibility thereof is poor.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 라인과 같은 패턴의 선폭 제어가 용이한 반도체 소자의 미세 패턴 형성방법을 제공하는데,그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a fine pattern of a semiconductor device, in which line width control of a pattern such as a line is easy to be solved.
도 1a 및 도 1b는 종래 기술에 따른 미세 패턴 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a method for forming a fine pattern according to the prior art.
도 2a 및 도 2b는 종래 다른 기술에 따른 미세 패턴 형성방법을 설명하기 위한 단면도.2A and 2B are cross-sectional views illustrating a method for forming a fine pattern according to another conventional technology.
도 3a 내지 도 3f는 본 발명의 실시예에 따른 미세 패턴 형성방법을 설명하기 위한 각 공정별 단면도.3A to 3F are cross-sectional views for each process for explaining a method for forming a fine pattern according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
21 : 반도체 기판 22 : 패터닝용 박막21 semiconductor substrate 22 thin film for patterning
22a : 라인 패턴 23 : 하드 마스크막22a: line pattern 23: hard mask film
24 : 실리콘막 25 : 산화막24 silicon film 25 oxide film
26 : 감광막 패턴 27 : 콘택홀26: photosensitive film pattern 27: contact hole
28 : 스페이서 29 : 실리콘 에피층28 spacer 29 silicon epi layer
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 미세 패턴 형성방법은, 반도체 기판 상에 패터닝용 박막, 하드 마스크막, 실리콘막 및 산화막을 차례로 형성하는 단계; 상기 실리콘막을 노출시키는 콘택홀이 형성되도록, 상기 산화막을 패터닝하는 단계; 상기 콘택홀의 측벽에 스페이서를 형성하는 단계; 상기 콘택홀에 의해 노출된 실리콘막 부분에 실리콘 에피층을 성장시키는 단계; 상기 스페이서 및 산화막을 제거하는 단계; 상기 실리콘 에피층을 마스크로해서 상기 실리콘막과 하드 마스크막을 식각하는 단계; 및 상기 하드 마스크막을 마스크로해서, 상기 패터닝용 박막을 식각하는 단계를 포함하여 이루어진다.Method for forming a fine pattern of a semiconductor device of the present invention for achieving the above object comprises the steps of sequentially forming a patterning thin film, a hard mask film, a silicon film and an oxide film on a semiconductor substrate; Patterning the oxide film to form a contact hole exposing the silicon film; Forming a spacer on sidewalls of the contact hole; Growing a silicon epitaxial layer on a portion of the silicon film exposed by the contact hole; Removing the spacers and the oxide film; Etching the silicon layer and the hard mask layer using the silicon epitaxial layer as a mask; And etching the patterning thin film using the hard mask layer as a mask.
본 발명에 따르면, 스페이서 및 선택적 에피텍셜 성장법을 이용하여 선폭의 제어가 가능한 하드 마스크막을 형성시킬 수 있기 때문에, 상기 하드 마스크막을 식각 마스크로하는 식각 공정을 통해 미세 선폭을 갖는 라인 패턴을 형성할 수 있고, 아울러, 상기 라인 패턴 형성의 재현성을 향상시킬 수 있다.According to the present invention, since a hard mask film capable of controlling the line width can be formed using a spacer and a selective epitaxial growth method, a line pattern having a fine line width can be formed through an etching process using the hard mask film as an etching mask. In addition, the reproducibility of the line pattern formation can be improved.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3f는 본 발명의 실시예에 따른 반도체 소자의 미세 패턴 형성방법을 설명하기 위한 각 공정별 단면도이다.3A to 3F are cross-sectional views of respective processes for describing a method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention.
먼저, 도 3a에 도시된 바와 같이, 반도체 기판(21) 상에 패터닝용 박막(22)을 형성하고, 그런다음, 상기 패터닝용 박막(22) 상에 순차적으로 하드마스크막(23), 박막의 실리콘막(24) 및 산화막(25)을 각각 500 내지 2,000Å, 100 내지 300Å, 그리고, 1,000 내지 3,000Å 두께로 형성한다. 여기서, 상기 패터닝용 박막(22)은 목적에 따라 그 재질이 결정되며, 본 발명의 실시예에서는 폴리실리콘막으로 형성된다. 그리고, 상기 박막의 실리콘막(24)은 폴리실리콘막 또는 비정질실리콘막 중에서 선택되는 하나의 막으로 형성하며, 아울러, 후속의 실리콘 에피층의 형성시에 실리콘의 성장 시드(seed)로서 이용한다.First, as shown in FIG. 3A, the patterning thin film 22 is formed on the semiconductor substrate 21. Then, the hard mask film 23 and the thin film are sequentially formed on the patterning thin film 22. The silicon film 24 and the oxide film 25 are formed to have a thickness of 500 to 2,000 kPa, 100 to 300 kPa, and 1,000 to 3,000 kPa, respectively. Here, the patterning thin film 22 is a material is determined according to the purpose, in the embodiment of the present invention is formed of a polysilicon film. The thin silicon film 24 is formed of one film selected from a polysilicon film or an amorphous silicon film, and is used as a growth seed of silicon in the subsequent formation of a silicon epilayer.
그 다음, 도 3b에 도시된 바와 같이, 상기 산화막(25) 상에 개구부를 갖는 감광막 패턴(26)을 형성하고, 그런다음, 노출된 산화막 부분을 식각하여, 상기 실리콘막(24)을 노출시키는 콘택홀(27)을 형성한다.Next, as shown in FIG. 3B, a photosensitive film pattern 26 having an opening is formed on the oxide film 25, and then the exposed oxide film portion is etched to expose the silicon film 24. The contact hole 27 is formed.
다음으로, 도 3c에 도시된 바와 같이, 감광막 패턴을 제거한 상태에서, 콘택홀(27)을 포함한 산화막(25) 상에 절연막을 증착하고, 그런다음, 상기 절연막을 에치백하여 상기 콘택홀(27)의 양 측벽에 스페이서(28)를 형성한다. 여기서, 상기 스페이서(28)는 최종적으로 얻게 되는 미세 패턴의 선폭을 결정하게 되므로, 그 두께 조절이 요구되고, 본 발명의 실시예에서는 100 내지 1,000Å 두께로 증착함이 바람직하다.Next, as illustrated in FIG. 3C, an insulating film is deposited on the oxide film 25 including the contact hole 27 in a state where the photoresist pattern is removed. Then, the insulating film is etched back to the contact hole 27. Spacers 28 are formed on both sidewalls of the substrate. Here, since the spacer 28 is to determine the line width of the finally obtained fine pattern, the thickness control is required, in the embodiment of the present invention is preferably deposited to a thickness of 100 to 1,000Å.
계속해서, 도 3d에 도시된 바와 같이, 희석된 HF 용액을 이용하여 노출된 실리콘막 부분을 세정하고, 그런다음, 선택적 에피텍셜 성장법을 이용해서, 세정된 실리콘막 부분 상에 실리콘 에피층(29)을 성장시킨다. 여기서, 상기 실리콘 에피층(29)의 성장 두께는 산화막(25) 보다 낮은 두께, 예를들어, 500 내지 2,000Å 두께로 형성한다.Subsequently, as shown in FIG. 3D, the exposed silicon film portion is cleaned using a diluted HF solution, and then, using the selective epitaxial growth method, the silicon epitaxial layer ( 29) grow. Here, the growth thickness of the silicon epitaxial layer 29 is formed to a thickness lower than the oxide film 25, for example, 500 to 2,000 kPa thick.
다음으로, 도 3e에 도시된 바와 같이, 스페이서 및 산화막을 소정 용액, 예를들어, 희석된 HF용액을 이용하여 제거하고, 그런다음, 실리콘 에피층(29)을 마스크로하는 반응이온식각을 수행해서, 실리콘막(24) 및 하드 마스크막(23)을 식각한다.Next, as shown in FIG. 3E, the spacer and the oxide film are removed using a predetermined solution, for example, diluted HF solution, and then reactive ion etching is performed using the silicon epi layer 29 as a mask. The silicon film 24 and the hard mask film 23 are etched.
그리고나서, 도 3f에 도시된 바와 같이, 식각된 하드 마스크막(23)을 마스크로하는 식각 공정으로 그 하부의 패터닝용 박막을 식각해서, 미세 선폭을 갖는 라인 패턴(22a)을 형성한다. 여기서, 상기 패터닝용 박막의 식각시, 하드 마스크막(23) 상에 잔류되어 있는 실리콘 에피층 및 실리콘층도 함께 식각·제거된다.Then, as shown in FIG. 3F, the patterning thin film under the etching is etched by an etching process using the etched hard mask film 23 as a mask to form a line pattern 22a having a fine line width. Here, during the etching of the patterning thin film, the silicon epitaxial layer and the silicon layer remaining on the hard mask film 23 are also etched and removed.
한편, 상기 실리콘 에피층 및 실리콘막은 상기 패터닝용 박막의 식각시에 함께 제거되지만, 경우에 따라서, 상기 하드 마스크막(23)의 식각 후, 상기 패터닝용 박막의 식각 이전에 제거시킬 수도 있다.Meanwhile, the silicon epitaxial layer and the silicon film may be removed together during the etching of the patterning thin film, but in some cases, after the etching of the hard mask layer 23, the silicon epitaxial layer and the silicon film may be removed before the etching of the patterning thin film.
상기에서, 라인 패턴(22a)은 포토 공정에 의해 구현되는 패턴의 폭 보다 더 좁은 폭의 하드 마스크막을 이용한 식각 공정으로 얻어지므로, 본 발명을 이용할 경우, 포토 공정에 의해 얻을 수 없는 임계 치수 이하의 폭을 갖는 라인 패턴을 형성할 수 있다. 또한, 식각 장벽으로서 기능하는 하드 마스크막의 두께를 그대로 유지시킬 수 있기 때문에, 식각 공정의 안정화를 얻을 수 있다.In the above, since the line pattern 22a is obtained by an etching process using a hard mask film having a width narrower than the width of the pattern realized by the photo process, the line pattern 22a is less than or equal to the critical dimension that cannot be obtained by the photo process. A line pattern having a width can be formed. In addition, since the thickness of the hard mask film functioning as the etching barrier can be maintained as it is, stabilization of the etching process can be obtained.
이상에서와 같이, 본 발명은 콘택홀의 양 측벽에 스페이서를 형성시키는 것에 의해 라인 패턴의 선폭을 감소시킬 수 있고, 아울러, 절연막의 증착 두께에 따라 상기 라인 패턴의 선폭 제어를 용이하게 수행할 수 있다.As described above, the present invention can reduce the line width of the line pattern by forming spacers on both sidewalls of the contact hole, and can also easily control the line width of the line pattern according to the deposition thickness of the insulating film. .
따라서, 포토 공정에 의해 구현할 수 없는 미세 선폭의 라인 패턴 형성이 가능하며, 아울러, 상기 라인 패턴 형성의 재현성을 높일 수 있고, 결과적으로, 고집적 소자의 제조에 매우 유리하게 적용할 수 있다.Therefore, it is possible to form a line pattern having a fine line width that cannot be realized by the photo process, and also to improve the reproducibility of the line pattern formation, and as a result, it can be very advantageously applied to the production of highly integrated devices.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (9)
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