KR100315754B1 - Expandable Logic Analyser and Controlling Method for the same - Google Patents

Abstract

The present invention relates to a logic analyzer for accurately observing signal stages of a logic circuit. In particular, the sub-controller (Slave Controller, SC) and the main controller (Master Controller, MC) are separately configured to facilitate expansion and trigger conditions. The present invention relates to a logic analyzer and a control method for implementing the same in a memory to start the observation of signal lines under a desired condition.

The logic analyzer of the present invention installs the logic analyzer 20 between the computer 40 and the target circuit 30, drives the target circuit 30 according to the control software of the computer 40, and stores the result signal. The logic analyzer 20 is largely composed of one main controller 70 (Master Controller, MC) and a plurality of memory units 50 (Memory Block, MB). The main controller 70 has a means for transmitting and receiving data to and from the computer 40 through a parallel port, and the control unit 60 and control signals and data of the respective memory units 50. It is configured to have a means for transmitting and receiving.

According to the logic analyzer and the control method of the present invention as described above, the memory unit 50 can be additionally installed if necessary due to the structure of the hardware, and the expansion is easy, and the input and the process are controlled by the program of the computer 40. As the result is transmitted to the computer 40 for analysis, the flexibility of logic analysis is greatly ensured. Therefore, even when emulation using new hardware or prototype is required, it can be easily transformed. In addition to saving money, the company has a dramatic effect on securing competitive advantage through rapid product development.

Description

Expandable Logic Analyzer and Control Method {Expandable Logic Analyser and Controlling Method for the same}

The present invention relates to a logic analyzer for accurately observing signal stages of a logic circuit. In particular, the sub-controller (Slave Controller, SC) and the main controller (Master Controller, MC) are separately configured to facilitate expansion and trigger conditions. The present invention relates to a logic analyzer and a control method for implementing the same in a memory to start the observation of signal lines under a desired condition.

Recently, with the rapid development of integrated circuit design and semiconductor process technology, the scale of digital circuit design is increasing and its configuration is also becoming complicated. In addition, competition in the market is becoming more and more fierce, and the practical task of developing a superior product in a short time is emerging. Therefore, the necessity of a technique for quickly and efficiently implementing and verifying a designed circuit is very high.

In the past, we have relied mainly on software simulation to verify the circuits designed as above, but simulation is a test of the behavior by modeling, not the actual situation in which the circuit is driven, and also depends on the input vector, which limits the reliability and accuracy. There was. In addition, the performance of simulation software and computers is often unable to keep up with the rapidly increasing circuit complexity, which often results in the inability to obtain the right software or computer at the right time, so testing is postponed until such verification tools are developed. It takes a lot of time and has the disadvantage of realizing the timing of commercialization.

Therefore, in order to overcome the shortcomings of the simulation and to verify the accuracy of the circuit, a new prototyping method can be performed in a more practical operating environment, as shown in the schematic diagram of FIG. Presented and spotlighted. That is, according to this, the corresponding signal lines of the logic analyzer 20 are connected to the signal lines of the target circuit 30, which requires experiments, and the target circuit 30 is driven according to the control program of the computer 40, and the resulting signal is obtained. It is configured to be able to store in the memory of the logic analyzer 20.

As described above, when testing the target circuit implemented on the prototype or the emulator, it is necessary to observe the waveform of each signal to determine the normal operation. However, it is very cumbersome and complex to find out how the user physically implements the signal lines he wants to observe, and to connect and observe the observation signals to the signal lines. It is cumbersome.

In addition, as the system becomes more complex and diverse, ASIC fabrication technology is remarkably improved, and accordingly, the trend of implementing one system as an ASIC on a single chip is prominent. According to this tendency, in view of the fact that the number of signal lines to be observed in the logic circuit is proportional to the size of the circuit, the logic analyzer should be designed to be easily extended for the observation of complex systems. However, in the conventional logic analyzer, since the memory device and the control device are integrally configured together on one board, there is a problem in that the expansion cannot be easily performed even when the necessity of expansion occurs due to the increase in signal lines.

In addition, in the face of active development of high performance emulator equipment with various functions, the addition of logic analysis function is essential. However, the conventional logic analyzer has a serious problem that it is almost impossible to be mounted on other equipment because it is manufactured in one system having all the necessary functions.

The present invention is to solve the above problems, and to provide a logic analyzer and a control method thereof that can be easily mounted on an emulator or the like and have a structure that is easy to expand.

1 is a general schematic diagram of a logic analyzer using a computer,

2 is a schematic block diagram of an internal structure of a logic analyzer of the present invention;

3 is a schematic diagram of a sub-control unit SC of the logic analyzer of the present invention;

4 is a schematic diagram of a main control unit MC of the logic analyzer of the present invention;

5 is a diagram illustrating the scalability of the logic analyzer of the present invention;

6 is a memory structure diagram for checking a trigger condition in the logic analyzer of the present invention;

7 is a configuration diagram of a state detector of a logic analyzer of the present invention;

8 is a state transition diagram of a logic analyzer of the present invention;

9 is a table showing data that must be stored in a memory in order for the state detector of the logic analyzer of the present invention to have a state transition as shown in FIG. 8;

10 is a flowchart of a control program of the logic analyzer of the present invention.

<Description of Symbols for Major Parts of Drawings>

20: logic analyzer 30: target circuit

40: computer 50: memory section

60: slave controller (SC)

70: master controller (MC)

In order to achieve the above object, the logic analyzer of the present invention is provided with a logic analyzer 20 between the computer 40 and the target circuit 30, as shown in FIG. Accordingly, the target circuit 30 is driven to store the resultant signal.

The detailed configuration of the logic analyzer 20 is largely shown in the schematic block diagram of FIG. 2. The logic analyzer 20 of the present invention includes a main controller 70 (Master Controller, MC) and a plurality of memory units ( 50) (Memory Block, MB), wherein the main control unit 70 has means for transmitting and receiving data through the parallel port with the computer 40, and also the sub-control unit of each memory unit 50 60 and means for transmitting and receiving control signals and data.

On the other hand, each of the memory unit 50 is largely composed of a sub-control unit 60, SRAM and signal lines, the sub-control unit 60 is provided with a means for transmitting and receiving control signals and data with the main control unit 70 The SRAM is configured to output data to or receive data from the signal line according to a control signal of the sub-control unit 60.

As shown in FIG. 3, the sub-controller 60 may include an address generator for designating an address of an SRAM for storing sampled signal values, a read / write controller for controlling a read / write operation of the SRAM, and observed data. It is composed of a transmission module for transmitting to the main controller 70.

The data I / O pins of the SRAM are connected to the observation signal line or the transmission module through a buffer.

That is, in the related art, the control unit connected to the computer 40 was configured as one, but in the present invention, it is divided into one main controller 70 and a plurality of sub-control units 60 subordinate to each memory unit 50. will be.

The operation of the logic analyzer of the present invention as described above will be described in detail.

The memory unit 50 is controlled by the sub-control unit 60 (Slave Controller, SC), and stores the observed value of the signal line to be observed in the SRAM every predetermined sampling period. The sampling start time is synchronized by the main controller 70, and when the memory becomes full, a hardware interrupt is generated to the host computer and the sampling operation is stopped. In addition, the sampling operation in each memory unit 50 is controlled by the sub-control unit 60 of the corresponding memory unit 50, and the operation of each sub-control unit 60 is controlled by one main controller 70. Has a very easy structure.

The main controller 70 selects one of a plurality of memory units 50 subordinate to the main controller 70 and transmits observation data stored in the SRAM to the computer 40 through the parallel port. In other words, the observed data is processed by the host computer, which allows the user to apply the host computer to observe the operation of the circuit.

The main controller 70 stores a trigger condition specified by the user in the SRAM using a program on the computer 40. The trigger condition and the address of the SRAM memory area to store it are transmitted from the computer 40 to the main controller 70 through the parallel port. The control unit 60 is synchronized when all the conditions are satisfied by comparing the signal values sampled through the trigger condition check input with the start of sampling.

After performing the observation of the signal lines to be observed, the main controller 70 designates one of the plurality of memory units 50 and receives the observed data stored in the SRAM and transmits the observed data to the computer 40 through the parallel port. In this case, as shown in the schematic diagram of FIG. 4, when a command for designating the operation of the main control unit 70 in the program on the computer 40 is transmitted through the parallel port, the command is transmitted by the command decoder in the main control unit 70. The type of work to be translated and determined by the main control unit 70 is determined. The type of job determines the meaning of the next data transferred through the parallel port.

As illustrated in FIG. 5, a plurality of memory units 50 may be easily mounted on the main control unit 70. The sampling operation in each memory unit 50 is controlled by the sub-control unit 60 of the memory unit 50, and one main control unit 70 controls the operation of each sub-control unit 60. Each memory unit 50 is assigned with a unique memory unit 50 identifier, and the main control unit 70 outputs the memory unit 50 identifier to designate a specific memory unit 50. The non-selected memory section 50 ignores all data on the bus.

Meanwhile, as shown in the memory structure diagram of FIG. 6, the trigger condition detector uses the data output of the SRAM as a memory address having the next trigger condition. The 8-bit data output of the memory is the upper 8 bits of the 16-bit address, and the values of the eight signal lines that are the trigger condition check targets are the lower 8-bit addresses.

On the other hand, the state detector for checking the trigger condition in each sub-control unit 60 is configured in the memory unit 50 using the SRAM. Each trigger condition consists of up to 8 bits and can check up to 255 consecutive trigger conditions. When the trigger condition is 3 bits, the state detector may check a trigger condition by configuring a 64 word memory having one word of 3 bits as shown in the configuration diagram of FIG. 7. Here, one word output by the current address is mapped to the upper 3 bits of the next address.

Given a trigger condition in the order of S2 (010), S5 (101), S3 (011), and S6 (110), the memory is composed of a finite state circuit as shown in the state transition diagram of FIG.

In this case, only when 010, 101, 011, and 110 are continuously input, the control signal indicating the start of sampling should be generated. Thus, data is stored in the memory in the form shown in the diagram of FIG. Here, CL (Current Level) represents the depth of the current state, INP represents the 3-bit data input for checking the trigger condition, and NL (Next Level) represents the depth of the next state. In the remaining address spaces not shown in FIG. 9, all 000 values are stored.

Here CL and INP constitute a memory address that designates one word, and NL is the word that is output. Only when data of 010, 101, 011, and 110 are input in sequence, it goes into Start state, and if an input that does not meet the trigger condition is entered once, the upper 3 bits of the next address become 000 and return to the initial S2 state. I will go.

10 is a flowchart illustrating a control method of a logic analyzer of the present invention having the configuration and operation described above.

In detail, first, a circuit 30 to be verified is designated and a test input to be applied thereto is generated.

After that, it is checked whether a corresponding signal line exists in the circuit to be subjected to the logic analysis, and if there is no signal line, the signal line ends. If so, the signal lines are determined, and then a connection state is established with corresponding signal lines of the logic analyzer.

Then, it is determined whether to use a trigger condition. If not, the computer 40 immediately instructs the main controller 70 to perform a logic analysis operation.

However, if the trigger condition is used, the signal lines to be used for the trigger condition check are determined from the circuit to be verified, the connection with the observation signal line of the logic analyzer is established, and then the computer 40 inputs the trigger condition data to the main controller 70. The main controller 70 configures a trigger condition check circuit using a memory. Then, the computer 40 instructs the main controller 70 to start the logic analysis, and the main controller 70 starts the trigger condition check. At this time, if the user interrupt occurs, the process returns to the initial stage and repeats the trigger condition check until all trigger conditions are satisfied.

After taking measures according to the trigger condition check as described above, the sub-control unit 60 on each memory unit 50 starts sampling the logic value of the observation signal line by the main controller 70 and repeats until an interrupt occurs. If an interrupt occurs, the address variable ADD and the counter variable i are initialized, and then incremented by 1 until the memory variable ADD becomes the last address of the memory. After reading the sampling data stored at the memory address ADD from the SRAM module of the i-th memory unit 50 to the computer 40 while increasing by one until the variable i becomes the last memory unit 50, Go back to the beginning.

Therefore, according to the logic analyzer and the control method of the present invention as described above, the memory unit 50 can be additionally installed if necessary in the structure of the hardware, so that the expansion is easy, and the input and the progress are controlled by the program of the computer 40. And the results are transmitted back to the computer 40 for analysis, which greatly guarantees the flexibility of logic analysis. Accordingly, even when emulation using new hardware or a prototype is required, it can be easily transformed. The cost savings and rapid product development have a dramatic effect on securing a competitive advantage.

Claims (2)

In the logic analyzer 20 composed of one main control unit 70 and a plurality of memory units 50, The main control unit 70 has a means for transmitting and receiving data to and from the computer 40 through a parallel port, and can also transmit and receive control signals and data to and from the sub-control unit 60 of each of the memory units 50. Configured to have a means of Each of the memory unit 50 is composed of a sub-control unit 60, SRAM and signal lines. The sub-control unit 60 includes means for transmitting and receiving control signals and data to and from the main controller 70, and an address generator for designating an address of the SRAM for storing sampled signal values, and reading / reading of the SRAM. Read / write controller for controlling the write operation, and a transmission module for transmitting the observed data to the main control unit 70, The SRAM is configured to output data to the signal line or receive data from the signal line according to the control signal of the sub-control unit 60, and the data I / O pin is configured to be connected to the observation signal line or the transmission module through a buffer. Scalable logic analyzer, characterized in that. In the method for controlling a logic analyzer having the configuration as claimed in claim 1, Designating a circuit 30 to be verified and generating a test input to be applied thereto; Thereafter checking whether a corresponding signal line exists in the circuit to be subjected to the logic analysis, if there is no signal line, terminating; if there is a signal line, determining the signal lines and making a connection state with corresponding signal lines of a logic analyzer; It is determined whether to use the trigger condition, and if the trigger condition is not used, the computer 40 immediately instructs the main controller 70 to perform a logic analysis operation. After determining and establishing a connection with the observation signal line of the logic analyzer, the computer 40 inputs trigger condition data to the main control unit 70, and the main control unit 70 uses a memory to execute the trigger condition check circuit. After the configuration, the computer 40 instructs the main controller 70 to start the logic analysis, and the main controller 70 starts the trigger condition check and returns to the initial stage when an interruption of the user occurs, and all trigger conditions Repeating the trigger condition check until a is satisfied; After taking measures according to the trigger condition check as described above, the sub-control unit 60 on each memory unit 50 starts sampling the logic value of the observation signal line by the main controller 70 and repeats until an interrupt occurs. If an interrupt occurs, the address variable ADD and the counter variable i are initialized, and then incremented by 1 until the memory variable ADD becomes the last address of the memory. After reading the sampling data stored at the memory address ADD from the SRAM module of the i-th memory unit 50 to the computer 40 while increasing by one until the variable i becomes the last memory unit 50, Scalable logic analyzer control method comprising the step of returning to the initial start again.