KR100313493B1 - Fabricating method for metal line of semiconductor memory - Google Patents
Fabricating method for metal line of semiconductor memory Download PDFInfo
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- KR100313493B1 KR100313493B1 KR1019980008504A KR19980008504A KR100313493B1 KR 100313493 B1 KR100313493 B1 KR 100313493B1 KR 1019980008504 A KR1019980008504 A KR 1019980008504A KR 19980008504 A KR19980008504 A KR 19980008504A KR 100313493 B1 KR100313493 B1 KR 100313493B1
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- metal wiring
- metal
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 171
- 239000002184 metal Substances 0.000 title claims abstract description 171
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 12
- 239000003292 glue Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 7
- 239000011800 void material Substances 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 폭이 넓은 금속배선을 최소선폭으로 분할하여 형성함으로써, 금속배선의 그레인에서 금속원자가 확산되는 것을 방지하여 전하이동특성을 향상 시키는데 적당하도록 한 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and in particular, by forming a wide metal wiring by dividing it into a minimum line width, thereby preventing metal atoms from diffusing in grains of the metal wiring, thereby making it suitable for improving charge transfer characteristics. The present invention relates to a metal wiring forming method of a semiconductor device.
일반적으로, 알루미늄 등을 사용하여 반도체 소자간의 접속을 하기위해 형성하는 금속배선은 반도체 소자가 형성된 기판의 상부에 절연층을 증착하고, 그 절연층에 콘택홀을 형성한 다음, 그 콘택홀 및 절연층에 금속을 증착한 후, 사진식각공정을 통해 동시에 형성한다. 이와 같이 형성되는 금속배선 중 그 폭이 최소선폭에 근 접한 금속배선의 원자배열을 그 그레인(grain)의 구조가 금속배선의 길이에 수직 방향으로 정렬되는 대나무구조(bamboo structure)로 형성되나, 금속배선의 폭이 0.6 mum 이상인 경우에는 보통의 다결정구조를 갖도록 형성되어 그레인의 경계를 통한 원자의 확산이 용이해저 수명이 단축되며, 이와 같은 종래 반도체 소자의 금속배선 형성방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a metal wiring formed for connection between semiconductor elements using aluminum or the like deposits an insulating layer on an upper portion of a substrate on which the semiconductor element is formed, and forms a contact hole in the insulating layer, and then the contact hole and insulation After the metal is deposited on the layer, it is simultaneously formed through a photolithography process. Among the metal wires formed as described above, the width of the metal wires close to the minimum wire width is formed in a bamboo structure in which the grain structure is aligned in the direction perpendicular to the length of the metal wires. When the width of the wiring is 0.6 mum or more, it is formed to have a normal polycrystalline structure, which facilitates the diffusion of atoms through the grain boundary, thereby shortening the lifespan. Referring to the accompanying drawings of the method of forming the metal wiring of the conventional semiconductor device, It will be described in detail as follows.
도1a 내지 도1c는 종래 반도체 소자의 금속배선 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 제조된 기판(1)의 상부에 절연층(2)을 증착하고, 그 절연층(2)의 상부에 배리어 금속층(3), 금속층(4), 글루(GLUE) 금속층(5)을 순차적으로 증착하는 단계(도1a)와; 사진식각공정을 통해 상기 글루 금속층(5),금속층(4), 배리어 금속층(3)의 일부를 식각하여 금속배선을 형성하는 단계(도1b)와; 상기 형성한 금속배선의 절연을 위해 상기 글루 금속층(5)의 상부와 노출된 절연층(2)의 상부에 절연층(6)을 증착하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views of a process for manufacturing a metal wiring of a conventional semiconductor device. As shown therein, an insulating layer 2 is deposited on the substrate 1 on which the semiconductor device is manufactured, and the insulating layer 2 is formed. Sequentially depositing a barrier metal layer (3), a metal layer (4), and a glue metal layer (5) on top of (Fig. 1A); Etching a portion of the glue metal layer 5, the metal layer 4, and the barrier metal layer 3 through a photolithography process to form metal wiring (FIG. 1B); In order to insulate the formed metal wiring, the insulating layer 6 is deposited on the upper portion of the glue metal layer 5 and the exposed insulating layer 2 (FIG. 1C).
이하, 상기와 같은 종래 반도체 소자의 금속배선 형성방법을 좀 더 상세히 설명한다.Hereinafter, the metal wiring forming method of the conventional semiconductor device as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 반도체 기판(1)에 특정 소자를 제조하고, 그 반도체 소자가 제조된 기판(1)의 상부 전면에 절연층(2)을 증착한다.First, as shown in FIG. 1A, a specific device is manufactured on the semiconductor substrate 1, and an insulating layer 2 is deposited on the entire upper surface of the substrate 1 on which the semiconductor device is manufactured.
그 다음, 도면에 도시하지는 않았지만 사진식각공정을 통해 상기 절연층(2)에 콘택홀을 형성하여 그 하부에 형성한 반도체 소자의 특정영역을 노출시킨다. 그 다음, 상기 콘택홀이 형성된 절연층(2)의 상부 전면에 배리어 금속층(3), 금속층(4), 글루(GLUE) 금속층(5)을 순차적으로 증착한다. 이때, 글루 금속층(5)은 티타늄(Ti)을 사용한다.Next, although not shown in the drawing, a contact hole is formed in the insulating layer 2 through a photolithography process to expose a specific region of the semiconductor device formed below. Next, the barrier metal layer 3, the metal layer 4, and the GLUE metal layer 5 are sequentially deposited on the entire upper surface of the insulating layer 2 on which the contact hole is formed. At this time, the glue metal layer 5 uses titanium (Ti).
그 다음, 도1b에 도시한 바와 같이 금속배선 마스크를 사용하는 사진식각공정을 통해 상기 글루 금속층(5), 금속층(4), 배리어 금속층(3)의 일부를 식각하여 선폭과 길이 및 패턴이 다른 다수의 단위 금속배선을 동시에 형성하게 된다.Next, as shown in FIG. 1B, a part of the glue metal layer 5, the metal layer 4, and the barrier metal layer 3 are etched through a photolithography process using a metal wiring mask, and the line width, length, and pattern are different. A plurality of unit metal wirings are formed at the same time.
그 다음, 도1c에 도시한 바와 같이 상기 형성한 금속배선 간의 절연 및 외부의 정전기로부터 소자의 보호를 위해 상기 글루 금속층(5)의 상부와 노출된 절연층(2)의 상부에 절연층(6)을 증착한다.Next, as shown in FIG. 1C, the insulating layer 6 is disposed on the upper part of the glue metal layer 5 and the exposed insulating layer 2 to protect the device from the insulation between the formed metal wires and external static electricity. E).
그러나, 상기한 바와 같이 종래 반도체 소자의 금속배선 형성방법은 각기 다른 선폭의 금속배선을 동시에 형성함으로써, 금속배선이 0.6 mum 이상인 경우 그 금속배선의 그레인 경계로 부터 원자가 확산되어 보이드(VOID) 및 힐록(HILL LOCK)이 형성되어 전하 이동특성이 열화되는 문제점이 있었다.However, as described above, in the method of forming metal wirings of the conventional semiconductor device, the metal wirings having different line widths are formed simultaneously, so that when the metal wirings are 0.6 mum or more, atoms diffuse from the grain boundaries of the metal wirings to cause voids and hillocks. (HILL LOCK) is formed there is a problem that the charge transfer characteristics deteriorate.
이와 같은 문제점을 감안한 본 발명은 금속배선의 그레인 경계로 부터 원자가 확산되는 것을 방지하는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for forming metal wirings in a semiconductor device which prevents atoms from diffusing from grain boundaries of the metal wirings.
도1a 내지 도1c는 종래 반도체 소자의 금속배선 제조공정 수순 단면도.1A to 1C are cross-sectional views of a metal wire manufacturing process of a conventional semiconductor device.
도2a 내지 도2d는 본 발명 반도체 소자의 금속배선 제조공정 수순 단면도.2A to 2D are cross-sectional views of a metal wiring manufacturing process of the semiconductor device according to the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2,6:절연층1: substrate 2, 6: insulation layer
3,7:배리어 금속층 4,8:금속층3,7: Barrier metal layer 4,8: Metal layer
5:글루 금속층5: glue metal layer
상기와 같은 목적은 반도체 소자가 제조된 기판의 상부에 절연층을 증착하고, 그 절연층에 콘택홀을 형성하여 반도체 소자의 특정영역을 노출시키는 콘택홀 형성단계와; 상기 콘택홀이 형성된 절연층의 상부에 금속을 증착하고, 그 금속을 패터닝하여 금속배선을 형성하는 금속배선 형성단계를 포함하는 반도체 소자의 금속배선 형성방법에 있어서, 상기 금속배선 형성단계를 최소선폭 이상의 금속배선을 형성할 때, 그 금속배선을 최소선폭을 갖는 단위영역으로 분할하고, 그 분할된 단위영역에 교번하여 금속배선패턴을 형성하는 1차 금속배선패턴 형성단계와; 상기 1차 금속배선패턴 형성단계에서 형성된 금속배선패턴의 사이에 금속배선패턴을 형성하는 2차 금속배선패턴 형성단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a contact hole forming step of depositing an insulating layer on the substrate on which the semiconductor device is manufactured, and forming a contact hole in the insulating layer to expose a specific region of the semiconductor device; In the method of forming a metal wiring of a semiconductor device comprising the step of depositing a metal on the insulating layer formed with the contact hole, and patterning the metal to form a metal wiring, the metal wiring forming step is a minimum line width Forming a metal wiring by forming a metal wiring pattern by dividing the metal wiring into unit regions having a minimum line width, and alternately forming the metal wiring patterns in the divided unit regions; This is achieved by configuring a secondary metal wiring pattern forming step of forming a metal wiring pattern between the metal wiring patterns formed in the primary metal wiring pattern forming step, and will be described in detail with reference to the accompanying drawings. As follows.
도2a 내지 도2d는 본 발명 반도체 소자의 금속배선 제조공정 수순 단면도로서, 이에 도시한 바와 같이 반도체 소자가 제조된 기판(1)의 상부에 절연층(2)을 증착하고, 그 절연층(2)의 상부에 배리어 금속층(3), 금속층(4)을 순차적으로 증착하는 단계(도2a)와; 사진식각공정을 통해 상기 배리어 금속층(3), 금속층(4)의 일부를균일한 간격으로 식각하여 금속배선패턴을 형성하는 단계(도2b)와; 상기 금속배선패턴의 사이에 노출된 절연층(2)과 금속배선 패턴의 상부전면에 배리어 금속층(7)과 금속층(8)을 증착하는 단계(도2c)와; 상기 배리어 금속층(7)과 금속층(8)을 에치백하여 상기 금속층(4)을 노출시키고, 상대적으로 좁은 선폭을 갖는 금속배선영역(WS)에 증착된 배리어 금속층(7)과 금속층(8)을 선택적으로 식각한 후, 상기 금속층(8)(4)과 노출된 배리어 금속층(7)의 상부에 글루 금속층(5)을 증착한 후, 각 금속배선의 절연을 위해 상기 글루 금속층(5)의 상부와 노출된 절연층(2)의 상부에 절연층(6)을 증착하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a process for manufacturing a metal wiring of the semiconductor device according to the present invention. As shown in FIG. Sequentially depositing a barrier metal layer (3) and a metal layer (4) on the top of the (); Etching a portion of the barrier metal layer 3 and the metal layer 4 at uniform intervals through a photolithography process to form a metal wiring pattern (FIG. 2B); Depositing a barrier metal layer (7) and a metal layer (8) on the insulating layer (2) exposed between the metal wiring pattern and the upper surface of the metal wiring pattern (FIG. 2C); The barrier metal layer 7 and the metal layer 8 are etched back to expose the metal layer 4 and the barrier metal layer 7 and the metal layer 8 deposited in the metal wiring region WS having a relatively narrow line width. After selectively etching, the metal layer 8 is deposited on the metal layer 8 and the exposed barrier metal layer 7, and then the top of the metal layer 5 is insulated for insulation of each metal wiring. And depositing an insulating layer 6 on the exposed insulating layer 2 (FIG. 2D).
이하, 상기와 같이 구성된 본 발명을 좀 더 상세히 설명하면 다음과 같다.Hereinafter, the present invention configured as described in more detail as follows.
먼저, 도2a에 도시한 바와 같이 반도체 소자가 제조된 기판(1)의 상부에 절연층(2)을 증착한 후, 그 절연층(2)에 콘택홀을 형성하여 상기 반도체 소자의 특정영역을 노출시키고, 상기 콘택홀이 형성된 절연층(2)의 상부에 배리어 금속층(3)과 금속층(4)을 증착한다.First, as shown in FIG. 2A, an insulating layer 2 is deposited on the substrate 1 on which the semiconductor device is manufactured, and then contact holes are formed in the insulating layer 2 to form a specific region of the semiconductor device. The barrier metal layer 3 and the metal layer 4 are deposited on the insulating layer 2 on which the contact hole is formed.
여기서 상기 절연층(2)에 형성된 콘택홀과 그 콘택홀을 통해 배리어금속층(3)과 금속층(4)이 상기 노출된 반도체 소자의 특정영역에 접하는 형상은 상기 도2a에 보여지지는 않지만 이는 단면의 선택에 있어서 보다 간단한 도면을 제공하려는 의도로 상기 콘택홀이 형성되지 않은 영역의 단면을 보였다.Here, a contact hole formed in the insulating layer 2 and a shape in which the barrier metal layer 3 and the metal layer 4 contact the specific region of the exposed semiconductor device through the contact hole are not shown in FIG. The cross section of the region where the contact hole is not formed is shown with the intention of providing a simpler drawing in the selection of.
그 다음, 도2b에 도시한 바와 같이 사진식각공정을 통해 상기 금속층(4)과 배리어 금속층(4)의 일부를 식각한다. 이때, 선폭이 넓은 금속배선을 형성하는 경우, 그 금속배선을 최소선폭(Ws)을 단위로 하여 각 단위에 교번하여 금속층(4)과 배리어금속층(4)이 잔존하도록 식각한다. 예를 들어 0.6 mu m의 선폭을 갖는 금속배선을 형성하는 경우, 최소선폭인 0.2 mu m의 선폭을 갖는 2개의 금속배선패턴을 0.2 mu m의 간격으로 형성한다. 이후의 공정에서 상기 형성한 2개의 금속배선패턴 사이에 금속배선을 형성하여 원하는 0.6 mu m의 선폭을 갖는 금속배선을 형성하게 된다.Next, as shown in FIG. 2B, the metal layer 4 and a part of the barrier metal layer 4 are etched through a photolithography process. At this time, in the case of forming a metal wiring having a wide line width, the metal wiring is etched alternately in each unit by the minimum line width Ws so that the metal layer 4 and the barrier metal layer 4 remain. For example, when forming a metal wiring having a line width of 0.6 mu m, two metal wiring patterns having a line width of 0.2 mu m, which is the minimum line width, are formed at intervals of 0.2 mu m. In the subsequent process, metal wiring is formed between the formed metal wiring patterns to form a metal wiring having a desired line width of 0.6 mu m.
그 다음, 도2c에 도시한 바와 같이 상기 선폭이 넓은 금속배선의 영역에 최소선폭을 단위로하여 형성한 금속배선패턴과 절연층(2)의 상부에 배리어 금속층(7)과 금속층(8)을 순차적으로 증착한다.Next, as shown in FIG. 2C, the barrier metal layer 7 and the metal layer 8 are formed on the metal wiring pattern and the insulating layer 2 formed on the basis of the minimum line width in the region of the wide metal wiring. Deposition sequentially.
그 다음, 도2d에 도시한 바와 같이 상기 증착된 금속층(8)을 에치백하여 그 상부가 상기 증착한 금속층(4)의 상부와 동일한 높이가 되도록 하고, 금속배선의 사이에 위치하는 금속층(8)과 배리어 금속층(7)을 식각하여 최소선폭(Ws) 또는 다수의 최소선폭(Ws)을 갖는 금속배선패턴의 합인 특정 선폭(WL)을 갖는 금속배선을 형성한다.Next, as shown in FIG. 2D, the deposited metal layer 8 is etched back so that the upper portion thereof is flush with the upper portion of the deposited metal layer 4, and the metal layer 8 positioned between the metal wires. ) And the barrier metal layer 7 are etched to form a metal wire having a specific line width W L which is the sum of the metal line patterns having the minimum line width Ws or a plurality of minimum line widths Ws.
그 다음, 상기 금속배선 패턴의 최상층인 금속층(4)과 금속층(8)의 상부 및 상기 금속층(4)과 금속층(8)의 사이에 노출되어 있는 배리어 금속층(7)의 상부전면에 글루 금속층(5)을 증착한다.Next, a glue metal layer is formed on the upper surface of the metal layer 4 and the metal layer 8, which are the uppermost layers of the metal wiring pattern, and the barrier metal layer 7 exposed between the metal layer 4 and the metal layer 8. 5) Deposit.
그 다음, 상기 형성된 최소선폭(Ws)의 금속배선과 특정 선폭(WL)의 글루 금속층(5)상부 및 노출된 절연층(2)의 상부에 절연층(6)을 증착한다.Next, an insulating layer 6 is deposited on the formed metal line having the minimum line width Ws, on the glue metal layer 5 having the specific line width W L , and on the exposed insulating layer 2.
즉, 제조하고자 하는 금속배선의 선폭이 최소선폭의 이상일 때, 그 금속배선의 선폭을 다수의 최소선폭영역으로 분할 하고, 그 분할된 최소선폭영역에 교번하여 1차로 금속배선패턴을 형성한 후, 그 1차로 형성한 금속배선패턴의 사이에 2차로 금속배선패턴을 형성하여, 그 금속배선의 선폭이 넓은 경우에도 상기 설명한 대나무형의 원자배열을 갖도록 함으로써, 원자의 확산을 방지할 수 있게 된다.That is, when the line width of the metal wiring to be manufactured is greater than or equal to the minimum line width, the line width of the metal wiring is divided into a plurality of minimum line width regions, and the metal wiring pattern is first formed alternately to the divided minimum line width regions. By forming a second metal wiring pattern between the first formed metal wiring patterns and having a wide line width of the metal wirings, it is possible to prevent the diffusion of atoms by having the above-described bamboo-type atomic arrangement.
상기한 바와 같이 본 발명은 제조하고자 하는 금속배선의 선폭이 최소선폭의 이상일 때, 그 금속배선의 선폭을 다수의 최소선폭영역으로 분할 하고, 그 분할된 최소선폭영역에 교번하여 1차로 금속배선패턴을 형성한 후, 그 1차로 형성한 금속배선패턴의 사이에 2차로 금속배선패턴을 형성하여, 그 금속배선의 선폭이 넓은 경우에도 상기 설명한 대나무형의 원자배열을 갖도록 함으로써, 원자의 확산을 방지하여 보이드 및 힐록을 방지하여 전하이동특성을 향상시키는 효과가 있다.As described above, according to the present invention, when the line width of the metal wire to be manufactured is greater than or equal to the minimum line width, the line width of the metal wire is divided into a plurality of minimum line width areas, and the metal wire pattern is alternately divided into the divided minimum line width areas. After forming the metal wiring pattern, the metal wiring pattern is formed secondly between the first metal wiring patterns formed so as to have the above-described bamboo-type atomic arrangement even when the line width of the metal wiring is wide, thereby preventing the diffusion of atoms. This prevents voids and hillocks, thereby improving the charge transfer characteristics.
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| KR1019980008504A KR100313493B1 (en) | 1998-03-13 | 1998-03-13 | Fabricating method for metal line of semiconductor memory |
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| KR1019980008504A KR100313493B1 (en) | 1998-03-13 | 1998-03-13 | Fabricating method for metal line of semiconductor memory |
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