KR100305206B1 - Method of forming a intermetal insulating film in a semiconductor device - Google Patents
Method of forming a intermetal insulating film in a semiconductor device Download PDFInfo
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- KR100305206B1 KR100305206B1 KR1019990025762A KR19990025762A KR100305206B1 KR 100305206 B1 KR100305206 B1 KR 100305206B1 KR 1019990025762 A KR1019990025762 A KR 1019990025762A KR 19990025762 A KR19990025762 A KR 19990025762A KR 100305206 B1 KR100305206 B1 KR 100305206B1
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- Prior art keywords
- film
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- insulating film
- interlayer insulating
- plug
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 230000001681 protective effect Effects 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 16
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000005452 bending Methods 0.000 abstract description 7
- 239000011241 protective layer Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속층간 절연막 형성 방법에 관한 것으로, 열적 유동성을 갖는 금속층간 절연막 상에 보호막을 형성한 이중 구조의 금속층간 절연막을 사용하는 경우, 플러그 콘택 홀을 형성하고 세정공정을 실시하기 전, 노출된 반도체 기판 상에 에피택셜막을 성장시키고 플러그 콘택 홀 측벽에 질화막 스페이서를 형성한 후 세정 공정을 실시하므로써, 금속층간 절연막과 보호막의 식각율 차이로 인한 플러그 콘택 홀 측면의 굴곡 현상을 방지할 수 있고, 열적 유동성을 갖는 금속층간 절연막 상부에 형성된 보호막에 의해 상부 배선층의 이동 및 변형을 억제할 수 있는 반도체 소자의 금속층간 절연막 형성 방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal interlayer insulating film of a semiconductor device. In the case of using a double layer interlayer insulating film having a protective film formed thereon, the plug contact hole and a cleaning process are performed. The epitaxial layer is grown on the exposed semiconductor substrate, the nitride spacer is formed on the sidewalls of the plug contact holes, and the cleaning process is performed to prevent bending of the side surfaces of the plug contact holes due to the difference in etching rates between the interlayer insulating film and the protective layer. A method of forming a metal interlayer insulating film of a semiconductor device capable of suppressing movement and deformation of an upper wiring layer by a protective film formed over the intermetallic insulating film having thermal fluidity is disclosed.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 금속층간 절연막으로 BPSG막과 보호막의 적층 구조를 사용하는 경우, 배선간의 접속을 위한 플러그 콘택 홀 측벽에 질화막 스페이서를 형성하므로써 콘택 홀 측벽에 굴곡 현상이 발생하는 것을 억제할 수 있는 반도체 소자의 금속층간 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the case of using a laminated structure of a BPSG film and a protective film as an interlayer insulating film of a semiconductor device, contact hole sidewalls are formed by forming nitride film spacers on the sidewalls of plug contact holes for connection between wirings The present invention relates to a method for forming an interlayer insulating film of a semiconductor device capable of suppressing occurrence of bending phenomenon.
회로의 선폭이 0.2㎛ 이하인 초고집적 반도체 소자의 제조 시에는 배선간의 절연을 위해 층간 절연막으로 BPSG막을 주로 사용한다. 이 BPSG막은 배선간의 갭 매립 특성을 향상시키고 열적 부담을 감소시키기 위하여 고농도의 보론(B)과 인(P) 불순물을 함유하고 있다. 이러한 고농도의 BPSG막은 후속 열공정에 의해서 유동성을 나타내어 상층 배선이 이동되거나 변형되는 문제점이 있다. 이에 따라 BPSG막 상층에 안정한 막질을 갖는 저온 플라즈마 산화막을 적층하여 사용하게 된다. 이와 같은 BPSG막/저온 플라즈마 산화막 구조는 반도체 기판의 접합 영역이 노출되는 플러그 콘택 홀 형성 후의 세정 공정시, 고농도의 BPSG막과 저온 플라즈마 산화막 간의 식각율 차이로 인하여 콘택 홀 측면에 굴곡이 발생하게 된다.In the fabrication of ultra-high density semiconductor devices having a line width of 0.2 mu m or less, a BPSG film is mainly used as an interlayer insulating film for insulation between wirings. This BPSG film contains high concentrations of boron (B) and phosphorus (P) impurities in order to improve gap filling characteristics between wirings and to reduce thermal burden. Such a high concentration of BPSG film exhibits fluidity by a subsequent thermal process, so that the upper layer wiring is moved or deformed. As a result, a low-temperature plasma oxide film having a stable film quality is laminated on the BPSG film. Such a BPSG film / low temperature plasma oxide film structure causes bending in the contact hole side due to a difference in etching rate between a high concentration of BPSG film and a low temperature plasma oxide film during the cleaning process after the plug contact hole is formed in which the junction region of the semiconductor substrate is exposed. .
도 1은 종래 금속층간 절연막 형성 방법의 문제점을 설명하기 위해 도시한 셈(SEM) 사진으로서, BPSG막(11)과 저온 플라즈마 산화막(12) 계면에서의 식각율 차이로 인하여 콘택 홀 측벽에서 굴곡 현상(13)이 발생한 것을 알 수 있다. 이러한 측면 굴곡이 과도하게 되면 플러그 콘택과 콘택 간의 접촉을 유발하거나 플러그 폴리 실리콘의 층덮힘을 불량하게 하여 소자의 특성이 열악해지는 문제점이 있다.FIG. 1 is a SEM photograph illustrating a problem of a method of forming a conventional interlayer insulating film, and a bending phenomenon occurs in a contact hole sidewall due to a difference in etching rates at an interface between a BPSG film 11 and a low temperature plasma oxide film 12. It can be seen that (13) has occurred. Excessive side curvature causes problems between the plug contact and the contact or poor layer covering of the plug polysilicon, resulting in poor device characteristics.
따라서, 본 발명은 플러그 콘택 홀 형성 후 노출된 반도체 기판 상에 애피택셜층을 성장시키고, 플러그 콘택 홀 내의 노출된 금속층간 절연막 측벽에 질화막 스페이서를 형성하므로써, 후속 플러그 콘택 홀의 세정 공정시 콘택 홀 측벽에 굴곡 현상이 발생하는 것을 억제할 수 있는 반도체 소자의 금속층간 절연막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention grows the epitaxial layer on the exposed semiconductor substrate after the formation of the plug contact hole, and forms the nitride spacer on the exposed sidewall of the interlayer insulating film in the plug contact hole, thereby making contact hole sidewalls in the subsequent cleaning process of the plug contact hole. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device capable of suppressing the occurrence of bending phenomenon.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속층간 절연막 형성 방법은 접합 영역이 형성된 반도체 기판 상에 하부배선층을 형성하고 전체구조 상에 금속층간 절연막을 형성하고 표면을 평탄화시키는 단계; 전체구조 상에 보호막을 형성하는 단계; 상기 반도체 기판의 접합 영여기 노출되도록 상기 보호막 및 금속층간 절연막을 식각하여 플러그 콘택 홀을 형성하는 단계; 상기 플러그 콘택 홀 저부의 노출된 접합 영역 상에 선택적으로 에피택셜막을 성장시키는 단계; 전체구조 상에 질화막을 형성한 후 전면식각하여 플러그 콘택 홀의 측벽에 질화막 스페이서를 형성하는 단계; 상기 플러그 콘택 홀 내의 자연 산화막이나 불순물을 제거하기 위한 세정 공정을 실시하는 단계; 상기 플러그 콘택 홀이 매립되도록 전체구조 상에 플러그 폴리실리콘층을 형성하는 단계; 플러그로 사용될 부분 이외 지역의 상기 플러그 폴리실리콘층 및 보호막 일부를 제거하여 플러그를 형성하는 단계; 상기 플러그 상에 상부배선층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming an interlayer insulating film of a semiconductor device, the method comprising: forming a lower wiring layer on a semiconductor substrate on which a junction region is formed, forming an intermetallic insulating film on an entire structure, and flattening a surface thereof; Forming a protective film on the entire structure; Forming a plug contact hole by etching the passivation layer and the interlayer insulating layer to expose the junction region of the semiconductor substrate; Selectively growing an epitaxial film on an exposed junction region of the bottom of the plug contact hole; Forming a nitride film spacer on the sidewall of the plug contact hole by etching the entire surface after forming the nitride film on the entire structure; Performing a cleaning process for removing a native oxide film or impurities in the plug contact hole; Forming a plug polysilicon layer on an entire structure such that the plug contact hole is embedded; Removing a portion of the plug polysilicon layer and the protective film in a region other than the portion to be used as a plug to form a plug; And forming an upper wiring layer on the plug.
도 1은 종래 금속층간 절연막 형성 방법의 문제점을 설명하기 위해 도시한 셈(SEM) 사진.1 is a SEM photograph illustrating a problem of a conventional method for forming an interlayer insulating film.
도 2a 내지 2g는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.2A to 2G are cross-sectional views of devices sequentially shown to explain a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
21 : 반도체 기판 22 : 하부배선층21 semiconductor substrate 22 lower wiring layer
23 : 금속층간 절연막 24 : 보호막23: interlayer insulating film 24: protective film
25 : 플러그 콘택 홀 26 : 에피택셜막25: plug contact hole 26: epitaxial film
27 : 질화막 스페이서 28 : 플러그 폴리실리콘층27 nitride film spacer 28 plug polysilicon layer
29 : 상부배선층29: upper wiring layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 2g는 본 발명에 따른 반도체 소자의 금속층간 절연막 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.2A to 2G are cross-sectional views of devices sequentially shown to explain a method for forming an interlayer insulating film of a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 접합 영역이 형성된 반도체 기판(21) 상에 하부배선층(22)을 형성하고 전체구조 상에 금속층간 절연막(23)을 형성한 후 화학적 기계적 연마 공정에 의해 표면을 평탄화시킨다. 이후, 금속층간 절연막(23)의 유동성으로 의한 문제점을 방지하기 위하여 보호막(24)을 형성한다. 여기에서, 금속층간 절연막(23)은 BPSG막을 이용하여 5000 내지 15000Å의 두께로 형성한다. 이 때 BPSG막 중의 보론(B) 함유량은 3 내지 6wt%로 하고, 인(P)의 함유량은 2 내지 5wt%가 되도록 한다. 또한, 금속층간 절연막(23)은 BPSG막을 800 내지 1000℃의 온도 범위에서 10 내지 200초 동안 금속 열처리하여 형성하거나, 750 내지 900℃의 온도범위에서 10 내지 30분동안 퍼니스에서 열처리하여 형성한다. 이와 같은 금속층간 절연막(23)은 고농도의 BPSG막을 이용하여 형성하기 때문에, 후속 열공정에 의해 유동성이 심화되므로, 금속층간 절연막(23) 상에 보호막(24)을 형성한다. 보호막(24)은 저온 플라즈마 산화막으로써, 350 내지 500℃의 온도 조건 및 0.1 내지 10 Torr의 압력 조건에서 TEOS계열의 물질을 이용하여 1000 내지 4000Å의 두께로 형성한다.As shown in FIG. 2A, the lower wiring layer 22 is formed on the semiconductor substrate 21 on which the junction region is formed, and the interlayer insulating film 23 is formed on the entire structure, and then the surface is planarized by a chemical mechanical polishing process. Let's do it. Thereafter, the protective film 24 is formed to prevent a problem due to the fluidity of the interlayer insulating film 23. Here, the interlayer insulating film 23 is formed to a thickness of 5000 to 15000 kV using a BPSG film. At this time, the boron (B) content in the BPSG film is set to 3 to 6 wt%, and the content of phosphorus (P) is set to 2 to 5 wt%. In addition, the interlayer insulating film 23 is formed by heat treatment of the BPSG film for 10 to 200 seconds in the temperature range of 800 to 1000 ℃, or by heat treatment in the furnace for 10 to 30 minutes in the temperature range of 750 to 900 ℃. Since the interlayer insulating film 23 is formed by using a high concentration of BPSG film, since the fluidity is deepened by a subsequent thermal process, the protective film 24 is formed on the interlayer insulating film 23. The protective film 24 is a low-temperature plasma oxide film and is formed to have a thickness of 1000 to 4000 kPa using a TEOS-based material at a temperature of 350 to 500 ° C. and a pressure of 0.1 to 10 Torr.
도 2b에 도시된 바와 같이, 포토레지스트막을 이용한 노광 및 식각 공정으로 보호막(24) 및 금속층간 절연막(23)을 식각하여 반도체 기판(21)의 접합 영역이 노출되는 플러그 콘택 홀(25)을 형성한다. 플러그 콘택 홀(25)을 형성하기 위한 식각 공정은 건식 식각 공정을 이용한다.As shown in FIG. 2B, the passivation layer 24 and the interlayer insulating layer 23 are etched by an exposure and etching process using a photoresist layer to form a plug contact hole 25 exposing the junction region of the semiconductor substrate 21. do. The etching process for forming the plug contact hole 25 uses a dry etching process.
도 2c에 도시된 바와 같이, 플러그 콘택 홀(25) 저부의 노출된 접합 영역 상에 선택적으로 에피택셜막(26)을 성장시킨다. 애피택셜막(26)은 10 내지 100Å의 두께로 형성하며, 플러그 콘택 홀 측벽에 후속 공정으로 질화막 스페이서를 형성할 때 접합 영역에 가해지는 손상을 방지하는 역할을 한다.As shown in FIG. 2C, the epitaxial film 26 is selectively grown on the exposed junction region of the bottom of the plug contact hole 25. The epitaxial film 26 is formed to a thickness of 10 to 100 kPa, and serves to prevent damage to the bonding region when the nitride spacers are formed on the sidewalls of the plug contact holes in a subsequent process.
도 2d에 도시된 바와 같이, 전체구조 상에 질화막을 형성한 후 전면식각하여 플러그 콘택 홀(25)의 측벽에 질화막 스페이서(27)를 형성한다. 질화막은 고온 조압 화학기상법에 의해 500 내지 1500Å의 두께로 형성하며, 전면 식각 후의 질화막 스페이서(27)의 두께는 100 내지 800Å이 되도록 한다. 또한, 전면 식각 공정시 애피택셜막(26)은 접합 영역을 보호할 수 있도록 소량 제거되도록 한다.As shown in FIG. 2D, a nitride film is formed on the entire structure and then etched to form a nitride film spacer 27 on the sidewall of the plug contact hole 25. The nitride film is formed to a thickness of 500 to 1500 kPa by the high temperature roughening chemical vapor method, and the thickness of the nitride film spacer 27 after the entire surface etching is 100 to 800 kPa. In addition, the epitaxial layer 26 may be removed in a small amount so as to protect the junction region during the entire surface etching process.
도 2e는 콘택 저항을 감소시키기 위하여 플러그 콘택 홀 내의 자연 산화막이나 불순물을 제거하기 위한 세정 공정을 실시한 후, 플러그 콘택 홀이 매립되도록 전체구조 상에 플러그 폴리실리콘층(28)을 형성한 상태를 나타내는 소자의 단면도이다. 세정 공정은 BOE를 이용하여 실시하며, 금속층간 절연막(23)과 보호막(24)이 질화막 스페이서(27)로 보호되어 있기 때문에 금속층간 절연막(23)과 보호막(24) 계면에서의 측면 굴곡 현상은 나타나지 않게 된다. 또한, 세정 공정 후 콘택 저항을 낮추기 위하여 5가 이온을 주입하는 단계를 추가하는 것도 가능하다. 한편, 플러그 폴리실리콘층(28)은 2000 내지 4000Å의 두께로 형성하며, 플러그 폴리실리콘층(28)을 형성한 후 5가 이온을 주입하는 단계를 추가하는 것도 가능하다.FIG. 2E illustrates a state in which the plug polysilicon layer 28 is formed on the entire structure such that the plug contact hole is embedded after the cleaning process for removing the native oxide film or impurities in the plug contact hole to reduce the contact resistance. A cross-sectional view of the device. The cleaning process is performed using BOE, and since the intermetallic insulating film 23 and the protective film 24 are protected by the nitride film spacer 27, the side-side bending phenomenon at the interface between the interlayer insulating film 23 and the protective film 24 is prevented. It will not appear. It is also possible to add a step of implanting pentavalent ions to lower the contact resistance after the cleaning process. On the other hand, the plug polysilicon layer 28 is formed to a thickness of 2000 to 4000Å, it is also possible to add a step of implanting pentavalent ions after forming the plug polysilicon layer 28.
도 2f에 도시된 바와 같이, 화학적 기계적 연마 공정 또는 전면 식각 공정에 의해 플러그로 사용될 폴리실리콘 이외의 폴리실리콘을 제거하여 플러그를 형성한다. 이 연마 공정시에는 플러그 폴리실리콘층(28)이 충분히 연마되도록 하며, 보호막(24)은 금속층간 절연막(23)을 보호하도록 1000 내지 2000Å 정도 잔류되도록 한다.As shown in FIG. 2F, the polysilicon other than the polysilicon to be used as the plug is removed by a chemical mechanical polishing process or a front etching process to form a plug. In this polishing process, the plug polysilicon layer 28 is sufficiently polished, and the protective film 24 is left in the range of 1000 to 2000 kPa to protect the interlayer insulating film 23.
도 2g에 도시된 바와 같이, 플러그 폴리실리콘층(28)을 통하여 반도체 기판(21)의 접합 영역과 접속되는 비트라인 등의 상부 배선층(29)을 형성한다. 이때 상부 배선층(29)은 저온 플라즈마 산화막인 보호막(24) 상에 형성되기 때문에 하층의 금속층간 절연막(23)의 유동성에 의한 변형 및 이동이 일어나지 않게 된다.As shown in FIG. 2G, an upper wiring layer 29 such as a bit line connected to the junction region of the semiconductor substrate 21 is formed through the plug polysilicon layer 28. At this time, since the upper wiring layer 29 is formed on the protective film 24 which is a low-temperature plasma oxide film, deformation and movement due to fluidity of the lower interlayer insulating film 23 do not occur.
상술한 바와 같이, 본 발명은 열적 유동성을 갖는 금속층간 절연막 상에 보호막을 형성한 이중 구조의 금속층간 절연막을 사용하는 경우, 플러그 콘택 홀을 형성하고 세정공정을 실시하기 전, 노출된 반도체 기판 상에 에피택셜막을 성장시키고 플러그 콘택 홀 측벽에 질화막 스페이서를 형성한 후 세정 공정을 실시하므로써, 금속층간 절연막과 보호막의 식각율 차이로 인한 플러그 콘택 홀 측면의 굴곡 현상을 방지할 수 있고, 열적 유동성을 갖는 금속층간 절연막 상부에 형성된 보호막에 의해 상부 배선층의 이동 및 변형을 억제할 수 있는 효과가 있다.As described above, in the case of using the dual-layer interlayer insulating film in which a protective film is formed on the interlayer insulating film having thermal fluidity, the present invention is directed to the exposed semiconductor substrate before forming the plug contact hole and performing the cleaning process. By growing the epitaxial film and forming the nitride spacer on the sidewall of the plug contact hole, the cleaning process can be performed to prevent bending of the side surface of the plug contact hole due to the difference in the etch rate between the intermetallic insulating film and the protective film. The protective film formed over the intermetallic insulating film has an effect of suppressing the movement and deformation of the upper wiring layer.
Claims (17)
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| KR1019990025762A KR100305206B1 (en) | 1999-06-30 | 1999-06-30 | Method of forming a intermetal insulating film in a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100449948B1 (en) * | 2002-05-18 | 2004-09-30 | 주식회사 하이닉스반도체 | Method for fabricating contact plug with low contact resistance |
| KR101076781B1 (en) | 2009-07-29 | 2011-10-26 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming using the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100449948B1 (en) * | 2002-05-18 | 2004-09-30 | 주식회사 하이닉스반도체 | Method for fabricating contact plug with low contact resistance |
| KR101076781B1 (en) | 2009-07-29 | 2011-10-26 | 주식회사 하이닉스반도체 | Semiconductor device and method for forming using the same |
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