KR100303327B1 - Apparatus for duplicating of memory in switching system and method thereof - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

The present invention relates to an apparatus and method for memory redundancy in an exchange system.

I. The technical problem to be solved by the invention

When the board is doubled to stabilize data in the exchange system, the memory of the doubled board is shared.

All. Summary of Solution of the Invention

SUMMARY OF THE INVENTION In accordance with an aspect of the present invention, there is provided an apparatus of a board for memory redundancy in an exchange system, comprising: a signal processor for outputting a control signal according to a chip select signal and a read / write signal for board selection and memory access; An output buffer for connecting the output signal to an external board or an internal input buffer, an input buffer for receiving a signal from the output buffer or an external board, a memory for storing data, and the signal processor A first buffer for receiving an output signal and connecting it to the memory, and outputting the chip select signal and the read / write signal for accessing an external memory or an internal memory through the signal processor when the signal is selected as an active board; It characterized in that it comprises a control unit.

la. Important uses of the invention

Used in memory redundancy in switching systems.

Description

Apparatus and method for memory redundancy in an exchange system {APPARATUS FOR DUPLICATING OF MEMORY IN SWITCHING SYSTEM AND METHOD THEREOF}

The present invention relates to an apparatus and method for using a memory in an exchange system, and more particularly, to an apparatus and method for redundancy of a memory used in an active board and a standby board.

The duplexing method of DRAM (DRAM: hereinafter referred to as 'DRAM') using the 68000 series of processors is shared between the active and standby boards on its own board through a local buffer. It's the way you access, and you do the refresh. When master wants to write data to slave. I could wait until the negative board wasn't refreshing or the wealth wasn't accessing my DRAM before I could use it. In this way, even though both major and negative DRAMs are currently written (CURRENT WRITE), they are less likely to be used at the same time. There was a problem that the DRAM cannot be updated at the same time.

Accordingly, it is an object of the present invention to provide an apparatus and method that can duplicate memory and use it in a redundant exchange system.

Another object of the present invention is to provide an apparatus and method capable of communicating with all of the redundant boards when switching by redundancy.

In order to achieve the above objects, the present invention provides a control signal according to a chip select signal and a read / write signal for board selection and memory access in an apparatus of a board for memory redundancy in an exchange system. A signal processor for outputting, an output buffer for connecting the signal output from the signal processor to an external board or an internal input buffer, an input buffer for receiving signals from the output buffer or external board, and data A memory for storing a memory, a first buffer for receiving an output signal of the signal processor and connecting to the memory, and accessing an external memory or an internal memory through the signal processor when the active board is selected. And a controller for outputting the chip select signal and the read / write signal.

1 is a block diagram schematically showing an embodiment according to the present invention.

FIG. 2 is a diagram illustrating a chip select circuit for reading and writing by a quirrent write method according to an exemplary embodiment of the present invention.

3 is a schematic block diagram for controlling a buffer according to an embodiment of the present invention.

4 is a block diagram illustrating a refresh operation according to an embodiment of the present invention.

5 is a diagram illustrating a flow of signal lines for resetting.

6 is a diagram illustrating a signal flow for communication of a controller.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Specific details appear in the following description, which is provided to aid a more general understanding of the present invention, and it should be understood by those skilled in the art that the present invention may be practiced without these specific details. It will be self explanatory. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

1 is a block diagram schematically showing an embodiment according to the present invention.

FIG. 2 is a diagram illustrating a chip select circuit for reading and writing by a quirrent write method according to an exemplary embodiment of the present invention.

3 is a schematic block diagram for controlling a buffer according to an embodiment of the present invention.

4 is a block diagram illustrating a refresh operation according to an embodiment of the present invention.

5 is a diagram illustrating a flow of signal lines for resetting.

6 is a diagram illustrating a signal flow for communication of a controller.

An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

In order to duplicate the two boards 180 and 190 in FIG. 1, the configuration according to the present invention should not only control the duplexing of all signal lines going out, but also has the following basic structure in duplication of memory. . In order to share data simultaneously while sharing memory (DRAM: 110) of two boards 180 and 190, not only redundancy of signal lines, but also sharing of chip selection and writing of data to DRAM of master and slave simultaneously It is necessary to use the method, control the outgoing buffer, and initialize the initialization control at the time of implementation.

When one of the two boards 180 and 190 is active, an operation for chip selection of the shared DRAM 110 in the master 180 and the slave 190 will be described below. In the general case, one of the two boards is given priority to make it active. In this case, the active board becomes the master 180 and the rest becomes the slave 190. At this time, in order to access the shared DRAM 110, the board which becomes the master 180 gives a chip select signal RAS (1) to the slave 190 board to select the shared DRAM of the slave board 190, and the magnetic board. The shared DRAM 110 is also selected as RAS (0). That is, the chip select signal RAS (1) provided by the master board 180 enters the chip select signal O_RAS of the slave board 190. On the motherboard, the two chip select signals cross each other. In this case, two chip select signals from the controller 100 are required. This is controlled by Read / Write. In this way you can do the parent lighting. This can be controlled as shown in FIG. Referring to FIG. 2, a process of selecting an internal DRAM with two chip select signal lines and performing a constant write on an external DRAM is illustrated. The important point here is to access the two DRAMs, accessing the two chip select signals separately for reading and writing according to the quaternary write method. You can also access DRAM on your board even when you are in a Stand by state, that is, when you become a slave.

There are four cases of accessing a shared DRAM.

First: Reading your DRAM from the active board: Internal access

Second: When writing to own DRAM from active board and not to DRAM of external slave board: Concurrent Disable

Third: Writing from the active board to its own DRAM and simultaneously writing to the external slave board's DRAM: Concurrent Write

Fourth: read your own DRAM from slave board

Since all programs are executed only on the active board, the slave board will not be able to update the memory even if there are new programs or information. You can also save data to a board in standby state at the same time. In this case, a Concurrent Enable signal is transmitted first, which informs the program to decide whether to access an external DRAM. The signal is sent from the master to the slave, and the slave receives this signal and opens a buffer of all signal lines coming from outside. In addition, the master sees the signal determined by S / W, decides whether to write data to an external DRAM, and sends the chip select signal to the outside.

The buffer control of the master and the slave is described below with reference to FIG.

First: When the master board writes both its own DRAM and the slave's DRAM.

Second: When a slave board reads its DRAM.

Third: When the master board reads its DRAM.

In the first case, since both the DRAM of the master and the slave are selected and must be writeable at the same time, the signal line 'act_en' is enabled (Enable) as shown in FIG. 3, and both the master and the slave enable 'ea_en' give. Then, the address and data connected from the back pin to the common are connected to the master and slave DRAMs so that they can be written at the same time.

In the second case, it is necessary to check and see the data of the DRAM of the slave board. In this case, 'la_en', which enables the buffer shown in FIG. 3 (local buffer: 160), is set to low, and read and write. This allows the DRAM to access the DRAM internally, even when the slave becomes a signal line without going out the back pin.

In the third case, the master board provides a path for reading its data. Once active and becoming a master, 'act_en' is enabled, so all signal lines must enter or exit via the back pin. Therefore, enable 'ea_en' and make it low when reading 'd_dir'. That is, if it is slave and read, 'ea_en' is not enabled.

This process duplicates two boards and writes data to the DRAM at the same time. If one board is transferred to the other, it can be transferred while maintaining the same data that the active board wrote data to the slave.

The refresh (REFRESH) process will be described with reference to FIG. 4. In order to preserve the data of the DRAM 110, a refresh cycle is provided. This operation must be done during the refresh cycle or data will not be preserved. Therefore, when data is transferred while reading and writing for redundancy, the 'RAS' and 'CAS' signal lines of the DRAM 110 are received from the master, and thus the refresh cannot be performed within the refresh period. Therefore, to prepare for such a case, when the transfer is performed, if the slave performs the 'CAS' before the 'RAS' cycle to refresh the slave, the pin indicating the refresh is given to the slave. This is timed using the GPLA 3 coming from the controller 100 (eg 'MPC860').

When 'o_refsh' becomes 'low', the slave knows that it is refreshed and does not open the data or address buffer even if the chip is selected. This allows the master to access and refresh the slave.

Referring to the reset process with reference to FIG. 5, even if the two redundant boards are considered in the same manner as described above, once initialized due to a sudden error or board failure, the data of the DRAM cannot be updated or preserved. Another way to duplicate the two boards and more securely preserve the data on the DRAM is to prevent the reset process from being directly initiated by a switch or power supply. As a result, the reset operation is performed. When the reset signal is received, the controller 100 is interrupted (Interrupt 0 = IRQ (0)).

During the reset, the master board can be reset after performing an interrupt process that passes data to the slave board's DRAM. After the reset, all data is transferred and then transferred to the slave board. It also allows the reset from the active board to the standby board. The reset pin to the control unit 100 should be bidirectional, and the control pin is provided to the tristate output from the control circuit 170.

A communication process of the controller will be described below with reference to FIG. 6. Along with the above redundancy method, there is a need for a way to check the board status while always communicating between two redundant master and slave boards. At this time, there can be various methods. SPI provided by MPC860 using HDLC protocol can be used. Here, the SPI communication method is used. These signal lines must be enabled at all times, active or standby, and only need to control the direction. This path allows two boards to communicate with each other as simple data, regardless of whether they are active or slave to each other.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims below, but also by the equivalents of the claims of the present invention.

As described above, in the present invention, the signal line is duplicated between the master board and the slave board and the control signal is added to duplicate the memory, so that the two boards are always active when they are reset and transferred while exchanging their states. There is no need to lose any data the board has or write data to the slave when it is rebooted. In addition, since the data can be stored in the slave as it is, it can be transferred while keeping the data. In addition, by using the Concurrent light method, data can be written to the master and the slave at the same time, thereby increasing efficiency.

Claims (8)

In the apparatus of the board for memory redundancy in the switching system, A signal processor for outputting a control signal according to a chip select signal and a read / write signal for board selection and memory access; An output buffer for connecting the signal output from the signal processor to an external board or an internal input buffer; An input buffer for receiving a signal from the output buffer or an external board; A memory for storing data, A first buffer for receiving an output signal of the signal processor and connecting the first signal to the memory; And a controller for outputting the chip select signal and the read / write signal for accessing an external memory or an embedded memory through the signal processor when the active board is selected. The method of claim 1, wherein the signal processing unit, A first orifice for ORing the chip select signal and the read / write signal for accessing the internal memory; A second orifice for ORing the inverted signal with the chip select signal and the read / write signal; A third orifice for ORing the chip select signal and the inverted read / write signal for accessing the memory of the external board; A first AND gate for ANDing the output signals of the first and second OA gates; And a second end gate for ANDing the output signal of the first and third orifices. The method of claim 1, And a second buffer for controlling the memory by buffering a control signal output from the controller. A signal processor for outputting a control signal according to a chip select signal and a read / write signal for board selection, an output buffer for connecting the signal output from the signal processor to an external board or an internal input buffer, Redundancy in an exchange system having a first buffer for receiving an output signal from a signal processor or a control unit and connecting it to the memory, an input buffer for receiving a signal from the output buffer or an external board, and a memory for storing data In the buffer control method for memory access of a board, Enabling the input / output buffers of the master and slave boards when performing a write operation by accessing all of the memories of the master board and the slave board in the switching system; Disabling the I / O buffer of the slave board when reading the data of the internal memory from the slave board; Disabling the input / output buffer and enabling the first buffer to perform buffering; Enabling the output buffer when reading data from the built-in memory on the master board, A signal output through the output buffer is input to the memory through the input buffer of the master board to enable the input buffer to read the memory, and an input buffer for receiving a signal from an external slave board Disabling a process characterized in that the process. In the memory refresh method of the redundant board in the switching system, Transmitting a refresh message from the master board to a slave board when the master board is switched; And if the message is received by the slave board, directly performing a memory refresh operation of the slave board. The memory refresh operation of the slave board according to claim 5, wherein: Method which is made through FIFA. The method of claim 5, wherein when the message is received at the slave board, And disabling an input / output buffer of the slave board. In the memory reset method of a redundant board in a switching system, Updating the data of the internal memory of the master board to the memory of the slave board when reset data is generated in the master board; Transitioning the active board to the slave when the update process is completed; And resetting the master board.