KR100303204B1 - Fifo device having variable i/o width - Google Patents

Abstract

PURPOSE: A FIFO(First In First Out) device having the variable I/O width is provided to possess the variable data I/O width capable of independently controlling the data I/O width and to facilitate an interface between systems without an additional circuit and part. CONSTITUTION: The device comprises a FIFO(30) having a variable I/O width, a data input controller(20) converting the system bus width of input part into the width of FIFO bus, a data output controller(40) converting the width of FIFO bus into the system bus width of output part, a mode controller(50) controlling the width selection of FIFO I/O data and the operation for each bite, and a flag generator(60) displaying the internal state of FIFO. The mode controller is equipped with an input control counter, an output control counter, an input mode controller connecting to the input counter, an output mode controller connecting to the output counter.

Description

Apparatus of First In First Out with Variable Input / Output Width and Depth

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data interface device. In particular, first in first having a variable input / output width that enables an interface between systems having different data bus widths to be easily adjusted by independently controlling the input / output width of data. Out (FIFO) device.

In general, a first-in first-out method is mainly used as a data interface method between two systems. Conventional first-in, first-out interface apparatus requires an additional buffer and timing control circuit to adjust the difference in bus width for an interface between two systems having different data bus widths.

1 is a circuit diagram showing an example of a first-in, first-out device for interfacing two systems having different data bus widths. The first-in, first-out device of Fig. 1 includes a 16-bit FIFO 4 connected to a 16-bit system 2, an 8-bit buffer 6 and an 8-bit latch 8 commonly connected to the FIFO 4, and a buffer 6 And three-phase buffers 12 and 14 connected to the latch 8 and the buffer 8, respectively, and a buffer control unit 10 connected to the latch 8, three-phase buffers 12 and 14 and the FIFO 4, respectively. ) And an 8-bit system 16 commonly connected to the three-phase buffers 12 and 14 and connected to the buffer control unit 10.

FIG. 2 shows an operation timing diagram of the first-in first-out device shown in FIG.

In the FIF0 device of FIG. 1, the 16-bit system 2 checks the full-flag input from the FIFO 4 and transmits data. In detail, the 16-bit system 2 enables the write enable at the time T1 when the full flag signal full_flag in the low state is input from the FIFO 4, that is, when the FIFO 4 is not full. Apply a signal wen and transmit 16-bit data (FDI).

The FIFO 4 stores the 16-bit data FDI input through the data bus, and sets the empty flag (empty_flag) to Not Empty at the time T2. The 8-bit system 16 checks the empty flag (empty_flag) of the FIFO 4 to read enable at the time T3 when the sick empty state is input, that is, when the low empty empty flag signal is input. The signal ren is output to the buffer control unit 10. Subsequently, the buffer controller 10 applies an out enable signal oen to the FIFO 4 so that 16-bit data is output from the FIFO 4. The buffer controller 10 applies a latch enable signal lat_en to the 8-bit latch 8 so that the upper 8 bits of the 16-bit data FDO output from the FIFO 4 through the data bus. Data is stored in the 8-bit latch 8, and the lower 8-bit data is passed through the 8-bit buffer 6.

Then, the buffer controller 10 applies the even byte enable signal ev_en to the three-phase first buffer 12 by applying the first read enable signal ren to lower 8-bit data. (BFDL) is sent to the 8-bit system 16. In addition, the buffer controller 10 outputs an odd byte enable signal od-en to the second buffer 14 by the second read enable signal ren applied at the time T4. The upper 8-bit data BFDH stored in 8) is applied to the 8-bit system 16.

As such, the conventional FlFO device additionally needs a buffer and a timing control circuit to adjust the difference in bus width when interfacing between two systems having different bus widths. Accordingly, in terms of the FIFO maker, the production line and process of the chip are complicated because the FIFO chips according to the bus widths, such as 8 bits, 16 bits, and 32 bits, must be produced separately.

Accordingly, it is an object of the present invention to provide a first-in first-out apparatus having a variable input / output width that can independently adjust the input / output width of data.

Another object of the present invention is to provide a first-in, first-out apparatus having a variable input / output width that can easily interface between systems without requiring additional circuits and components by independently adjusting the input / output width.

It is still another object of the present invention to provide a first-in, first-out device having a variable input / output width capable of unifying a production line and a process by adjusting the input / output width by providing a plurality of FIFO chips having the same capacity.

1 is a circuit diagram showing a conventional first-in, first-out device connected to two systems.

FIG. 2 is an operation timing diagram of the first-in first-out device shown in FIG.

3 is a block diagram showing a first-in, first-out apparatus with a variable input / output width according to the present invention.

4 is a diagram illustrating a data input controller and a mode controller of FIG. 3;

FIG. 5 is a view showing a data output controller and a mode controller of FIG. 3; FIG.

FIG. 6 is a detailed view of the mode control unit of FIG. 3; FIG.

FIG. 7 is a view showing a flag generator of FIG. 3; FIG.

8 is an operation timing diagram of a first-in, first-out device according to the output mode of the mode control unit of FIG.

* Explanation of symbols for main parts of the drawings

20: data input control unit 22, 24, 26: first to third input mux

30: FIFO 40: data output control unit

42, 44: first and second output mux 50: mode control unit

52: input control counter 54: input mode control unit

56: output control counter 58: output mode control unit

60: flag generator

In order to achieve the above object, the first-in first-out device having the variable input / output width according to the present invention converts the first-in first-out means for interfacing between two systems having different bus widths, and the data width of the input-side system into the data width of the first-in first-out means. Data input control means for converting the data width of the first-in first-out means to the data width of the system on the output side, and data input and output means according to the mode signals input from two systems having different bus widths. And a mode control means for selecting the data width and controlling the byte-by-byte operation of the first-in first-out means in accordance with the mode signal.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 8.

3 is a circuit diagram showing the configuration of a first-in, first-out device having a variable input / output width according to the present invention. The first-in, first-out device having the variable input / output width of FIG. A flag indicating the internal state of the FIFO 30, the data output control unit 40 for converting to the system bus width on the output side, the mode control unit 50 for adjusting the input / output data width of the FIFO 30, and the operation for each byte. The generator 60 is provided.

The data input controller 20 of FIG. 3 converts the system bus width of the input side to the 32-bit bus width of the FIFO 30. As illustrated in FIG. 4, the data input control unit 20 receives data input from the data input bus DIN according to the input select signal ISEL applied from the mode control unit 50, for each byte, from the first to fourth FIFOs. Output to the input buses FI0, FI1, FI2, and FI3. Here, the input select signal ISEL applied from the mode controller 50 is a signal corresponding to the input mode IMODE applied from the system on the input side, and the input data width of the data input controller 20 is applied from the input side system. It can be seen that it is set according to the input mode (IMODE). The 32-bit data input bus DIN [31: 0] is an 8-bit first to fourth data input bus DIN [7: 0], DIN [15: 8] having a sequential address as shown in FIG. ], DIN [23:16], DIN [31:24]). Then, the data input control unit 20 assigns each of the data input buses DIN [7: 0], DIN [15: 8], DIN [23:16], DIN [31:24] to the input select signal ISEL. And first to third input multiplexers (hereinafter referred to as MUXs) that are selected accordingly and connected to the first to fourth FIFO input buses FI0, FI1, FI2, and FI3, respectively. do.

In detail, when the input data width is 32 bits, the data input control unit 20 outputs 32 bits of input data to the first to fourth FIFO input buses FI0, FI1, FI2, and FI3 for each byte. In other words, when the 32-bit input mode IMODE [1: 0] = 1O is applied from the input side system, the mode controller 50 inputs the input select signal ISEL [1: 0] = 10 corresponding thereto. Output to the first to third input mux 22, 24, 26 of the control unit 20. Accordingly, the first to third input muxes 22, 24, and 26 respectively select the second to fourth data input buses DIN [15: 8], DIN [23:16], and DIN [31:24]. The second to fourth FOFO input buses FI1, FI2, and FI3 are connected.

On the other hand, when the input data width is 16 bits, the data input control unit 20 receives the 16-bit data input through the lower 16-bit data input bus DIN [15: 0] from the first and second FIFO input buses FI0. , FI1 and the third and fourth FIFO input buses FI2 and RI3. Here, the data input bus DIN [31:16] of the upper 16 bits is not used. In other words, when the 16-bit input mode IMODE [1: 0] = 01 is applied from the input system, the mode controller 50 inputs the input select signal ISEL [1: 0] = 01 corresponding thereto. Output to the control unit 20. Accordingly, the first input mus 22 connects the second data input bus DIN [15: 8] to the second FIFO input bus FI1, and the second and third input muxes 24 and 26 are connected. The first and second data input buses DIN [7: 0], DIN [15: 8] are connected to the third and fourth FIFO input buses FI2, FI3.

Similarly, when the input data width is 8 bits, the data input control unit 20 receives 8-bit data input through the least significant 8-bit data input bus DIN [7: 0], respectively, from the first to fourth FIFO input buses FI0. , FI1, FI2, and FI3). Here, the data input bus DIN [31: 8] of the upper 24 bits is not used. In other words, when the 8-bit input mode IMODE [1: 0] = 00 is applied from the input side system, the mode controller 50 outputs the corresponding input select signal ISEL [1: 0] = 00. Output to (20). Accordingly, the first to third input muxes 22, 24, and 26 connect the first data input bus DIN [7: 0] to each of the second to fourth FIFO output buses FI1, FI2, and FI3. Let's do it.

The data output control unit 40 in FIG. 3 converts the output bus width of the 32-bit FIFO into the system bus width on the output side. As shown in FIG. 5, the 32-bit data input from the first to fourth FIFO output buses FO0, FO1, FO2, and FO3 are respectively converted according to the output select signal OSEL applied from the mode controller 50. Output to the output bus (DOUT [31: 0]). Here, the output select signal OSEL applied from the mode control unit 50 is a signal corresponding to the output mode IMODE applied from the system on the output side, and the output data width of the data output control unit 40 is the output mode OMODE. It can be seen that depends on. The 32-bit data output buses DOUT [31: 0] have four 8-bit data output buses DOUT [7: 0], DOUT [15: 8], and DOUT [with sequential addresses as shown in FIG. 23:16], DOUT [31:24]). The data output control unit 40 selects each of the first to fourth FIFO output buses FO0, FO1, F02, and FO3 according to the output select signal OSEL, thereby allowing the first and second data output buses DOUT [7]. : 0] and DOUT [15: 8]) and first and second output muxes 42 and 44 respectively.

In detail, when the output data width is 32 bits, the data output control unit 40 receives the 32 bit data input through the first to fourth FIFO output buses FO0, FO1, FO2, and FO3 from the 32 bit data output bus DOUT. [31: 0]). At this time, the output count (OCNT) value is ignored, the output count (OCNT) is input from the mode control unit 50 will be described later. In other words, when the 32-bit output mode OMODE [1: 0] = 1O is applied from the output side system, the mode control unit 50 outputs an output select signal OSEL [1: 0] = 10 corresponding thereto. Output to the first and second output mux (42, 44) of the control unit 40. Accordingly, the first and second output muxes 42 and 44 respectively connect the first and second FIFO output buses FOO and F01 to the first and second data output buses DOUT [7: 0] and DOUT [15]. : 8]) to each of them.

On the other hand, when the output data width is 16 bits, the data output control unit 40 may use 16-bit data through the fourth and third FIFO output buses F03 and F02, and the second and first FIFO output buses F01 and F00. 16-bit data inputted through is alternately selected according to the output count (OCNT) value and output to the lower 16-bit data output bus (DOUT [15: 0]). In other words, when the 16-bit output mode OMODE [1: 0] = 01 is applied from the output side system, the mode controller 50 outputs an output select signal OSEL [1: 0] = 01 corresponding thereto. Output to the first and second output mux (42, 44) of the control unit 40. At the same time, the mode controller 50 outputs the output count (OCNT) to the first and second output muxes 42 and 44. When the output count value OCNT is an even value, the first and second output muxes 42 and 44 respectively connect the third and fourth FIFO output buses FO2 and FO3 to the first and second data output buses DOUT [. 7: 0] and DOUT [15: 8]). In addition, when the output count value OCNT is an odd value, the first and second output muxes 42 and 44 may connect the first and second FIFO output buses F00 and F01 to the first and second data output buses, respectively. DOUT [7: 0], DOUT [15: 8]) respectively.

When the output data width is 8 bits, the data output control unit 40 sequentially processes 8-bit data input through each of the fourth to first FIFO output buses F03, F02, F01, and F00 according to the output count value OCNT. Select to output to the lowest 8-bit data output bus (DOUT [7: 0]). In other words, when the 8-bit output mode OMODE [1: 0] = 00 is applied from the output side system, the mode controller 50 outputs the corresponding output select signal OSEL [1: 0] = O0 and the output count. (OCNT) is output to the first output mux 42 of the data output controller 40. Accordingly, the first output mux 42 outputs each of the fourth to first FIFO output buses FO3, FO2, FO1, and FO0 according to the output count value OCNT. ) Sequentially

The FIFO 30 of FIG. 3 includes first to fourth FIFOs 32, 34, 36, and 38 for storing data in 8-bit units. The first to fourth FIFOs 32, 34, 36 and 38 are respectively connected to the first to fourth FIFO input buses FI0, FI1, FI2 and FI3 and the output buses FO0, FO1, FO2 and FO3, respectively. The data is stored or output by the write enable signal WE and the read enable signal RE applied from the mode controller 50 to each.

The mode controller 50 of FIG. 3 plays a role of selecting the input / output data width of the FIFO and adjusting the operation of each byte. To this end, the mode controller 50 includes an input control counter 52 and an output control counter 56, an input mode controller 54 connected to the input control counter 52, and an output control as shown in FIG. An output mode control unit 58 connected to the counter 56 is provided.

In the mode controller 50 of FIG. 6, the input control counter 52 increases the count value according to the write signal WR input from the outside in the form of a pulse and outputs the count value to the input mode controller 54. Here, the input control counter 52 increments the count value by 1 for each falling edge portion (Falling_edge) of the write signal WR, counts up to 4, and clears it. The input mode control unit 54 controls an input select (ISEL) signal for controlling the first to third input muxes 22, 24, and 26 of the data input control unit 20 and a write enable signal for the FIFO 30. It serves to generate. The input mode controller 54 generates the first to fourth write enable signals WE [3: 0] according to the count value input from the input control counter 54 to generate the first to fourth FIFOs 32,. 34, 36, and 38) to record data for each byte.

In detail, when the 32-bit input mode is applied from the system on the input side as shown in FIG. 8A, the input mode control unit 54 generates an input control counter 52 each time a write signal WR is generated. Each time a value is output, all of the write enable signals WE [3: 0] are applied to the write pointers of the first to fourth FIFOs 32, 34, 36, and 38. Accordingly, since the first to fourth FIFOs 32, 34, 36, and 38 simultaneously store data of 1 byte unit input through the respective input buses FI0, FI1, FI2, and FI3, the FIFO is 4 bytes in total. (32-bit) data will be stored.

As shown in FIG. 8B, when the 16-bit input mode is applied, the input mode control unit 54 outputs a lower half word when an even value is output from the input control counter 52, that is, an even-numbered write WR signal is generated. The first and second write enable signals WE [1] and WE [0] corresponding to the lower half words are applied to the write pointers of the first and second FIFOs 32 and 34. Similarly, when the odd value is output from the input control counter 52, that is, when the odd number write signal WR is generated, the third and fourth write enable WE [1] corresponding to the upper half word. , WE [0]) is applied to the write pointers of the third and fourth FIFOs 36 and 38. Accordingly, the first and second FIFOs 32 and 34 and the third and fourth FIFOs 36 and 38 alternately store 16-bit data as the write WR signal is generated.

As shown in FIG. 8C, when the 8-bit input mode is applied, the input mode control unit 54 transmits each of the write enable signals WE [3: 0] to the first through fourth signals according to the output value of the input control counter 52. The FIFOs 32, 34, 36, 38 are sequentially applied. In detail, the input mode controller 54 outputs the first write enable WE [0] signal by the first (ICNT = 0) write WR signal, and the second (ICNT = 1) write WR signal. By the second write enable (WE [1]) signal and the third (ICNT = 2) write (WR) signal by the third write enable (WE [2]) and fourth (ICNT = 3) write (WR) signals. Outputs the fourth write enable WE [3]. Accordingly, the first to fourth FIFOs 32, 34, 36, and 38 sequentially store 8-bit data as the write WR signal is generated.

In the mode control unit 50 of FIG. 6, the output control counter 56 outputs the count value increased according to the read (RD) signal input in the form of pulse from the outside to the output mode control unit 58 and the data output control unit 40. do. Here, the output control counter 56 increases the count value by 1 for each falling edge of the read (RD) signal, counts up to 4, and clears it. The output mode controller 58 generates an output select (OSEL) signal for controlling the first and second output muxes 42 and 44 of the data output controller 40 and a read enable signal RE of the FIFO 30. It plays a role. The output mode control unit 58 generates the first to fourth read enable signals RE [3: 0] according to the count value input from the output control counter 56, thereby generating the first to fourth FIFOs 32. , Data can be read byte by byte from (34, 36, 38).

In detail, when the 32-bit output mode (OMODE [1: 0] = 10) is applied from the output side system as shown in FIG. 8A, the output mode control unit 58 generates a write (WR) signal every time. Every time, i.e., every time the value of the output control counter 56 is outputted, all of the read enable signals RE [3: 0] are read from the read pointers of the first to fourth FIFOs 32, 34, 36, and 38. Pointer). As a result, each of the first to fourth FIFOs 32, 34, 36, and 38 simultaneously outputs one byte of data through the output buses FOO, F01, F02, and F03, so that the FIFO 30 totally 32 bits. Will output the data.

As shown in Fig. 8B, when the 16-bit output mode OMODE [1: 0] = 01 is applied, the output mode control unit 58 generates an output control counter 56 whenever an even-numbered read signal RD occurs. Each time an even value is output from the first and second read enable signals RE [1] and RE [0], the first and second FIFOs 32, Is applied to the lead pointer of 34). Similarly, every time an odd-numbered write signal RD occurs, that is, whenever an odd value is output from the output control counter 56, the third and fourth read enable signals RE corresponding to the upper half word RE are generated. [2], RE [3]) is applied to the read pointers of the third and fourth FIFOs 36 and 38. As a result, the first and second FIFOs 32 and 34 and the third and fourth FIFOs 36 and 38 alternately output 16-bit data as the read RD signal is generated.

As shown in Fig. 8C, when the 8-bit output mode OMODE [1: 0] = 00 is applied, the output mode controller 58 reads the lead enable RE [3: 0 according to the output value of the output control counter 56. ]) Is applied to the first to fourth FIFO (32, 34, 36, 38) sequentially. In detail, the output mode controller 58 outputs the first read enable signal RE [0] by the first (ICNT = 0) read RD signal, and the second (ICNT = 1) read RD signal. The second lead enable RE [1] signal and the third (ICNT = 2) lead RD signal by the third lead enable RE [2] and the fourth (ICNT = 3) lead RD The fourth lead enable RE [3] is output by the signal. As a result, the first to fourth FIFOs 32, 34, 36, and 38 sequentially output 8-bit data as the read RD signal is generated.

As shown in Fig. 7, the flag generator 60 of Fig. 3 serves to inform the external system (i.e., the system on the input and output side) of the internal state from the information of the write pointer and the read pointer of the FIFO 30. do. Here, EF (Empty Flag) is a flag indicating that the FIFO 30 is all empty and there is no data to be read anymore. If EF = 1, the empty flag indicates an empty state. HF (Half Flag) is a flag indicating the state in which the FIFO 30 is recorded in more than half. HF = 1 indicates more than half the recorded state, and HF = O indicates half or less recorded state. FF (Full Flag) is a flag indicating that the FIFO 30 is full and no more data can be recorded. If FF = 1, the flag is full. If FF = 0, the flag is not full.

As described above, the first-in first-out device having the variable width according to the present invention can easily perform the interface between the systems by adjusting the difference in the bus width of the input and output system. In addition, the first-in, first-out device having a variable width according to the present invention includes a plurality of FIFO chips in units of bytes and enables them according to the bus width, thereby eliminating the need for each FIFO chip according to the bus width as in the prior art. As a result, a single FIFO chip can be produced, thereby unifying production lines and processes into one.

On the other hand, it will be appreciated by those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (17)

First-in, first-out means for interfacing between two systems having different bus widths, data input control means for converting the data width of the input-side system into the data width of the first-in, first-out means, and the data width of the first-in, first-out means. A data output control means for converting the data width into a data width, and selecting a data width of the data input and output means in accordance with a mode signal input from two systems having different bus widths, and byte of the first-in first-out means according to the mode signal. A first-in, first-out apparatus having a variable input / output width, comprising mode control means for controlling a respective operation. 2. The variable input / output width according to claim 1, further comprising flag generation means for informing two systems having different bus widths whether or not data can be written in the first-in first-out means in response to a signal from the mode control means. First-in, first-out device having a. The first-in first-out apparatus having a variable input / output width according to claim 1, wherein the first-in first-out means comprises first to fourth first-in, first-out means operating in byte units. The method of claim 1, wherein the data input control means selects data input from an input side system among two systems having different bus widths in byte units according to an input select signal of the mode control means, and the second to fourth first-in-first-out. A first-in, first-out apparatus having a variable input / output width, comprising first to third multiplexers for outputting to each input bus of the means. The first-in first-out apparatus having a variable input / output width according to claim 4, wherein the input select signal is a signal corresponding to an input mode signal input from the input side system to the mode control means among two systems having different bus widths. The first-in first-out apparatus having a variable input / output width according to claim 4, wherein the lowest one byte input from an input side system among the two systems having different bus widths is output as it is to the input bus of the first first-in first-out means. The data output control means according to claim 1, wherein the data output control means selects one of the first to fourth output buses of the first-in, first-out means according to the force select signal and the output count signal of the mode control means to connect the output bus. And a first multiplexer and a second multiplexer for selecting any one of the second and fourth output buses of the first-in first-out means according to the output select signal and the output count signal of the mode control means and connecting them to the output bus. A first-in, first-out device having a variable input and output width. The first-in first-out apparatus with a variable input / output width according to claim 7, wherein the output select signal is a signal corresponding to an output mode signal input from the output side system to the mode control means. 2. The apparatus of claim 1, wherein the mode control means comprises an input control means for generating an input select signal for controlling the multiplexer of the data input control means and a write enable signal for the first-in first-out means, and a multiplexer for the data output control means. An input first-in first-out apparatus having a variable input / output width, comprising: an output select signal for controlling, an output count signal, and an output control means for generating a lead enable signal of the first-in first-out means. 10. The apparatus of claim 9, wherein the input control means includes input control counting means for counting a read signal input from an input side system among two systems having different bus widths, and an input mode inputted from an input side system among two systems having different bus widths. And input mode control means for generating an input select signal and a write enable signal in accordance with a signal and a count value input from said input control count means. 10. The apparatus of claim 9, wherein the output control means includes output control counting means for counting a write signal input from an output side system among two systems having different bus widths, and an output input from an output side system among two systems having different bus widths. And an output mode control means for generating an output select signal and a lead enable signal in accordance with a mode signal and a count value input from said output control count means. 12. The apparatus of claim 10, wherein the input mode control means has a variable input / output width characterized in that all of the first to fourth write enable signals are applied according to the input control count value when the input mode indicates 32 bits. First-in, first-out device. 11. The method of claim 10, wherein the input mode control means alternates between the first and second write enable signals and the third and fourth write enable signals according to the input control count value when the input mode indicates 16 bits. First-in, first-out device having a variable input and output width, characterized in that the application. The variable input / output width according to claim 10, wherein the input mode control means sequentially applies each of the first to fourth write enable signals according to the input control count value when the input mode indicates 8 bits. First-in, first-out device having a. 12. The variable input / output width of claim 11, wherein the output mode control means applies all of the first to fourth read enable signals according to the output control count value when the output mode indicates 32 bits. First-in, first-out device. 12. The method of claim 11, wherein the output mode control means alternates between the first and second lead enable signals and the third and fourth lead enable signals according to the output control count value when the output mode indicates 16 bits. First-in, first-out device having a variable input and output width, characterized in that the application. 12. The variable input / output width according to claim 11, wherein the output mode control means sequentially applies each of the first to fourth read enable signals according to the output control count value when the output mode indicates 8 bits. First-in, first-out device having a.