KR100284564B1 - How to convert data speed - Google Patents

Abstract

According to the present invention, when a data is written and read out using a first-in first-out (FIFO) between two convex processing data, a write clock and a read clock are generated in advance according to the data processing capability between the two convex to write and read the first-in first-out. The present invention relates to a data processing speed conversion method for smoothly writing and reading data even when the data processing speed between the two convexities is different. The present invention relates to a write clock and a readout of a first-in-first-out machine that records and reads data. Calculating a write and read minimum integer value at which the clock has a minimum integer ratio; Calculating a final write control value by adding an appropriate value convenient for circuit control to the system to the calculated write and read minimum integer values; Comparing the data processing speed between the write block for recording data and the read block for reading the recorded data after calculating the write control value and controlling the enable and disable times of the write control value according to the magnitude relationship; It will be executed sequentially.

Description

How to convert data speed

The present invention relates to a rate conversion method, and in particular, when data is recorded and read using a first-in first-out (FIFO) between two convex processing data, the data is recorded in advance according to the data processing capability between the two convex. The present invention relates to a data rate conversion method for generating a clock and a read clock to control writing and reading of a first-in, first-out, so that data can be written and read smoothly even when the data processing rates between the two convexities are different.

In general, a digital signal processing system uses first-in first-out (FIFO) for data rate conversion if the data rates between the two convexities are different.

In this case, first-in, first-out uses a full flag and an empty flag to indicate an internal state due to a difference in input / output data rates.

In this case, when the two signals are used, the state of the FIFO is continuously monitored to continuously change the input / output of the data according to the changed state.

1 is an example of a data processing speed control apparatus using the FIFO as described above.

As shown therein, data recording for generating an appropriate recordable signal WEN and a data output control signal by the externally transmitted write clock WCLK and the first-in-first-out FIFO generated by the full flag / FF. An input data path controller 2 for controlling output of data input in synchronization with the externally written clock clock WCLK by a data output control signal generated by the data recording controller 1; And a data read control section (3) for generating an appropriate readable signal (REN) and a data output control signal by means of the read clock (RCLK) transmitted from the outside and the empty flag (/ EF) obtained from the first-in, first-out (5). And output data for outputting data output from the first-in-first-out-outer 5 in synchronization with the read clock RCLK according to a data output control signal generated by the data readout control unit 3. The data output from the input data path control section 2 can be recorded in accordance with the path control section 4 and the data recordable signal obtained from the data recording control section 1, and the data reading control section 3 can read the data. It consists of a first-in, first-out (5) outputting the stored data in accordance with the signal and generating a full flag (/ FF) and an empty flag (/ EF) in accordance with the state of the internal write and read buffer.

The conventional data processing speed control device configured as described above is capable of recording a recordable signal according to the recording clock WCLK inputted from the recording block by the data recording control section 1 and the full flag / FF signal obtained by the first-in first-out-outer 5. WEN) is generated and provided to the first-in, first-out machine 5, and when a record is possible, a data output control signal is generated and transmitted to the input data path controller 2.

Then, the input data path controller 2 determines whether to output the input data Data In according to the data output control signal, and transmits the input data to the first-in, first-out selector 5 during data output.

On the other hand, the data read control section 3 generates the readable signal REN by the read clock RCLK transmitted from the block for processing data and the empty flag / EF obtained by the first-in-first-out 5. It delivers to the first-in, first-out (5), and at the same time delivers the data output control signal to the output data path control unit (4).

Accordingly, the output data path control unit 4 transfers the data output from the first-in first-out (5) to the data processing block at a later stage.

The first-in-first-outer 5 records the input data in accordance with the writeable signal WEN obtained from the data recording control unit 1 and the readable signal REN obtained from the data reading control unit 3, or records the input data. When the data processing speed between the input block and the convex that processes the data is changed, the data recording amount and the data output amount of the internal buffer are changed so that a signal called a data pool or a data empty is output. Will occur.

That is, when the speed of writing data to the first-in, first-out 5 is faster than the reading speed, the first-in, first-out 5 generates a full flag / FF to transfer to the data recording control unit 1. On the contrary, when the data reading speed is faster than the data writing speed, the empty flag / EF is generated and transmitted to the data reading control section 3.

At this time, if a full flag is generated from the first-in-first-out (5), the block for recording data in the first-in-first-out (5) should temporarily stop the operation of writing data to the first-in-first-out (5) to prevent data loss. When the empty flag is generated from the first-in, first-out 5, the block for reading data from the first-in, first-out 5 must suspend the data reading operation.

Therefore, in order to prevent data errors in the first-in-first-out (5), it is necessary to configure an appropriate write and read control circuit with reference to the flag generated in the first-in-first-out in the write or read block. It causes problems that make the design difficult and increase the complexity.

Accordingly, the present invention has been proposed to solve various problems generated in the data processing speed control apparatus using the conventional first-in, first-out.

In the present invention, when writing and reading data using a first-in first-out (FIFO) between two convex processing data, a write clock and a read clock are generated in advance according to the data processing capability between the two convex to record and read first-in-first-out. It is an object of the present invention to provide a data processing speed conversion method that allows data to be written and read smoothly even when the data processing speed between the two convexities is different.

The present invention (method) for achieving the above object,

Calculating a write and read minimum integer value having a minimum integer ratio between the write clock and the read clock of the first-in, first-out machine that writes and reads data;

Calculating a final write control value in consideration of an appropriate value for which circuit control is convenient for the system to the calculated write and read minimum integer values;

Calculating the write control value and comparing the data processing speed between the write block for recording the data and the read block for reading the recorded data and controlling the enable and disable time of the write control value according to the magnitude relationship; Is done.

In the above, if the write speed is greater than the read speed after the data processing speed comparison, the write is enabled by the read clock and the remaining write time is disabled. If the write speed is less than the read speed, the write clock is written. It is characterized by disabling the recording as much as the remaining read clock.

1 is an example of a data processing speed control apparatus using a conventional FIFO;

2 is a block diagram of a data processing speed converter using a FIFO to which the present invention is applied;

3 is an input / output timing diagram of each unit at the time of converting data processing speed in the present invention.

(a) is a part input / output timing chart when the write clock is larger than the read clock,

(b) is an input / output timing chart of each part when the read clock is larger than the write clock.

4 is a control flowchart showing a data processing speed conversion method according to the present invention;

<Explanation of symbols for main parts of the drawings>

10: data recording control unit 20: input data path control unit

30: data reading control part 40: output data path control part

50: first-in, first-out machine

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2 is a block diagram of a data processing rate converting apparatus using a FIFO to which the present invention is applied.

As shown in the drawing, the write clock WCLK transferred from the write block for writing data to the FIFO and the read clock obtained from the read block for reading the data written to the FIFO are compared, and the write enable signal ( A data recording control unit 10 controlling WEN and a data output control signal generated by the data recording control unit 10 to control the output of data input in synchronization with the externally written recording clock WCLK. A data read control section for generating a data output control signal while simultaneously generating a readable signal REN in accordance with the input data path control section 20 and a read clock RCLK transmitted from a read block for reading data written to the FIFO. 30 and the first-in, first-out in synchronization with the readout clock RCLK in accordance with a data output control signal generated by the data readout control unit 30. An output data path control unit 40 for outputting data output from the device 50 and data output from the input data path control unit 20 in accordance with a data recordable signal obtained from the data recording control unit 10; And a first-in, first-out machine (50) for outputting the stored data in accordance with the data readable signal obtained by the data reading control unit (30).

4 is a control flowchart illustrating a data processing speed conversion method according to the present invention.

Calculating a minimum integer value (x, y) having a minimum integer ratio between the write clock and the read clock of the first-in, first-out, as shown therein; Comparing the magnitude relationship between the write clock and read clock; If the speed of the write clock is faster than the speed of the read clock, writing as much as the read clock when writing data and disabling recording for the remaining write time; When the speed of the write clock is slower than the speed of the read clock, recording is performed by a write clock, and the write is disabled by the remaining read clock.

Referring to Figures 1 to 4 attached to the data processing speed conversion method according to the present invention made as described above in detail as follows.

First, the data write control unit 10, in the state initialized by the clear signal, when the write clock WCLK is input, the read clock RCLK obtained from the data read block for reading the data recorded in the first-in-first-out 50; Returns the value with the minimum integer ratio of. In other words, if the write clock is fin, the read clock is fout, and each minimum integer value is x and y, the following equation can be obtained.

fin: fout = x: y ........ (1)

Next, the final values X and Y are determined according to the magnitude of the write clock speed and the read clock, considering whether the minimum integer values x and y obtained above are appropriate values that are convenient for circuit control when applying the system. .

X and Y are expressed as follows.

X = Y + N, fin> fout ...... (2)

Y = X + N, fin <fout ...... (3).

In the above, N is an arbitrary integer meaning the clock remaining in the magnitude relationship between the write clock and the read clock.

That is, while the read clock reads Y data for the same time, the write clock means writes X data to the first-in-first-out 50.

In this case, when fin> fout of Equation (2), Y valid data is recorded when data is written to the first-in, first-out, and the write operation is stopped for N dummy clocks. When reading data, if the reading starts one clock later than the writing time point, no other control circuit is needed and the full and empty flags are not generated even if the data is read continuously.

FIG. 3A shows timings of input / output signals of each part of FIG. 2 when the write clock is larger than the read clock as described above.

Here, (a ') is a clear signal, (b') is a write clock WCLK applied to the data recording control unit 10, (c ') is a timing of input data, and (d') is the data. Is the timing of the writable signal WEN generated in the write control section 10, (e ') is the read clock RCLK applied to the data read control section 30, and (f') is the output data path control section. It is the timing of the data output from 40, and (g ') is the timing of the readable signal REN generated in the data reading control part 30.

On the other hand, in the case of fin <fout of Equation (3), if at least X valid data is written to the first-in, first-out, the first-in-first-out (50) data is read and the reading is stopped for N clock minutes. An effective write and read control can be performed without generating the full flag and empty flag of 50).

FIG. 3B shows timings of the input / output signals of each part of FIG. 2 when the write clock is later than the read clock as described above.

Here, (a ") is a clear signal, (b") is a write clock WCLK applied to the data recording control unit 10, (c ") is a timing of input data, and (d") is the data Is the timing of the writable signal WEN generated in the write control section 10, (e ") is the read clock RCLK applied to the data read control section 30, and (f") is the output data path control section. It is the timing of the data output from 40, and (g ") is the timing of the readable signal REN generated in the data reading control part 30.

The operation in the case of applying the data processing speed conversion method of the present invention to the system shown in FIG. 2 is as follows.

First, the data recording control unit 10 generates the recordable signal WEN according to the X and Y values obtained by the equations (1) to (3), and transmits it to the first-in, first-out machine 50. The controller 20 transmits the input data to the first-in, first-out machine 50 by the recordable signal.

Here, the timing of the data input to the first-in, first-out (50) is controlled according to the condition of fin> fout or fin <fout.

In addition, the data read control unit 30 also generates a readable signal REN according to the X and Y values obtained by the above equations (1) to (3), and transmits the readable signal REN to the first-in, first-out-first-out (50). 50) is to perform writing and reading of data smoothly without generating a full flag and an empty flag.

If the data processing rate conversion according to the present invention is applied to a system that actually needs a data processing rate conversion is as follows.

In the case of HDTV, a frame consists of 1125 scan lines of 2200 pixels per scan line, and the number of frames per second is 30 frames.

Thus, the HDTV system speed is 74.25 MHz. However, in order to reduce the burden on the hardware, video signal processing algorithm blocks such as motion compensation / estimation, variable length encoder / decoder, DCT / IDCT, quantizer / dequantizer, etc. Only 1088 scan lines which are effective image data and 33 MHz using only 1920 pixels per scan line are used.

That is, a first-in first-out machine for converting data processing speed is required between the image input / output unit and the signal processor.

In the first-in, first-out case, the write clock is 37.125 MHz, the read clock is 33 MHz, and in the decoder, the write clock is 33 MHz and the read clock is 37.125 MHz.

Therefore, substituting this into Equation (1) to obtain the minimum integer value according to the present invention,

37.125 MHz: 33 MHz = 144: 128.

That is, in the case of the encoder, when writing data to the FIFO, if 128 data of valid data and 16 clocks of dummy data are written, at least one clock after the reading is read, the pool or empty can be read. It does not occur.

In the case of the decoder, there is no occurrence of empty and pool by simply writing 128 clocks of data to the first-in, first-out, then valid data of 128 clocks and stopping reading for 16 clocks.

In this way, circuit control such as a frame memory unit located before or after the data processing rate conversion unit is much simpler than when using the full flag and the empty flag.

As described above, in the present invention, when the data processing speed between the block for writing data and the block for reading data is different, the timing of the write clock is compared by comparing the magnitude relationship between the write clock speed and the read clock speed. By adjusting appropriately, the first-in, first-out of data can be smoothly performed without generating a full flag and an empty flag in the first-in first-out machine.

In addition, since there is no need to design a peripheral circuit for processing the full flag and the empty flag generated in the first-in, first-out, the overall system implementation is simplified.

Claims (5)

A data processing system for recording data in a first-in, first-out, and reading data recorded in the first-in, first-out, Calculating a write and read minimum integer value having a minimum integer ratio between a write clock and a read clock of the first-in, first-out machine that writes and reads data; Calculating a final write control value by adding an appropriate value convenient for circuit control to the system to the calculated write and read minimum integer values; Comparing the data processing speed between the write block for recording data and the read block for reading the recorded data after calculating the write control value and controlling the enable and disable times of the write control value according to the magnitude relationship; Data processing speed conversion method characterized in that it comprises a. The method of claim 1, wherein the minimum integer value is calculated by fin: fout = x: y when fin is a write clock, fout is a read clock, and x and y are the minimum integer values. And calculating the minimum integer value. The final write control value X is calculated by Y + N when the speed of the write clock fin is faster than the speed of the read clock fout. How to convert data speed. Here, Y means a read clock for reading recorded data, and N means a remaining dummy clock remaining after subtracting the read clock Y from the write clock. The final write control value Y is calculated by X + N when the speed of the write clock fin is later than the speed of the read clock fout. How to convert data speed. Here, X denotes a write clock for recording data, and N denotes a remaining dummy clock obtained by subtracting the write clock (X) from a read clock. 2. The method of claim 1, wherein after the data processing speed comparison, the write speed is enabled by a read clock when the write speed is greater than the read speed, and the remaining write time is disabled, and the write clock when the write speed is less than the read speed. A method of converting data processing speed, comprising: disabling recording by the remaining read clock after the recording.

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