JPH11120757A - Fifo register circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale and to make handling easy when the number of bits accumulated in FIFO is desired to know externally by taking an output of a shift register outside of FIFO, and controlling writing and reading in/from FIFO based on the number of data accumulated inside of FIFO obtained from an output of the shift register. SOLUTION: In a status display section 5, data is moved in the status display section 5 with same movement as the data movement in a data accumulation section 4. A control section 3 decides whether data is shifted in FIFO or not considering an output of the status display section 5. A decoder 13 decodes a state in which output Snout-S(n-1)out from each shift register S1-Sn of the status display section 5 of FIFO are decoded and data of (n-1) bits is accumulated in a state being almost filled up, resets a SR-FF18, and outputs a control signal of prohibiting of writing to an input interface section.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a FIFO register circuit used for data communication, and more particularly, to a FIFO register circuit capable of reducing the circuit scale.

[0002]

2. Description of the Related Art Generally, a first-in first-out (FIFO) type buffer in which data is output in the order of input from the moment of input is known. This is called FIFO. The FIFO does not need to be aware of the address externally, and operates only with the write clock and the read clock. These two clocks are completely asynchronous and can control reading and writing from outside at any time. However, since the address does not need to be considered externally, the internal state cannot be grasped by this alone. Therefore, the Full Flag, Empty F
There is a function to display a lag, and it tells the outside whether the FIFO is now full or empty. On the outside, the display is controlled, and control is performed to stop the write clock if Full Flag is set, and Empty Flag is set.
Control is performed such that the read clock is stopped if g rises. This FIFO can be used, for example, as a buffer memory when a clock extracted from a reception transmission line is replaced with an internal clock in the communication device on the receiving side of the communication device. That is, the received data is naturally transmitted by the clock of the device that issued it, and the transmitted clock and the internal clock of the device that received it have different phases. Furthermore, if synchronization is not achieved between the transmitting device and the receiving device, the clock speed will also differ. Therefore, the receiving device extracts a clock from the received data, and recognizes the received data using the extracted clock.

[0003] However, since the receiving device has a clock in the device operating the receiving device, it is necessary to adjust the received data to the phase thereof. So, FIF
Using the fact that O reads and writes are completely asynchronous,
Once the received data is written to the FIFO with the receive clock,
At the time of reading, the received data is read with the clock in the device so that the received data is adjusted to the phase of the clock in the device. Here, if the transmitting device and the receiving device are synchronized even if the clock phases are different, the reading from the receiving FIFO can be started after the data is sufficiently accumulated in the FIFO, so that the received data is erroneous. Can be received normally, but when synchronization is not established, the clock speed itself differs slightly between the transmitting device and the receiving device.
Just storing some data in the FO,
The IFO is full or empty. In such a state, the write and read data cannot be stopped, so that a data error occurs in the FIFO due to overwriting, reading twice, or the like. If this is left as it is, it will not be full frequently, or it will become empty or accumulate data, and the number of data errors will be extremely large.

In order to prevent such a situation, once it is about to be full or empty (leave a margin and set the margin to 1) for a certain bit (m).
There is a control method in which the write or read operation is stopped and the data error for the stop is inevitable, and a sufficient amount of data is stored in the FIFO so that no data error occurs for a while. This is called slip control. .
The information required for the slip control includes information that the FIFO is going to be full (n-1 bits are stored), information that the FIFO is going to be empty (only 1 bit is stored), and full-m bits are stored. Is necessary, and information that m bits are stored. In the case of the conventional FIFO, information indicating that the FIFO is almost full, is likely to be empty, and is full-m bits or m bits cannot be externally known. For this reason, FIF
An up / down counter must be prepared outside O, the number of bits written and the number of bits read must be counted, and the output thereof must be decoded to control writing and reading.

[0005] The above prior art will be described specifically with reference to FIG. Figure 2 shows a FIFO composed of shift registers
5 shows a FIFO register circuit that performs slip control by using. As shown in FIG. 2, the FIFO register circuit includes an input interface unit 1 for flowing input data into the FIFO, an output interface unit 2 for outputting data stored in the FIFO, and an input data unit. And a data storage unit 4 for controlling the flow of data in the FIFO quickly and a data storage unit 4 for storing actual data.
A status display unit 5 for displaying how much data has been stored, an up / down counter unit 6 for counting the number of write clocks and read clocks, and indicating the number of data stored in the FIFO, Decoders 7, 8, 10, 11 for decoding the output of the down counter 6 and SR-FFs (SR flip-flops) 9, 12 for generating a write / read control signal based on the decoder output. In the FIFO register circuit, the FIFO includes an input interface unit 1, an output interface unit 2, a control unit 3, a data storage unit 4, and a status display unit 5, and the external circuits include an up-down counter unit 6, a decoder unit 7, 8, 10, 11 and SR-FF 9, 12. The data storage unit 4 includes a plurality of (in this case, n) shift registers D1 to Dn, and the status display unit 5 also includes n shift registers S1 to Sn.

As an operation of the FIFO register circuit, input data is input to the data storage unit 4 through the input interface unit 1 by a write clock. The data stored in the data storage unit 4 is stored in the control unit 3.
, The data reaches the first shift register of the data storage unit 4 by the clock in the FIFO which is considerably faster than the write / read clock, and the input data is stored in the shift register immediately after the previously input data. Is done. In this way, the input data is stored in the shift register closest to the output side where no data is stored. Further, when a read clock is input, the data is simultaneously shifted by the number of clocks containing the stored data. In the status display unit 5, the status display data moves in the status display unit 5 in the same manner as the data moves in the data storage unit 4. Looking at the output of the status display section 5, the control section 3 determines whether or not the data shifts in the FIFO.

[0007] In the conventional FIFO register shown in FIG. 2, an FIFO including shift registers D 1 to Dn is used.
Since O does not output the internal state to the outside, the up-down counter unit 6 must be set to the outside when slip control is performed (the FIFO constituted by the shift register is full. No Flag or Empty Flag). The outputs of the up / down counter section 6 are decoded by decoders 7 and 8 to indicate that the state is full-m bits and full-1 bit, respectively, and the SR-FF 9 writes based on the decoding result. Is generated. That is, if the FIFO is almost full (n-1 bits are accumulated), the decoder 8 decodes the data and the SR-FF 9
Is reset, and a write-inhibit control signal is output to the input interface unit 1. Since reading is being performed while writing is prohibited, the output of the up / down counter unit 6 decreases to nm. At that time, the decoder 7
, The SR-FF 9 is set, and a write enable control signal is output to the input interface unit 1. Similarly, the decoders 10, 11, SR-FF12
If the number of bits stored in the FIFO is 1 bit, a read-inhibit control signal is output to the output interface unit 2, and if m-bit data is accumulated, a read-enable control signal is output. Thus, the conventional FIF
In O, the up-down counter section 6 had to be prepared and controlled to perform the slip control.

[0008]

However, in the above-mentioned conventional FIFO register circuit, the provision of the up / down counter section 6 on the outside increases the circuit scale on the outside and requires control of the circuit. However, there was a drawback that it became complicated. The present invention has been made in order to eliminate the disadvantages of the conventional FIFO as described above, and to reduce the circuit scale which must be provided externally when the number of bits stored in the FIFO is known externally. It is an object of the present invention to provide a FIFO register circuit which can be easily performed.

[0009]

In order to achieve the above object, the present invention provides a FIFO register circuit having a first-in first-out type buffer (FIFO) for performing slip control, wherein the FIFO comprises a plurality of shift registers. Means for extracting the output of each shift register to the outside of the FIFO in order to obtain the number of data stored inside the FIFO, and the means stored in the FIFO obtained from the output of each shift register. Control means for controlling writing and reading to and from the FIFO based on the number of data. Another feature of the present invention is that the FIFO has a data storage unit composed of a plurality of shift registers, and a status display unit composed of a plurality of shift registers.
The output of each shift register of the status display section is drawn to the outside. According to another feature of the present invention, the control means obtains the number of data stored in the FIFO from the output of each shift register of the status display unit, and the first value at which the number of stored data is likely to become full of the FIFO. Is set, the writing to the FIFO is prohibited, and the reading from the FIFO is prohibited when the number of stored data becomes the second value that is likely to empty the FIFO. That is.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on illustrated embodiments. FIG. 1 is a circuit diagram showing one embodiment of a FIFO register circuit according to the present invention. As shown in FIG. 1, this FIFO register circuit stores
An input interface unit 1 for flowing into the FO;
An output interface unit 2 for outputting data stored in the FO;
The control unit 3 controls the flow of the data quickly, the data storage unit 4 stores the actual data, the status display unit 5 displays how much data is stored, and the FIFO of the capacity n is almost full ( a decoder 13 for decoding a state that has been stored (n-1 bits), a decoder 14 for decoding a state where there is some allowance before the FIFO is filled (n-m bits are stored), and the decoders 13 and 14 An SR-FF 15 for controlling the validity / invalidity of the write clock in response to the decoding result from
A decoder 16 for decoding a state where the FO is almost empty (the remaining one bit), a decoder 17 for decoding a state where data is stored to some extent in the FIFO (m bits are stored), and An SR-FF 18 for controlling the validity / invalidity of the read clock in response to the decoding result. The data storage unit 4 includes a plurality (n in this case) of shift registers D1.
To Dn, and the status display section 5 also includes n shift registers S1 to Sn.

Next, the operation of the FIFO register circuit will be described. First, the input data is passed through the input interface unit 1 by the write clock to the data storage unit 4.
Is input to Then, the data input to the data storage unit 4 reaches the first shift register of the data storage unit 4 by the clock in the FIFO which is considerably faster than the write / read clock while being controlled by the control unit 3, and the input data is The data is stored in the shift register immediately after the previously input data. In this way, the input data is stored in the shift register closest to the output side where no data is stored. Further, when a read clock is input, the data is simultaneously shifted by the number of clocks containing the stored data. In the status display unit 5, the status display data is displayed in the same manner as the data moves in the data storage unit 4.
It is a mechanism that moves inside. Looking at the output of the status display section 5, the control section 3 determines whether or not the data shifts in the FIFO. The decoder 13 outputs the outputs Snout to S (n-1) from the shift registers S1 to Sn of the status display unit 5 of the FIFO.
out is decoded and the FIFO is almost full (n-
The stored state is decoded, and the SR-FF 18 is reset according to the decoding result, and a write-inhibit control signal is output to the input interface unit 1.

Since reading is performed while writing is prohibited, the number of bits stored in the FIFO decreases to nm, and at that time, the signals Snout to Snout from the status display unit 5 are output. A signal is output from the decoder 14 that decodes S (nm) out and S
The R-FF 15 is set and the input interface unit 1
, A write enable control signal is output. Similarly, the decoders 16, 17 and SR-FF 18 perform FIFO
If the number of accumulated bits is 1 bit, a read-inhibit control signal is output to the output interface unit 2,
When the m-bit data is accumulated, a read permission control signal is output. That is, the decoder 16 decodes the outputs S1out to Sout from the shift registers S1 to S1 of the status display unit 5, and
The state where the number of stored bits of O is 1 bit is decoded,
The SR-FF 18 is reset according to the decoding result, and a read-inhibit control signal is output to the output interface unit 2.

Since writing is performed while reading is prohibited, the number of bits stored in the FIFO increases to m bits. At this time, the signals S1out to Smout from the status display unit 5 are output. A signal is output from the decoder 17 that decodes
The R-FF 18 is set, and a read permission control signal is output to the output interface unit 2. By outputting the output of each shift register of the status display unit 5 from the FIFO to the outside in this manner, an up-down counter unit is not required as compared with the conventional case, thereby making it possible to reduce the circuit scale and control it. Troublesomeness can be eliminated. Therefore, the slip control can be more simply realized. Although the present invention has been described with reference to an example in which the present invention is applied to slip control, the present invention is not limited to this, and can be applied to all circuits using a FIFO register.

[0014]

As described above, according to the present invention, the number of data stored therein is extracted to the outside from the FIFO constituted by the shift register, thereby making the up-down counter unit different from the conventional case. No longer needed
This can reduce the circuit scale. Further, the trouble of controlling the up / down counter section can be eliminated, and the slip control can be more simply realized. Therefore, a remarkable effect is exhibited in reducing the circuit scale in the peripheral portion of the FIFO and simplifying the design.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a FIFO register circuit embodying the present invention.

FIG. 2 is a circuit diagram of a FIFO register circuit in which slip control is realized by a FIFO configured by a conventional shift register.

[Explanation of symbols]

1 input interface unit 2 output interface unit 3 control unit
4 Data storage unit 5 Status display unit
6, up-down counter, 7,
8, 10, 11, 13, 14, 16, 17 ... decoder,
9, 12, 15, 18 ... SR flip-flop (SR-
FF),

Claims (3)

[Claims] An FIFO having a first-in first-out type buffer (FIFO) for performing slip control
A register circuit, wherein the FIFO is constituted by a plurality of shift registers, and means for extracting an output of each shift register to the outside of the FIFO to obtain the number of data stored in the FIFO; Control means for controlling writing to and reading from the FIFO based on the number of data stored in the FIFO obtained from the output of the shift register.
FO register circuit. 2. The apparatus according to claim 1, wherein the FIFO includes a data storage unit including a plurality of shift registers, and a status display unit including a plurality of shift registers, and the extracting unit outputs an output of each shift register of the status display unit. 2. The apparatus according to claim 1, wherein the apparatus is configured to be drawn out to the outside.
3. The FIFO register circuit according to 1. 3. The control means obtains the number of data stored in the FIFO from the output of each shift register of the status display unit, and the number of stored data becomes a first value that is likely to fill the FIFO. In this case, control is performed to prohibit writing to the FIFO and to prohibit reading from the FIFO when the number of stored data becomes a second value that is likely to cause the FIFO to become empty. 3. The FIFO register circuit according to claim 2, wherein: