JP2983372B2 - Image reproducing apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a recording medium such as an optical disk.
Reads the compressed image data recorded on the body and gives it to the display device.
The present invention relates to an image reproducing apparatus and a method suitable for obtaining an image.

[0002]

2. Description of the Related Art Recent optical recording media such as an optical disc called a CD-ROM can store an enormous amount of data and are therefore used for many purposes.
In particular, image data has a very large data amount, so CD-
The features of the ROM can be fully exhibited.

[0003] Moving image data is compressed and recorded on a CD-ROM or the like.
As a technique for reproducing, there is an MPEG method. This predicts and reproduces frames in the forward and backward directions by intra-frame coding, inter-frame coding, and motion compensation using a motion vector. The MPEG system increases the efficiency of compression, but requires an arithmetic circuit and an image memory in the decoding unit, and increases the hardware scale.

As a technique for compressing and reproducing still images,
There is a JPEG system using intra-frame coding. JPE
Even in the G method, a moving image can be reproduced in a pseudo manner by continuously decoding still image data. In other words, assuming a fixed frame rate at the time of decoding and reading out data for one frame, and if the amount of information is limited so that the decoding time is equal to or less than the frame rate, a moving image can be displayed at that frame rate. However, the amount of information may be small depending on the type and size of the image.
Such a fixed frame rate is not desirable because it is better to increase the rate, and a high-quality image may be required even if the frame rate is reduced.

[0005]

Therefore, when a moving picture is intra-coded at an arbitrary frame rate that can be decoded according to the amount of information, at the time of decoding, the period in which the frames are thinned out is detected and the image data is decoded. A way to display at the original frame rate is needed.

When the time from reading from the CD-ROM to decoding is delayed for some reason, it is necessary to take a solution for continuing the display on the display device without interruption.

[0007]

According to an image reproducing apparatus of the present invention, data representing a frame number is stored in each frame.
An image data generator for outputting image data recorded in a header in frame units together with its frame number, and generating an output end signal when the output of one frame of image data is completed. First and second image memories for alternately storing output image data for one frame each, a display device for displaying an image represented by image data alternately read from the first and second image memories, And controlling writing of image data output from the image data generating device to the first or second image memory and reading of image data to be displayed on the display device from the first or second image memory. It is composed of a control device.

The control device includes a first operation mode in which image data is written to the first image memory and image data is read from the second image memory, and image data is read from the second image memory. A second operation mode in which only image data is read from the first image memory, and a third operation mode in which image data is written in the second image memory; and image data from the first image memory. Has a fourth operation mode in which only reading is performed.

The writing of the image data to one of the first and second image memories is completed, and the number of frame synchronization signals appearing after the completion of the writing is determined by the other image memory from which the reading is performed. When the condition that the value added to the frame number of the image data is equal to or larger than the frame number of the image data written to the one image memory is satisfied, the first or second operation mode is switched to the second operation mode. the third operation mode, or from the third or fourth operation mode to transition to the first mode of operation
Has become .

The above-mentioned image data generating device and display device are not necessarily essential for the image reproducing device according to the present invention.

The most essential part of the image reproducing apparatus according to the present invention is that the image data given together with the frame number is alternately written in frame units, and the image data is alternately read out for display. And the second
And the control device for controlling the writing of the image data to the first or second image memory and the reading of the image data from the first or second image memory. be able to.

The control device further comprises a first and a second
When the writing of the image data to one of the image memories is completed and the above condition is not satisfied, the first operation mode is switched to the second operation mode, or the third operation mode is switched to the fourth operation mode. transitions to mode, the the condition is the third from the second operation mode when filled operation mode, or from the fourth operation mode so as to perform an operation that a transition to the first mode of operation I have .

In one embodiment of the present invention, the control device corresponds to the first and second image memories, respectively, and stores a frame number of image data written in the corresponding image memory. The frame numbers of the first and second storage means to be stored and the storage means selected from the first and second storage means are loaded, and the loaded frame numbers are input for each frame synchronization signal. Counter means for decrementing, comparing means for comparing the count value of the counter means with the selected frame number stored in the memory, and the result of comparison by the comparing means;
When the count value is equal to or larger than the frame number, the first or second operation mode is switched to the third mode on the condition that the write end signal has already been output.
Operation mode to, or means for generating a transition from the third or fourth operation mode to the first mode of operation, the newly selected selecting means storing means corresponding to the operation mode after the transition, as well as new Means for loading the frame number of the storage means selected before the selection into the counter means.

[0014] In another embodiment of the invention, the
The first and second storage means are newly stored by the selection means.
The storage means selected for the new image data
Until the frame number associated with the data is stored.
It consists of a register that stores the maximum value that can be stored .

In still another embodiment of the present invention, a first timing for incrementing the counter means and a second timing for operating the comparing means during a period in which the frame synchronization signal is supplied. Timing control means for generating, in this order, a third timing for loading the timing and the frame number of the storage means into the counter means, and a fourth timing for transition of the operation mode and new selection of the storage means. Is provided.

In a preferred embodiment of the present invention,
The control device has a clear operation mode in which a reset signal is supplied in the first to fourth operation modes and, in response, data representing a constant value is written to at least one of the first and second image memories.

According to the image reproducing method of the present invention, the image data given together with the frame number for each frame is alternately written to the first and second image memories, and the first and second image memories are written. A first operation mode in which image data is written to the first image memory and image data is read from the second image memory in order to alternately read image data for display from the second image memory; A second operation mode in which only image data is read from the image memory, a third operation mode in which image data is selected from the first image memory and image data is written in the second image memory, and A fourth operation mode in which only image data is read from the first image memory is set, and writing of the image data to one of the first and second image memories is completed. The value obtained by adding the number of frame synchronizing signals appearing after the end of the writing to the frame number of the image data in the other image memory being read is the frame of the image data written in the one image memory. When the condition that the number is equal to or greater than the number is satisfied, a transition is made from the first or second operation mode to the third operation mode, or from the third or fourth operation mode to the first operation mode. .

[0018]

The writing of the image data to one of the first and second image memories is completed, and the number of frame synchronization signals appearing after the completion of the writing is determined by the image of the other image memory being read. When the condition that the value added to the frame number of the data is equal to or larger than the frame number of the image data written in the one image memory is satisfied, the first operation mode is changed to the third operation mode. , Or from the third operation mode to the first operation mode.

Further, when the writing of the image data into one of the first and second image memories is completed and the above condition is not satisfied, the operation mode is changed from the first operation mode to the second operation mode, or Transition from the third operation mode to the fourth operation mode, and when the above condition is satisfied, from the second operation mode to the third operation mode, or from the fourth operation mode to the first operation mode. Transition.

[0020]

FIG. 1 shows the overall configuration of an image reproducing apparatus.

An optical recording medium such as a CD-ROM has an arbitrary frame format capable of decoding moving image digital image data.
Data is compressed at a rate by a technique such as DCT (Discrete Cosine Transform), coding, or the like, and recorded in frame units. Further, as the additional information, the frame number.
(Number) and data representing the image type are recorded as a header for each frame.

The reading device 11 includes an optical head and reads compressed image data for each frame from an optical recording medium.
The compressed image data is stored in the buffer memory 12.

The expansion circuit 13 decodes the compressed image data temporarily stored in the buffer memory 12, expands the data by a method such as inverse DCT, and outputs the image data in frame units.

The image reproducing apparatus has two frame memories M
1 and M2. One frame of image data expanded by the expansion circuit 13 is supplied to the gate circuit 21 or 2.
3 and are alternately applied to and stored in the frame memory M1 or M2.

The image data for one frame stored in the frame memories M1 and M2 is alternately read out via the gate circuit 22 or 24 and applied to the display device 17.

Writing of image data in the frame memories M1 and M2 is controlled by memory write signals M1W and M2W, respectively, and reading of image data is controlled by memory read signals M1R and M2R, respectively.

These memory write signals M1W, M2
W and the memory read signals M1R and M2R are generated in the memory control circuit 16. The memory control circuit 16 is also supplied with image data output from the expansion circuit 13 and various timing signals generated in the timing generation circuit 15. The timing generating circuit 15 outputs a frame synchronizing signal * F (inverted signal is indicated by * instead of a bar) given from the synchronizing signal generating circuit 14,
A timing signal to be provided to the memory control circuit 16 is generated based on the horizontal synchronization signal * HS and various signals input from the expansion circuit 13. Details of these circuits 15 and 16 will be described later.

FIG. 2 shows the format of the image data output from the expansion circuit 13.

At the beginning of one frame of image data, a frame number is assigned. And data on the image type.
Frame NO. Is generally assigned a serial number. However, a frame number may be recorded on an optical recording medium such as a CD-ROM by thinning out several frames. May have missing numbers. The image type data indicates a moving image or a still image. In this embodiment, only moving images are handled.

Generally, image data for one frame is output during one frame period (1/30 second). However, if the expansion process in the expansion circuit 13 takes a long time, it may take two or more frame periods (2/30 seconds) to output one frame of image data.

Further, the image data is output from the decompression circuit 13 continuously in each frame period in principle. As shown by hatching in FIG. 2, the image data is output over one frame period or more. It may not be output. This is due to, for example, a temporary interruption of the reading process in the reading device 11.

FIG. 3 shows the image data (data on the data bus) output from the expansion circuit 13 and the frame number. Enable signal * FNE, image type enable signal * T
The YPE and the data enable signal * DATAE are shown.

The expansion circuit 13 is supplied with the system clock signal CK, the frame synchronization signal * F and the horizontal synchronization signal * HS output from the synchronization signal generation circuit 14. The decompression circuit 13 outputs a frame N on a data bus (for example, 8 bits) in synchronization with the system clock signal CK.
O. Outputs data, image type data and image data. Frame NO. The data is composed of three bytes and is output over three clock cycles. The image type data is composed of one byte. This image type data is followed by image data.

Frame No. The enable signal * FNE is the frame number. It becomes L level when data is being output. The image type enable signal * TYPE goes low when image type data is being output. The data enable signal * DATAE goes low when image data is being output. These various enable signals * FNE, * TYPE and * DATA
E is supplied to the timing generation circuit 15.

The expansion circuit 13 further generates an end signal Wend indicating that the output of the image data for one frame is completed, and this signal Wend is given to the timing generation circuit 15.

The write / read control of the memories M1 , M2 by the memory control circuit 16 will be described with reference to FIGS.

FIG. 5 shows an outline of the configuration of the memory control circuit 16 (a more detailed configuration including timing control and the like will be described later).

The memory control circuit 16 has two registers RE.
G1 and REG2. These registers REG
1 and REG2 are frame numbers of the image data supplied from the expansion circuit 13. Data is stored alternately. One of the registers REG1 and REG2 is selected by the selector SE, and the frame No. stored in the selected register is selected. Is the load enable signal * L
It is loaded into the frame counter CN when OADE is given. When the counter clock signal TCLK is supplied, the frame counter CN adds one to the previously loaded value.

The comparison circuit 30 stores the count value (CN) of the counter CN and the frame number stored in the register (register REG1 or REG2) selected by the selector SE. (REG) and (CN) ≧
An output is generated at the time of (REG).

The sequencer 31 has a sequencer clock signal SCLK described in detail after synchronizing with the output of the comparison circuit 30 and the frame synchronization signal * F, and the end signal We described above.
nd (same as the end signal WE given from the timing generation circuit 15), and based on these input signals, the memory write signals M1W, M2W, and the memory read signals according to the transition conditions shown in FIG. M1R,
Output M2R.

FIG. 6 shows the operation of the memory control circuit 16 shown in FIG. In this figure, the width of the L level of the frame synchronization signal * F is exaggerated. The frame synchronization signal * F shown in FIGS. 4 and 6 is equivalent to the sequencer clock signal SCLK given to the sequencer 31 in the operation of the sequencer 31, and is easily understood in FIGS. 4 and 6. For this reason, the frame synchronization signal * F is shown instead of the clock signal SCLK.

A to I shown in FIG. 6 are frame numbers of image data. Alternatively, it represents the count value of the counter CN. A to I are operation numbers incremented by one.
+ 1 = B, B + 1 = C, C + 1 = D, D + 1 = E, E +
1 = F, F + 1 = G, G + 1 = H, H + 1 = 1.

The basic purpose of the write / read control of the memories M1 and M2 in the memory control circuit 16 is as follows.

As shown in FIG. 6, first, in the first frame period, the frame No. B is output, and then, in the second frame period, the frame No. D is output, the image data is not output in the third frame period, and the frame number is output in the fourth frame period. F is output, and the fifth image data is output.
No image data is output in the frame period of the frame No., and in the sixth frame period, the frame No. G is output, and the frame No. G is output over two frame periods of the seventh and eighth frame periods. It is assumed that I image data is output.

The frame number of the image data output from the expansion circuit 13 Are discontinuous, such as B, C, D, E, F, G, H, and have missing numbers. When there is a missing number, there is a period during which the image data is not output for a period corresponding to the missing number, such as the third and fifth frame periods (image data having a frame number next to the missing number frame is transmitted first. Will be). Further, one frame of image data may be output over two frame periods, such as the seventh and eighth frame periods.

Even in such a case, the image data is always read out from one of the memories M1 and M2 in every frame period, and the display device 17 continuously outputs the frame number. Are written to the memories M1 and M2 and the written image data is read from the memories M1 and M2 so that the images are displayed in the order of.

In order to perform such memory read / write control, the sequencer 31 transitions between state 1 to state 4 under the transition conditions shown in FIG.

In state 1, the sequencer 31 writes the image data output from the expansion circuit 13 into the memory M1 (writes the memory M1: outputs the memory write signal M1W), and reads out the image data stored in the memory M2 ( Read memory M2: Output memory read signal M2R).

In contrast, in state 3, the sequencer 31 writes the image data output from the decompression circuit 13 into the memory M2 (writes the memory M2: outputs the memory write signal M2W) and stores the image data in the memory M1. Read image data (read memory M1: output memory read signal M1R).

In state 2, the sequencer 31 performs only reading of image data from the memory M2 (reading the memory M2: outputting a memory read signal M2R). Writing to the memory M1 is not performed.

In state 4, the sequencer 31 performs only reading of the image data from the memory M1 (reading the memory M1: outputting the memory read signal M1R). Writing of image data to the memory M2 is not performed.

When writing the image data output from the expansion circuit 13 into the memory M1, the frame number of the image data is stored in the memory M1. Are stored in the register REG1. Extension circuit 13
When writing the image data output from the memory M2 into the frame M. Is the register REG2
Is stored.

When the state of the sequencer 31 transitions to the state 1 or the state 3, the frame number stored in the register REG1 or REG2 immediately before the transition. Is loaded into the counter CN.

The counter CN is incremented for each frame synchronization signal * F.

During the period when the frame synchronization signal * F is at the L level, the counter CN is incremented, the comparison result is fetched by the comparison circuit 30, transition between states, and the frame number of the register REG1 or REG2 is changed. The data is loaded into the counter CN in this order.

In the transition from the state 1 to the state 3, the end signal Wend is applied and the frame synchronization signal * F
Is at the L level (when the sequencer clock signal SCLK is supplied) and the output of the comparison circuit 30 is (C
N) ≧ (REG1) (counter CN
Is stored in the register REG1. Greater than or equal to).

In state 1, the end signal Wend is given, but when other conditions are not satisfied, the operation first moves to state 2, and then (CN) ≧ (CN) while the frame synchronization signal * F is at the L level. When REG1) is satisfied, transition is made from state 2 to state 3.

In the state 1, the end signal We is output.
When nd is not given (for example, when image data of frame No. 1 is written over two frame periods), the state does not transition to state 3 even if frame synchronization signal * F is at L level.

The transition from the state 3 to the state 1 is provided with the end signal Wend and the frame synchronization signal * F.
Is at the L level (when the sequencer clock signal SCLK is supplied) and the output of the comparison circuit 30 is (C
N) ≧ (REG2) (counter CN
Is stored in the register REG2. Greater than or equal to).

In the state 3, the end signal Wend is given, but when other conditions are not satisfied, the process first proceeds to the state 4, and then, when the frame synchronization signal * F is at the L level, (CN) ≧ ( When REG2) is satisfied, transition is made from state 4 to state 1.

In state 3, the end signal We is output.
When nd is not given, the state does not transition to state 1 even if the frame synchronization signal * F is at the L level.

The above operation can be easily understood from FIGS.

FIG. 7 shows the operation of the timing generation circuit 15. The timing generation circuit 15 is composed of a combination of a frequency dividing circuit, a logic circuit and the like, and is supplied from the system clock signal CK, the frame synchronization signal * F and the horizontal synchronization signal * HS supplied from the synchronization signal generation circuit 14, and from the expansion circuit 13. Various signals * FNE, * TYPE,
* Various signals for controlling the memory control circuit 16 are generated based on DATAE and Wend.

The counter clock signal TCLK, the sequencer clock signal SCLK, and the sequencer output latch clock signal LCLK are synchronized with the horizontal synchronization signal * HS in the above-described order during the period when the frame synchronization signal * F is at the L level. Occur. The counter load enable signal * LOADE is the sequencer clock signal SC
It is at the L level from the fall of LK to the point in time beyond the output point of the latch clock signal LCLK.

The timing generation circuit 15 further includes a memory write signal M1W supplied from the memory control circuit 16.
Alternatively, a data request signal RQ is generated at the time of rising of either of M2W. Data request signal R
Q is the OR of the memory write signals M1W and M2W.
The data request signal RQ is provided to the decompression circuit 13 as a request for outputting the next one frame of image data. The data request signal RQ is reset by an end signal Wend provided from the expansion circuit 13.

The end signal WE is the same as the end signal Wend. The timing generation circuit 15 also includes the extension circuit 13
From the frame No. Enable signal * FNE
To the memory control circuit 16.

FIG. 8 shows a specific circuit configuration of the memory control circuit 16, which is substantially the same as the circuit shown in FIG. Therefore, in FIG. 8, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted.

The operation timing in FIG. 8 will be described with reference to various timing signals shown in FIG.

When the counter clock signal TCLK is applied, the count value of the counter CN is incremented. The count value of the counter CN and the frame number output from the selector SE are output. The comparison result in the comparison circuit 30 is read into the sequencer 31 at the timing of the sequencer clock signal SCLK. The sequencer clock signal SCLK is synchronized with the frame synchronization signal * F.
Therefore, at this time, the sequencer 31
The transition condition shown in FIG. 4 can be determined based on the comparison result of 0 and the presence / absence of the end signal WE (Wend).

As a result of this determination, the memory control signals M1W, M2W, M1R and M2R output from the sequencer 31 are latched by the latch circuit 32 at the time of the latch clock signal LCLK.
And output to the outside.

The frame No. given to the counter CN through the selector SE. (Register REG1 or R
(Stored in EG2) is loaded into the counter CN immediately after the above-described comparison operation by the fall of the load enable signal * LOADE .

Registers REG1 and REG2 are enabled when memory write signals M1W and M2W are at H level, respectively.

When memory write signal M1W or M2W rises (latch clock signal LCL
K), flip-flop 33
Or 34 is set, and the output Q is set in the register REG.
1 or REG2. When the register REG1 or REG2 is enabled by the memory write signal M1W or M2W, the register REG1 or REG2 operates to set the stored content to the maximum value (all 1s) when an input is given to the set terminal (M value set). ).

Thereafter, the frame No. Enable signal *
The flip-flops 33 and 34 are forcibly reset by the fall of FNE. Register R enabled by memory write signal M1W or M2W
EG1 or REG2 is the frame number supplied from the expansion circuit 13 at that time. Data is fetched and stored at the timing of the system clock signal CK.

Frame No. Enable signal * FNE and frame NO. If no data is given, the maximum value M remains set in the register REG1 or REG2. Decompression circuit 1 for some reason (eg, reading device 11 interrupts reading data from optical disc)
3, when the image data is not output, the transition condition (CN) described above is determined by the maximum value M set in the register.
≧ (REG) is not satisfied, and no failure occurs in the sequence in the sequencer 31 .

The selector SE receives the latch clock signal LC
The registers REG1 and REG2 are switched at the timing of LK. That is, the falling timing of the latch clock signal LCLK is detected by the NOT circuit 36, and the state of the memory read signal M1R at this time is stored in the flip-flop 35. When the output Q of the flip-flop 35 is at H level, the register REG1 is selected by the selector 35, and when the output Q is at L level, the register REG2 is selected by the selector 35.

Next, the operation to which the memory clear processing is added will be described.

FIG. 9 shows the transition condition between the states when the memory clear processing is added to the transition condition between the states shown in FIG.

The memory clear process is a process of writing (writing) a constant value (for example, all 0s) to the memory M1 and reading (reading) data from the memory M2 when a reset command is given. In response to a reset input from a reset input button, power-on, or the like, a CPU that controls the overall operation of the image reproducing apparatus gives a reset command to the sequencer 31.

States 5 to 7 are added.

In the state 5, the sequencer 31 inserts data 0 into the memory M1 (memory M1 write: outputs a memory write signal M1W), and image data (frame NO.Z data) stored in the memory M2. (Read memory M2: output memory read signal M2R).

In state 6, the sequencer 31 reads data (all 0s in this case) stored in the memory M1 (read memory M1: outputs a memory read signal M1R) and outputs the image supplied from the expansion circuit 13. Data (data of frame No. A) is written into the memory M2 (memory M2 write: outputs a memory write signal M2W).

In state 7, the sequencer 31 stores the data stored in the memory M1 (in this case, all 0s).
(Memory M1 read: memory read signal M1R is output). State 7 is not always necessary and can be omitted.

When a reset command is given, the sequencer 31 always moves to state 5 in any of the states 1 to 4, 5, and 7.

FIG. 10 is a time chart corresponding to FIG. 7. Operations of states 5 to 7 will be described with reference to FIG.

The sequencer 31 executes the processing of the state 5, that is, the clear processing of the memory M1. When the clear processing is completed, the sequencer 31 generates the clear end signal Clend, raises the memory write signal M2W, and shifts from the state 5 to the state 6. Transition. A data request signal RQ is generated from the timing generation circuit 15 at the rise of the memory write signal M2W, and is supplied to the expansion circuit 13.
As a result, the image data (frame N
O. A) is output. In state 6, this image data is written to the memory M2.

When the writing of the image data into the memory M2 is completed in the state 6, the decompression circuit 13 sends the end We
Since nd (WE) is given, the sequencer 31 transitions from state 6 to state 7.

In state 7, when one frame period elapses, sequencer 31 sets memory write signal M1W
And proceeds to state 1. Memory write signal M1
Since the data request signal RQ is generated from the timing generation circuit 15 by W and given to the expansion circuit 13,
Image data (data of frame No. B) is output from the expansion circuit 13. This image data is written into the memory M1. In state 1, the image data (data of frame No. A) stored in the memory M2 is read out and displayed on the display device 17.

An end signal Wend is output and A + 1
Since ≧ B is satisfied, a transition is made from state 1 to state 3. When the memory write signal M2W rises, the data request signal RQ is supplied from the timing generation circuit 15 to the expansion circuit 13.

However, the expansion circuit 1
Assuming that no image data is output from field No. 3, field NO. Neither the enable signal * FNE nor the data enable signal * DATAE is output. Register REG2
Is kept in a state where the maximum value M is set. Since the end signal Wend is not output and (CN) ≧ (REG2) is not satisfied, input of image data is awaited in the state 3. This means that the maximum value is set in the register REG1 or REG2.

When the image data (data of frame No. C) is output from the decompression circuit 13, the image data is written into the memory M2. It goes without saying that in state 3, the image data in the memory M1 is read out and displayed over the entire period.

[0092]

As described above, according to the present invention,
The first and second image memories are always in one of the first to fourth operation modes, and given image data is alternately stored in one of the first and second image memories based on the frame number. The image data is always read from one of the other image memories, the image is displayed on the display device at the frame rate at the time of encoding, and the image data is decoded due to a data read error or the like. Even if it is late, the image data is always displayed on the display device, and the image display is not interrupted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an image reproducing apparatus.

FIG. 2 shows a format of image data.

FIG. 3 shows image data and signals accompanying the image data.

FIG. 4 is an operation state transition diagram.

FIG. 5 is a block diagram illustrating a configuration example of a memory control circuit.

FIG. 6 is a timing chart showing the operation of the memory control circuit.

FIG. 7 is a timing chart showing the operation of the timing generation circuit;
It is a chart.

FIG. 8 is a block diagram illustrating a specific example of a memory control circuit.

FIG. 9 is an operation state transition diagram including a clear operation.

FIG. 10 is a timing chart corresponding to FIG. 6 including a clear operation.

[Explanation of Signs] 13 Decompression circuit 15 Timing generation circuit 16 Memory control circuit 17 Display device 30 Comparison circuit 31 Sequencer 32 Latch circuit 33, 34, 35 Flip-flop M1, M2 Image memory REG1, REG2 Register SE Selector CN Counter

Claims (9)

(57) [Claims] 1. An image data in which data representing a frame number is recorded in a header for each frame is output together with the frame number in frame units, and an output end signal is output when the output of one frame of image data is completed. The generated image data generator, first and second image memories for alternately storing the image data output from the image data generator for one frame at a time, and read alternately from the first and second image memories. A display device for displaying an image represented by the image data, and writing the image data output from the image data generation device to the first or second image memory and the image data to be displayed on the display device. A control device for controlling reading from the first or second image memory; A first operation mode in which is written into the first image memory and image data is read out from the second image memory, a second operation mode in which only image data is read out from the second image memory, A third operation mode in which image data is read from the first image memory and image data is written in the second image memory, and a fourth operation mode in which only image data is read from the first image memory The writing of image data to one of the first and second image memories is completed, and the number of frame synchronization signals appearing after the end of the writing is determined by the image of the other image memory being read. When the value added to the frame number of the data is equal to or larger than the frame number of the image data written in the one image memory, the first or second operation mode is set. An image reproducing apparatus, characterized in that the transition from the three modes of operation or the third or fourth operation mode, the first mode of operation. 2. The image data in which data representing a frame number is recorded in a header for each frame is given and written alternately with the frame number in frame units, and the image data is alternately read out for display. First and second image memories, and a control device for controlling writing of the image data to the first or second image memory and reading of the image data from the first or second image memory A first operation mode in which the control device writes image data into the first image memory and reads image data from the second image memory; A second operation mode in which only reading is performed, in which image data is read from the first image memory and image data is written in the second image memory A third operation mode, and a fourth operation mode in which only image data is read from the first image memory. Writing of image data to either one of the first and second image memories is performed. The value obtained by adding the number of frame synchronizing signals appearing after the end of the writing to the frame number of the image data in the other image memory being read is written into the one image memory.
When being equal to or greater to the frame number of the image data, it makes a transition to the third operation mode from the first or second operation mode or from the third or fourth operation mode, the first mode of operation An image reproducing apparatus characterized by the above-mentioned. 3. The first and second storages corresponding to the first and second image memories, respectively, and storing the frame numbers of the image data written in the corresponding image memories. Means, a frame number of a storage means selected from the first and second storage means is loaded, a counter means for incrementing the loaded frame number for each frame synchronization signal, and a count value of the counter means Comparing means for comparing the selected frame number with the selected frame number stored in the storage means. As a result of comparison by the comparing means, when the count value is equal to or greater than the frame number, a write end signal has already been output. Provided that the first or second
Means for causing a transition from the first operation mode to the third operation mode or from the third or fourth operation mode to the first operation mode, and storage means corresponding to the operation mode after the transition are newly selected. 3. The image reproducing apparatus according to claim 1, further comprising a selecting unit for performing the selection, and a unit for loading the frame number of the storage unit selected before the new selection into the counter unit. 4. The storage device according to claim 1, wherein the storage means newly selected by the selection means stores the frame number associated with the new image data from the selection time to the storage time. 4. The image reproducing apparatus according to claim 3, comprising a register for storing a maximum possible value. 5. A counter for incrementing said counter means during a period in which a frame synchronization signal is supplied.
Timing, a second timing for operating the comparison means, a third timing for loading the frame number of the storage means into the counter means, and a transition of the operation mode and a new selection of the storage means. 4. The apparatus according to claim 3, further comprising timing control means for generating the fourth timing in this order.
An image reproducing device according to claim 1. 6. The control device according to claim 1, wherein a reset signal is applied in the first to fourth operation modes, and in response to the reset signal, a data representing a constant value is written in at least one of the first and second image memories. 3. The image reproducing apparatus according to claim 1, wherein the image reproducing apparatus has an operation mode. 7. An image data in which data representing a frame number is recorded in a header for each frame, is given together with the frame number in frame units, and is written alternately in first and second image memories. And a first operation mode for writing image data to the first image memory and reading image data from the second image memory to alternately read image data for display from the second image memory A second operation mode in which only image data is read out from the second image memory, a third operation mode in which image data is selected from the first image memory and image data is written into the second image memory An operation mode and a fourth operation mode in which only the image data is read from the first image memory are set, and the data is transferred to one of the first and second image memories. The value obtained by adding the number of frame synchronization signals appearing after the completion of the writing of the image data and after the completion of the writing to the frame number of the image data of the other image memory being read is written to the one image memory. When the condition that the frame number is equal to or larger than the frame number of the embedded image data is satisfied, the first or second operation mode changes to the third operation mode, or the third or fourth operation mode changes to the first operation mode. An image reproducing method characterized by transitioning to a mode. 8. When the writing of image data to one of the first and second image memories is completed and the above condition is not satisfied, the operation mode is changed from the first operation mode to the second operation mode, or Transition from the third operation mode to the fourth operation mode, and when the above condition is satisfied, from the second operation mode to the third operation mode, or from the fourth operation mode to the first operation mode. 8. The image reproducing method according to claim 7, wherein a transition is made. 9. A clear operation mode for writing data representing a constant value to at least one of the first and second image memories in response to a reset signal being applied in the first to fourth operation modes. 9. The image reproducing method according to claim 8, wherein a transition is made.