KR100284075B1 - Method for forming fuse box of semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a fuse box of a semiconductor device, wherein the first metal wiring is left in a region to be repaired without being completely etched, and then a large contact hole is formed in the entire repair region by wet and dry etching when the second metal wiring is formed. Forming, connecting the first metal wiring and the second metal wiring, blanking etching, forming a passivation layer and patterning so that the fuse box area is exposed to prevent the failure of the device during the reliability test, the production yield of the device And a technology capable of improving reliability.

Description

Method for forming fuse box of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fuse box of a semiconductor device. In particular, in a method of improving reliability due to high integration of a semiconductor device, a passivation layer is repaired by forming a new metal wiring structure when forming a fuse box. The present invention relates to a technology that can prevent the device from failing during reliability testing by allowing land to be buried in a stable manner.

As semiconductor devices become highly integrated due to the development of general micropattern forming technology, in the case of DRAM devices, when the memory capacity is increased by four times, the size of the chip is also increased by about two times.

Therefore, since the rate of partial defects is increased, the yield of a complete chip having no defects in the manufactured chip is reduced and productivity is reduced. Thus, an extra memory cell is formed in the chip, thereby exchanging with a cell in which a defect occurs during the manufacturing process. In order to increase the yield of the chip.

In addition, it is essential for the semiconductor device to operate normally in a high pressure / high temperature environment and to improve the repair rate in order to increase the yield of the device.

To this end, the protection structure of the fuse box area, which is vulnerable to external temperature / pressure / humidity, is improved by utilizing a new metal wiring structure, so that the device can be stably protected from the external environment, and the space for the area to be repaired should be increased a little more. This has risen.

1A to 1D are diagrams illustrating a process of manufacturing a fuse box of a semiconductor device according to the related art.

First, the first oxide film 2, the repair layer 3, the second oxide film 4, and the first metal wiring 5 are sequentially formed on the semiconductor substrate 1, and then the first photoresist film pattern 20 is formed. (See FIG. 1A).

Next, the first photoresist film pattern 20 is dry-etched with a mask to form a first metal wiring 5 pattern, and then the first interlayer insulating film 6, the SOG film 7, and the second interlayer insulating film 8 are formed. After sequentially forming the second photosensitive film pattern 25 is formed on the entire surface (see Fig. 1b).

Next, the second photoresist pattern 25 is wetted or dried using a mask to be etched until the first metal wiring 5 is exposed to form a contact hole 9.

Next, the second metal wiring 10, the first passivation layer 11, and the second passivation layer 12 are sequentially formed on the entire surface of the structure, and then the third photoresist layer pattern 30 is formed on the entire surface. (See FIG. 1C).

Then, the third photoresist pattern 30 is used as an etch mask and patterned until the second oxide film 4 is exposed (see FIG. 1D).

According to the prior art as described above, when the passivation layer is buried well because the metal wiring around the fuse box is exposed, voids are generated to cause a failure during the reliability test.

In addition, when the part to be repaired using the photosensitive film is etched by dry etching method, the insulating layer between the metal wirings is exposed to the outside, and external moisture can penetrate into the inside of the device through this, which causes a failure in reliability. There is a problem that the yield and reliability of the deterioration.

Accordingly, the present invention is to solve the above problems and to form one large contact hole in the entire repair area by wet and dry etching when the second metal wire is formed after the first metal wire is left in the area to be repaired without being completely etched. To connect the first and second metal wires, etch the blanket, form a passivation layer, and then pattern the process to expose the fuse box area to prevent failure during reliability test, thereby improving device reliability and yield. It is an object of the present invention to provide a method for forming a fuse box of a semiconductor device.

1a to 1d is a process diagram of a fuse box manufacturing of a semiconductor device according to the prior art

2a to 2d is a manufacturing process diagram of the fuse box of the semiconductor device according to the present invention

<Explanation of symbols on the main parts of the drawing>

1, 50: semiconductor substrate 2: first oxide film

3, 54: repair layer 4: second oxide film

5, 58: first metal wiring 20, 66: first photosensitive film pattern

6, 60: first interlayer insulating film 7: SOG film

8, 64: second interlayer insulating film 25, 76: second photosensitive film pattern

9 contact hole 10, 68 second metal wiring

11, 72: 1st passivation layer 12, 74: 2nd passivation layer

52: first insulating film 56: second insulating film

62 planarization layer 30 third photosensitive film pattern

According to the present invention for achieving the above object,

Sequentially forming a first insulating film, a repair layer, a second insulating film, a first metal wiring, a first interlayer insulating film, a planarization layer, and a second interlayer insulating film on the semiconductor substrate;

Forming a contact hole by forming a first photoresist layer pattern on the second interlayer insulating layer and etching until the first metal wiring is exposed with an exposure mask;

Forming a second metal wiring on the entire surface of the structure;

Etching the portion of the second metal wiring to the fuse box until the second insulating layer is exposed by using an etching mask;

Sequentially forming a first passivation layer and a second passivation layer on the entire surface of the structure;

Forming a second photoresist pattern on the second passivation layer and patterning the second photoresist layer through an exposure mask until the second insulating layer is exposed;

Hereinafter, a method of forming a fuse box of a semiconductor device will be described in detail with reference to the accompanying drawings.

2a to 2d is a process diagram of the fuse box manufacturing of the semiconductor device according to the present invention.

First, the first insulating film 52, the repair layer 54, the second insulating film 56, the first metal wiring 58, the first interlayer insulating film 60, and the planarization layer 62 are disposed on the semiconductor substrate 50. ), The second interlayer insulating film 64 is sequentially formed, and then the first photoresist film pattern 66 is formed in a portion intended to be a fuse box region.

Here, the first and second insulating layers 52 and 56 are formed of an oxide film, the repair layer 54 is used as a word line or a bit line, and the first metal wiring 58 is formed of a tungsten or aluminum film. do.

In addition, the first and second interlayer insulating films 60 and 64 are formed of a nitride film and a silicon-rich oxide film, respectively, and the planarization layer 62 is formed of a spin on glass (SOG) film (see FIG. 2A). )

Next, using the first photoresist pattern 66 as an exposure mask, the contact hole is formed by etching until the first metal wiring 58 is exposed.

Next, a second metal wiring 68 is formed on the entire surface of the structure, and then the second insulating layer 56 is exposed by using an etching mask on a portion of the second metal wiring 68 that is intended as a fuse box. Blanket etch until

At this time, the inner wall of the fuse box is slightly overetched by the etching selectivity between the second metal wiring 68 and the second interlayer insulating film 64, and the second metal wiring 68 is formed by the blanket etching. A spacer film isolates the first interlayer insulating film 60 and the planarization layer 62 from an external environment, and exposes the second interlayer insulating film 64 (see FIG. 2B).

Next, the first passivation layer 72 and the second passivation layer 74 are sequentially formed on the entire surface of the structure, and then the second photoresist layer pattern 76 is formed.

Here, the first passivation layer 72 is formed of a PE-oxide film, and the second passivation layer 74 is formed of a PE-nitride film. The embedding of layers 72 and 74 can be easily buried as compared with the prior art. (See Figure 2c)

Next, the second photoresist pattern 76 is dry-etched with an exposure mask to pattern the second insulating layer 56 until the second insulating layer 56 is exposed to expose the fuse box region.

At this time, the first and second passivation layers 72 and 74 still surround the fuse box sidewalls, and the inside of the device is protected from the external environment (see FIG. 2D).

As described above, the formation structure of the new fuse box according to the present invention prevents buried or void generation during the conventional passivation layer embedding so that the inside of the device is completely blocked from external moisture, thereby ensuring reliability. There is an advantage of preventing the device from failing.

In addition, in the present invention, by increasing the repair rate of the device by securing a wider margin of the portion to be repaired, there is an advantage that can improve the reliability and yield of the semiconductor device.

Claims (5)

Sequentially forming a first insulating film, a repair layer, a second insulating film, a first metal wiring, a first interlayer insulating film, a planarization layer, and a second interlayer insulating film on the semiconductor substrate; Forming a first photoresist layer pattern on the second interlayer insulating layer, the first photoresist layer pattern protecting a portion scheduled as a first metal wiring and exposing a portion intended as a fuse box region; Etching the stacked structure of the second interlayer insulating layer, the planarization layer, and the first interlayer insulating layer using the first photoresist pattern as an etch mask; The second metal layer and the first metal layer are vulcanized to form a first metal wiring and a second metal wiring, wherein the second metal wiring is formed in a spacer form on an etching surface of the stacked structure, and the etching process is excessive. Etching the second insulating film having a predetermined thickness by performing the etching process; Forming a first passivation layer and a second passivation layer on the entire surface; A second photoresist layer pattern is formed on the second passivation layer to expose a predetermined portion of the fuse box region, and the second passivation layer and the first passivation layer are etched using the second photoresist pattern as an etch mask. Protecting the side wall of the fuse box region; And removing the second photoresist pattern. The method of claim 1, wherein the repair layer is formed when a word line or a bit line is formed. The method of claim 1, wherein the first metal wiring and the second metal wiring are formed of tungsten or aluminum. The method of claim 1, wherein the first interlayer insulating film is formed of a nitride film, and the second interlayer insulating film is formed of a silicon-rich oxide film. The method of claim 1, wherein the first passivation layer is formed of a PE oxide layer, and the second passivation layer is formed of a PE nitride layer.

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