KR100279783B1 - Driving method for display and driving circuit and display device using same - Google Patents

Abstract

A driving circuit and a driving method for driving a display device functioning as a capacitive load such as a PDP (plasma display panel) in which light emission is displayed using a discharge phenomenon and each pulse for scanning and display is sequentially applied to a plurality of electrodes The present invention relates to a display device using the same, and more particularly to a display device using the same, which is capable of controlling the width of a high voltage pulse with a low power consumption and improving the light emission effect, A method of driving a display device for supplying and recovering a current, comprising the steps of: flowing current through a path in a charge supply source to an electrode through a resonance in a path to charge the electrode; The resonance in the other path is used to make the current flow.

According to such a configuration feature, the period of the pulse voltage of the display function of the PDP can be lengthened without increasing the number of driving circuits to improve the luminous efficiency and increase the number of pulses to obtain a display of high luminance

Description

Driving method for display and driving circuit and display device using same

The present invention relates to a driving circuit for driving a display device functioning as a capacitive load such as a PDP (Plasma Display Panel) in which light emission is performed using a discharge phenomenon and each pulse for scanning and display is sequentially applied to a plurality of electrodes, And a display device using the same.

Conventionally, CQ Publishing Co. Ltd. Issued " How to use FETs ", pp. 110-114 (1983) discloses a switching circuit and a method for blocking or passing an input signal by using a semiconductor device, which inputs a small signal at the source of the MOS transistor, draws the output signal at its drain, A substrate potential is set for a source or a drain so that the pn junction between the source and the drain is not biased in the forward direction under any condition, and the conduction and blocking of the signal are controlled by the gate voltage.

However, the prior art does not consider at all whether to use the stray diode between the drain and the substrate, as well as to pass or interrupt the high-voltage signal.

Conventionally, a method of driving several electrodes of a display element having a capacitive load, a method of driving the circuit by a simple push-pull circuit, and a method of reducing power consumption by using a power recovery circuit have been described .

A switching circuit 1201 is provided between the electrode 1112 of the display elements 604, 607, and 610 and the high voltage power supply 1115 in the former push-pull circuit, as shown in FIG. 39 And a switching circuit 1202 is disposed between the electrode 1112 and the ground level and a high voltage pulse is applied to the electrode 1112 by turning on and off these circuits 1201 and 1202 . When a circuit is driven in this manner, power consumption increases when the electrode is charged and discharged.

There are two types of PDP devices, namely, an AC type and a DC type.

In an AC type PDP, an electrode in a discharge space in the panel is covered with a dielectric layer, and a discharge charge is reciprocated on the dielectric layer. In this AC type driving device and driving method, pulses for display are continuously emitted by the memory effect by the wall charges on the dielectric layer.

On the other hand, in the DC type PDP, the electrodes in the panel are exposed in the discharge space, and electric charges due to discharge flow into the external circuit through the electrodes. Therefore, this type of PDP is referred to as a direct current type, that is, a DC type, and the memory function of the display pulse is executed by the floating charge in the discharge space.

As the driving method of the PDP, there are conventionally two methods of address / display separation method and address / display multiplexing method.

Such an address / display separation method is disclosed in, for example, Japanese Patent Laid-Open Publication No. 4-195188 (1990).

Referring to FIG. 46, one frame FM is divided into a plurality of subframes SF1 to SF4, and each subframe is divided into an address cycle and a display cycle. In this address cycle, as shown in FIG. 47, there are a priming period and a write period. In this priming period, discharge (Pw) -cells are performed in all the discharge cells. In the write period, each Y electrode Pf is scanned to select an electrode, and wall charges are once formed in the discharge cell by this scan pulse and a write pulse coinciding with the scan pulse. Only the discharge cells on which the wall charges are formed are caused to emit light by the display pulse Ps of the next display cycle.

This method requires a long time until an address cycle and a display cycle are simultaneously disconnected from all the discharge cells and once a wall charge is formed during an address period and then a display pulse is applied. Therefore, an AC Type PDP.

On the other hand, an address / display multiplexing method in the same AC type PDP driving method is disclosed in Japanese Patent No. 2,528,195

Referring to FIG. 48, one frame is divided into a plurality of subframes, and the emission time width of each subframe forms a binary system. In each of the subframes, the time is shifted on the line of the electrodes, and the lines are sequentially driven. The drive waveform in this subframe is once written by the write pulse Pw and the display pulse Ps is not emitted when the erase pulse P _E is applied, And emits light when the erase pulse P _E is not applied.

Further, in the driving method of the DC type PDP, since the memory effect is realized by using the space charge, it is necessary to apply the display pulse immediately after addressing. Therefore, they all belong to some sort of address / display multiplexing method. For example, Japanese Laid-Open Patent Publication No. 7-7246 discloses this driving method. In this method, a scanning pulse is applied to the cathode K, and a display pulse is applied to the anode A immediately thereafter. The scan of the panel is sequentially performed from the top to the bottom of the panel over one field time.

By the latter method using the power recovery circuit, the power consumption at the time of charge / discharge of the electrode can be sufficiently reduced. For example, Japanese Laid-Open Patent Publication No. 63-101897 (1988) discloses this method. In this method, the charge accumulated in the electrode during charging and discharging of the electrode, It can be recovered by using. According to this example, the circuit can be driven with a power of 1/10 times or less as required for a conventional circuit.

On the other hand, in the case of driving the electrode as the capacitive load, since the power recovery circuit includes the inductor, disposing the power recovery circuit for each electrode is difficult in terms of integration and also in terms of the number of parts. Therefore, it is preferable to dispose the power recovery circuit in common for all the electrodes. At this time, in the driving method in which the high voltage pulses are made different for each display element, it is necessary to arrange a switching circuit between the power recovery circuit and each of the electrodes. This switching circuit is described in Japanese Patent Application Laid-Open No. 2-92111 (1990). In this example, it is also described that the electric power accumulated and discharged at the time of charge / discharge of the electrode is recovered through the switch.

It is an object of the present invention to provide a display element driving method capable of controlling a width of a high voltage pulse with a simple circuit configuration at a low power consumption and a circuit for realizing the method.

There has been a problem that power consumption for dedicated devices is increased in the method of driving the electrodes using the push-pull circuit according to the related art, thereby increasing the power consumption of all devices. For example, conventionally, the power consumption of the high-voltage driver IC is increased as the frequency drive pulse is increased by using a high-voltage driver IC in this type of drive circuit. As a result, the high-voltage driver IC is damaged by the heat generated therein, and the reliability of the device is remarkably deteriorated.

As a method of recovering the electric power accumulated and discharged at the time of charge / discharge of the electrode using a switching circuit according to the prior art, there is a method of controlling only the presence or absence of the applied high voltage pulse and controlling the pulse width There is a way. According to the mode for driving the display device, it is necessary to control the pulse width of the high voltage pulse instead of controlling the presence or absence of the high voltage pulse. For example, in the case of an address electrode of an AC type plasma display, the pulse width of the high voltage pulse must be controlled according to the signal to be displayed. In addition, it is necessary to control the rise and fall of the pulse during such driving. However, this is not considered at all in the past.

Therefore, a first object of the present invention is to provide a driving method of low power consumption and a circuit for realizing the driving method even if the pulse width is arbitrarily selected.

Further, in the above-described conventional technique, since the period of the display pulse is short, the space charge in the discharge cell is increased, resulting in a problem that the luminous efficiency is low. There is also a problem that a large number of display pulses can not be applied. In addition, since pulses to be applied can not be commonly applied to electrodes, there is a problem that the number of circuits increases.

Hereinafter, the problems of the driving method of the above-mentioned prior art, particularly the driving method of AC type and DC type PDP will be described in detail.

In the address / display separation method of the AC type PDP shown in FIG. 46, 70% or more of the period of one field is required for the time of the address cycle, so that the time of the display cycle becomes 5 msec or less. In order to increase the luminance of the light emission, about 500 display pulses must be inserted between the display cycles within this period. Therefore, the period of the display pulse is shortened to about 10 mu sec. If the period of the display pulse is short, the number of discharges in a unit time increases. As a result, the space charges in the discharge cells increase and the discharge electrons slow down. As a result, the excitation probability of the Xe atoms, which are gases in the panel, becomes small and the luminous efficiency decreases.

On the other hand, if the time width of the display cycle is lengthened, the luminous efficiency is improved but the number of display pulses is reduced and the luminescence brightness is lowered. In order to lengthen the period of the display pulse and to increase the number of display pulses, the time width of the display cycle may be increased. However, the time width of the address cycle is shortened to cause erroneous discharge during the write operation for wall charge formation. Therefore, in the address / display separation method of the AC type PDP, there is a limit in further improving the luminous efficiency and increasing the brightness.

On the other hand, in the address / display multiplexing method of the AC type PDP shown in FIG. 48 and FIG. 49, one frame period can be used almost as a display time. Therefore, the period of the display pulse can be lengthened and the number of pulses applied can be increased. However, since the display is a matrix panel, the write pulse Pw and the erase pulse P _E must be independently applied to the X electrode and the Y electrode. Since these pulses Pw and P _E drive sequential electrodes as shown in FIG. 48, a driver circuit is required for each of these electrodes, thereby increasing the number of circuits.

The DC type PDP driving method shown in FIG. 50 and FIG. 51 is a DC type discharge method. Therefore, in order to increase the luminous efficiency, if the pulse width of the display pulse applied to the anode is not very narrow, about 0.2 .mu.sec If such a display pulse generating circuit is constituted by a power recovery circuit, there is a problem that the recovery rate and its efficiency are lowered.

In order to discharge with such a narrow pulse, the voltage value of the pulse is 300V, which is a high voltage, so that there is a problem that the breakdown voltage of the circuit element used must be increased to cope with such a high voltage.

In addition, as a problem of the driving method itself, display pulses to be applied to the anode are interrupted in the respective subfields, and the time deviates from each other for each electrode. Therefore, a driver circuit is required for each electrode, thereby increasing the number of circuits.

Another object of the present invention is to solve such a problem, and it is an object of the present invention to provide a liquid crystal display device capable of improving the light emission effect by lengthening the period of the display pulse and increasing the number of pulses to be applied to obtain high brightness, A method of driving a PDP, a driving circuit, and a driving apparatus.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG.

FIG. 2 is a timing diagram showing the operation timing of FIG. 1;

FIG. 3 is an equivalent circuit diagram of the circuit shown in FIG. 1 during charging; FIG.

FIG. 4 is a timing chart showing the operation timing of the circuit shown in FIG. 1 of the present invention; FIG.

FIG. 5 is a circuit diagram showing another embodiment of the present invention. FIG.

FIG. 6 is a timing chart showing the operation timing of the circuit configuration shown in FIG. 5;

FIG. 7 is a circuit diagram showing still another embodiment of the present invention. FIG.

FIG. 8 is a timing chart showing the operation timing of the circuit configuration shown in FIG. 7; FIG.

FIG. 9 is a circuit diagram showing another embodiment of the present invention. FIG.

FIG. 10 is a circuit diagram of a negative voltage circuit usable in the circuit shown in FIG. 9; FIG.

11 is a circuit diagram of another embodiment of the present invention.

12 is a timing chart showing the operation timing of the circuit configuration shown in Fig. 11; Fig.

13, 14 and 15 are circuit diagrams showing still another embodiment of the present invention.

16 is a cross-sectional view of an integrated circuit;

17 is a cross-sectional view of another embodiment of an integrated circuit;

FIG. 18 is a schematic view showing a circuit configuration in which the present invention is applied to a matrix display device. FIG.

Fig. 19 shows an example of a voltage waveform applied to each electrode of the circuit shown in Fig. 18; Fig.

20 is a circuit diagram showing an example of a sub-pulse switch according to the present invention;

21 is a timing chart showing operation timing of the circuit shown in Fig. 20; Fig.

22 is a timing chart showing another operation timing;

23 to 28 are circuit diagrams showing various embodiments of the present invention.

29 is a circuit diagram showing a configuration of a sub pulse switch of a low voltage pulse;

FIG. 30 is a truth table showing the operation of the circuit shown in FIG. 29; FIG.

FIG. 31 is a circuit diagram showing still another embodiment of the present invention. FIG.

Figure 32 is a truth table showing the operation of the circuit shown in Figure 31;

FIG. 33 is a circuit diagram showing still another embodiment of the present invention. FIG.

FIG. 34 is a circuit diagram showing still another embodiment of the present invention. FIG.

FIG. 35 is a timing chart showing the operation timing of the circuit shown in FIG. 34; FIG.

FIG. 36 is a block diagram showing a circuit configuration using the circuit shown in FIG. 20; FIG.

FIG. 37 is a block diagram showing a circuit configuration when the present invention is applied to a matrix panel; FIG.

FIG. 38 is a circuit diagram showing an example of a circuit using a one-way switch according to the present invention; FIG.

FIG. 39 is a diagram showing a conventional circuit configuration; FIG.

FIG. 40 is a circuit diagram showing an example of a circuit in which a bipolar transistor of the present invention is used; FIG.

41 is a circuit diagram showing an example of a circuit in which a voltage holding circuit is disposed on each electrode of the present invention;

FIG. 42 is a circuit diagram showing an example of a circuit for controlling the inductance value of the present invention; FIG.

FIG. 43 is a circuit diagram showing an example of a control circuit for a switching circuit according to the present invention; FIG.

FIG. 44 is a timing diagram illustrating each operation of the switching circuit of the present invention; FIG.

FIG. 45 is a diagram showing signal drive waveforms of respective electrodes in a second embodiment of a method of driving a PDP (plasma display panel) according to the present invention; FIG.

FIG. 46 is a diagram showing an example of a conventional address / display multiple driving method of an AC type PDP; FIG.

FIG. 47 is a diagram showing a signal driving waveform in the conventional driving method shown in FIG. 46; FIG.

FIG. 48 is a view showing an example of a conventional address / display multiple driving method of an AC type PDP; FIG.

Fig. 49 is a diagram showing a signal drive waveform in the conventional drive method shown in Fig. 48; Fig.

FIG. 50 is a view showing an example of a conventional address / display separation driving method of a DC type PDP; FIG.

51 shows the scanning procedure in the conventional driving method shown in FIG. 50; FIG.

FIG. 52 is an exploded perspective view showing the structure of the PDP; FIG.

FIG. 53 is a view showing the wiring of electrodes in the PDP shown in FIG. 52; FIG.

FIG. 54 is a view showing a scanning method in the PDP driving method according to the present invention; FIG.

FIG. 55 is a diagram showing signal drive waveforms of respective electrodes in a second embodiment of a method of driving a PDP according to the present invention; FIG.

FIG. 56 is a diagram showing signal drive waveforms of the respective electrodes in the third embodiment of the method of driving a PDP according to the present invention; FIG.

Fig. 57 is a view showing signal drive waveforms of the respective electrodes in the fourth embodiment of the driving method of the PDP according to the present invention; Fig.

FIG. 58 is a view showing one specific example of the gray scale display method in the driving method of the PDP according to the present invention; FIG.

FIG. 59 is a view showing another specific example of the gray scale display method in the driving method of the PDP according to the present invention; FIG.

60 is a configuration diagram showing a second embodiment of a display device of a PDP according to the present invention;

FIG. 61 is a circuit configuration diagram showing one specific example of the Y power recovery circuit and the pulse voltage distribution circuit shown in FIG. 60; FIG.

FIG. 62 is a voltage waveform diagram for explaining the operation of the specific example shown in FIG. 61; FIG.

FIG. 63 is a circuit configuration diagram showing another specific example of the Y-power recovery circuit and the pulse voltage distribution circuit shown in FIG. 60; FIG.

FIG. 64 is a voltage waveform diagram for explaining the operation of the specific example shown in FIG. 63; FIG.

FIG. 65 is a circuit configuration diagram showing one specific example of the X power recovery circuit in FIG. 60; FIG.

FIG. 66 is a voltage waveform diagram for explaining the operation of the embodiment shown in FIG. 65; FIG.

FIG. 67 is a circuit configuration diagram showing one specific example of the A electrode driving circuit in FIG. 60; FIG.

FIG. 68 is a voltage waveform diagram for explaining the operation of the embodiment shown in FIG. 67; FIG.

Figure 69 is a configuration diagram showing a second embodiment of a display device of a PDP according to the present invention;

FIG. 70 is a circuit configuration diagram showing one specific example of the pulse voltage distribution circuit shown in FIG. 46; FIG.

FIG. 71 is a voltage waveform diagram for explaining the operation of the specific example shown in FIG. 70; FIG.

Figure 72 is a system block diagram showing one application example of a display device of a PDP according to the present invention;

Figure 73 is a system block diagram showing another application example of the display device of the PDP according to the present invention;

FIG. 74 is a system block diagram showing another application example of the PDP display apparatus according to the present invention; FIG.

FIG. 75 is a system block diagram showing another application example of a display device of a PDP according to the present invention; FIG.

In order to achieve the first object, the present invention provides a method of driving a plurality of electrodes of a display element, which is a capacitive load, such that the discharge current path of the electrode is different from the charge current path, Lt; / RTI >

Further, the present invention simultaneously performs charging and discharging of the electrodes of the display element.

Further, the present invention detects the number of discharged electrodes and the number of charged electrodes in the electrodes of the display element, and controls the value of the power recovery inductance according to the detected number.

Further, the present invention is characterized in that a series circuit including a first switch, a first diode and a first inductor is connected to a power source or a charged capacitor, and its output terminal is connected to at least two electrodes via at least two first unidirectional switches And the first switch, the first diode and the first unidirectional switch are conducted when the electrode is charged, and the other series circuit including the second switch, the second diode and the second inductor are connected to the power supply or the charged capacitive element And the output terminal thereof is connected to at least two electrodes via at least two second unidirectional switches, and the second switch, the second diode and the second unidirectional switch are conducted when the electrode is discharged.

The output terminal of the first inductor and the output terminal of the second inductor are connected to a switching circuit for maintaining the output terminal of the first inductor and the output terminal of the second inductor at the level of the high- To the switching circuit.

In addition, the present invention comprises first and second unidirectional switches each including a diode and a FET using a series connection circuit.

Further, in the present invention, the first and second unidirectional switches are constituted by using a bipolar transistor circuit.

In addition, the present invention is characterized in that a plurality of series circuits are constituted by a first switching circuit, a first diode and a first inductor respectively, and an inverse number between inductances of a plurality of first inductors is constituted by a substantially binary system, A second switching circuit, a second diode and a second inductor, and the inductance values of the plurality of second inductors are configured as binary systems.

In addition, the present invention relates to a voltage holding circuit for holding the electrode level of the display element 3 at the level of the high voltage power source, and another voltage holding circuit for holding the level of the low voltage power source to the electrode of the display element.

Further, in the present invention, the electrode of the display element is used as the address electrode of the AC type plasma display.

In order to achieve the above second object, the present invention provides a plasma display panel comprising at least a plurality of cells, each of which has three electrodes (X electrode, Y electrode, A electrode) and a discharge space, At least the surface adjacent to at least the discharge space of at least two of the X electrodes and the Y electrodes is covered with an electrical insulator and a set of cells including a total of a plurality of cells is divided into a plurality of sets of cells And Y electrodes of cells belonging to a middle set of the same cells in the middle cell of the cell are connected to each other by electrodes. The driving method of the plasma display panel comprises a step of generating information on a plasma display panel Fields are divided into a plurality of subfields, and the number of divided subfields is k, and a set A (hereinafter referred to as " medium set A ") of cells in a set of a plurality of cells, One subfield A (hereinafter referred to as " Scanning is referred to as a sub-field A "), and injection of the other sub-fields than the sub-field A by a set of a particular cell for a set of other than the cell group of the cell A is to be scanned a subfield A.

Further, the present invention applies a pulse electrode to at least one of the Y electrode and the A electrode, or both, in the scanning function.

Further, the present invention makes it possible to carry out the scanning function by at least one of the middle sets of cells and to perform the display while executing the next scanning function.

In the present invention, the X electrodes of the cells belonging to the middle set of cells are connected by an electric conductor.

Further, the present invention applies a pulse voltage to at least one of the X electrode and the Y electrode or both of the display function.

In the present invention, the display function alternately applies a pulse voltage to the X electrode and the Y electrode.

Further, the present invention is characterized in that there is an arbitrary time domain in the display period, and a periodic pulse is applied to the X electrode in common to the set of the large sum of cells over the time domain in at least one or a plurality of sets of the cells And a pulse voltage having at least a scan function and a display function simultaneously or separately is applied to the Y electrode in a set of each cell of the set of cells in the middle sum sum.

Further, in the present invention, the X electrodes of all the cells belonging to a large set of cells are connected by an electric conductor.

In the present invention, a set of cells in the middle sum sum is a set of cells.

In the present invention, a pulse electrode having a priming function is also applied to the Y electrode.

In the present invention, the scan function is performed on one of the coalesced sums of spatially adjacent cells, and then the pulse voltage is multiplied by the number k of the subfields divided into the A electrodes or an integer multiple thereof, while the scan function is performed on the other side .

In addition, the present invention allows the pulse voltage having the priming function to overlap with the periodic pulse voltage applied to the X electrode at least once in a time-wise manner.

Further, the present invention applies a periodic pulse voltage to the X electrode for at least one field period of display information.

Also, in the present invention, the periodic pulse voltage applied to the X electrode and the pulse voltage applied to the Y electrode and having the priming function have different polarities from each other.

Further, in the present invention, the periodic pulse voltage applied to the X electrode is negative and the pulse voltage applied to the Y electrode and having the priming function is positive.

Further, in the present invention, the periodic pulse voltage applied to the X electrode is temporally different among a set of at least two cells.

Further, the present invention is characterized in that the first pulse voltage of the periodic pulse voltage is applied to the X electrode of the middle sum of arbitrary cells in the subfield, and the pulse voltage having the scanning function applied to the Y electrode of the same cell in the same subfield Apply at the same time interval.

Further, the present invention is characterized in that a pulse voltage having a priming function is applied to a Y electrode of a large sum of arbitrary cells in a subfield, a pulse voltage having a scanning function applied to a Y electrode of a large sum of the same cells in the same subfield .

Further, in the present invention, a pulse voltage having a priming function is applied to the Y electrode at the same time in a set of a large sum of at least one or a plurality of cells among a set of cells.

In the present invention, a pulse voltage having a scanning function of an arbitrary subfield is applied to the Y electrode of a cell in which the waveform is concentrated, and a pulse voltage having a scanning function of a subfield different from that of the subfield is applied, (K, n, p: constants) of the pulse voltage of the information to be displayed on the display panel.

In addition, the present invention ensures that the periodic pulse voltage applied to the X electrode of the middle sum of arbitrary cells and the pulse voltage having the scanning function applied to the Y electrode of the middle sum of the cells do not overlap with each other in terms of time.

In addition, the present invention ensures that the periodic pulse voltage applied to the X electrode of the middle sum of arbitrary cells and the pulse voltage applied to the Y electrode of the middle sum of the cells and having the display function do not overlap with each other in terms of time.

In addition, the present invention prevents the pulse voltage applied to the A electrode from overlapping with the periodic pulse voltage applied to the X electrode and the pulse voltage having the display function applied to the Y electrode in terms of time.

In the present invention, a pulse voltage having a scanning function of any subfield is applied to a set of cells, a pulse voltage having a display function is periodically applied, and the application of the periodic pulse voltage having the display function is performed next Before the pulse voltage having the priming function of the subfield of the subfields is input.

Further, the present invention applies a pulse voltage having an erase function between a pulse voltage having a display function and a pulse voltage having a priming function.

Further, the present invention applies the pulse voltage having the preliminary discharge function after the periodic pulse voltage having the display function is stopped and before the pulse voltage having the priming function is applied.

Further, the present invention makes the number of pulse voltages having a display function different in at least two subfields.

In the present invention, the number of pulse voltages having a display function is approximately 1: 2: 4 in at least three subfields.

In addition, the present invention provides a plasma display panel comprising at least a plurality of cells, each of the cells having at least three electrodes of an X electrode, a Y electrode and an A electrode and a discharge space, A plurality of cells including a total of a plurality of cells are divided into a plurality of sets of cells, and Y electrodes of cells belonging to a middle set of the same cells in the set of cells are connected to each other And the information displayed on the plasma display panel is divided into a plurality of (k) subfields, the plasma display panel comprising a plurality of cells, Means for scanning one subfield A (hereinafter referred to as "subfield A") among a plurality of subfields by a set A (hereinafter referred to as "medium set A") of cells of the subfield A, A cell that is different from A While a set of scanning a sub-field A has a scanning means for the other sub-fields than the sub-field A by a set of a particular cell.

In the present invention, the scanning function is performed by providing means for applying pulse electrodes to at least one of the Y electrode and the A electrode or both.

The present invention also includes means for executing the scanning function by at least one of the middle sets of cells and means for executing the display function during execution of the next scanning function.

In the present invention, the X electrodes of the cells belonging to the middle set of cells are connected by an electric conductor.

Further, the present invention has means for applying a pulse voltage to at least one of the X electrode and the Y electrode or both of them by a display function.

Further, the present invention has means for alternately applying a pulse voltage to the X electrode and the Y electrode in the display function.

In addition, the present invention is characterized in that there is an arbitrary time domain in the display period and, in at least one or more of the middle sets of cells, Means for applying a pulse signal and means for applying a pulse voltage having at least a scanning function and a display function simultaneously or separately to the Y electrode in the set of the cells of the set of cells in the middle sum sum.

Further, in the present invention, the X electrodes of all the cells belonging to a large set of cells are connected by an electric conductor.

In the present invention, a set of cells in the middle sum sum is a set of cells.

The present invention also includes means for applying a pulse electrode having a priming function to the Y electrode.

Further, the present invention is characterized in that it comprises a means for performing a scanning function on one of a set of spatially adjacent cells and a means for performing a scanning function on the other side by the number k of sub- Lt; RTI ID = 0.0 >

Further, the present invention has means for overlapping the pulse voltage having the priming function and the periodic pulse voltage applied to the X electrode at least once in time.

Further, the present invention has means for applying a periodic pulse voltage to the X electrode for at least one field period of display information

Further, the present invention has means for making the periodic pulse voltage applied to the X electrode different from the polarity of the pulse voltage applied to the Y electrode and having a priming function.

The present invention also includes means for making the periodic pulse voltage applied to the X electrode the pulse voltage of the negative electrode and means for applying the pulse voltage having the priming function to the Y electrode as the positive pulse voltage.

Further, the present invention has means for making the periodic pulse voltage applied to the X electrode temporally different among a set of at least two cells.

Further, the present invention is characterized in that the first pulse voltage of the periodic pulse voltage is applied to the X electrode of the middle sum of arbitrary cells in the subfield, and the pulse voltage having the scanning function applied to the Y electrode of the same cell in the same subfield At the same time interval.

Further, the present invention is characterized in that a pulse voltage having a priming function is applied to a Y electrode of a large sum of arbitrary cells in a subfield, a pulse voltage having a scanning function applied to a Y electrode of a large sum of the same cells in the same subfield As shown in Fig.

Further, the present invention has means for applying a pulse voltage having a priming function to the Y electrodes at the same time in at least one or more of the middle set of cells.

Further, the present invention is characterized in that it comprises a means for applying a pulse voltage having a scanning function of an arbitrary subfield to a Y electrode of a cell having a large sum and a means for applying a pulse voltage having a scanning function of a subfield different from the subfield to the Y electrode (K, n, p: integer) of the pulse voltage of the information to be displayed on the A electrode during the application of the pulse voltage.

In addition, the present invention has a means for preventing the periodic pulse voltage applied to the X electrode of the middle sum of any cell and the pulse voltage having the scanning function applied to the Y electrode of the middle sum of the cells from overlapping with each other in terms of time.

Further, the present invention has means for preventing the periodic pulse voltage applied to the X electrode of the middle sum of any cell and the pulse voltage applied to the Y electrode of the middle sum of the cells from overlapping with each other temporally.

Further, the present invention has means for preventing the pulse voltage applied to the A electrode from overlapping with the periodic pulse voltage applied to the X electrode and the pulse voltage having the display function applied to the Y electrode in terms of time.

In addition, the present invention is characterized in that it comprises means for applying a pulse voltage having a scanning function of an arbitrary subfield to a set of cells, means for periodically applying a pulse voltage having a display function after a pulse voltage having a scanning function, And means for interrupting the application of the periodic pulse voltage before the pulse voltage having the priming function of the next subfield is applied.

Further, the present invention has means for applying a pulse voltage having an erase function between a pulse voltage having a display function and a pulse voltage having a priming function.

The present invention also has means for applying a pulse voltage having a preliminary discharge function after the periodic pulse voltage having the display function is stopped and before the pulse voltage having the priming function is applied.

Further, the present invention has means for making the number of pulse voltages having a display function different in at least two subfields.

Further, the present invention has means for making the number of pulse voltages having a display function in a ratio of approximately 1: 2: 4 in at least three subfields.

In the present invention, the means for executing the display function in a set of cells is configured to apply a periodic pulse from the power recovery circuit through a switch.

Further, the plasma display panel of the present invention is AC type.

Further, the present invention is a television display device, a data monitor display device, a television monitor display device for displaying a video signal from a camera, or an information display device in a public place.

[Example]

Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a switching circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation timing thereof.

The method of claim 1 also, Q1 is a PNP transistor in a bipolar transistor wherein a current circuit, Q2 is an N channel MOS FET, C _L, which functions as a driving element to reduce or cut off through the high-voltage signal is a capacitive load.

In the basic circuit of the present invention, the FET Q2 serves as a switch for passing and blocking the high voltage pulse V _IN by the gate V _G of the FET Q2 in accordance with the low voltage input signal Vc (101). Under these conditions, the high voltage pulse V _IN is applied from the drain D side to the source S side, whereby the FET Q2 has a function of supplying the capacitive load C _L.

Hereinafter, the operation thereof will be described in accordance with the timing chart shown in FIG.

Since the emitter of the transistor Q1 is grounded, the "L" level (V _H -V _DD ) of Vc shown in FIG. 2 is applied to the base B to turn on the transistor Q1. When the transistor is a silicon device, the voltage of the emitter E is about 0.7 V larger than the base voltage. The difference between the emitter voltage and the high voltage V _H is applied through resistor 102 to form current Io.

The current Io flows from the collector C of the transistor Q1 through the resistor R. [ In this way, a voltage is generated between the source and the gate of the FET Q2.

3 is an equivalent circuit diagram of a circuit for charging the gate input capacitance C _i of the FET Q2. The gate voltage V _G is obtained by the following equation.

[Formula 1]

However, τ = C _i R, R represents the resistance value of the resistance R shown in FIG. 1, and Io represents the intensity of the current.

Theta of the above equation is the rising time constant of the FET Q2. The resistance R is, for example, 30 kΩ, C _i , is, for example, 100 pF, and τ is equal to 37 μsec. As can be seen from Equation 1, the current intensity Io and the time constant? Can be determined independently of each other. In order to drive the FET Q2 at high speed, the rise time constant? Should be made as small as possible.

Specifically, the gate input capacitance C _i is determined by the above-mentioned components. However, if the resistance value R is small, the voltage between the gate G and the source S becomes smaller than the threshold voltage V _TH and the conductivity is insufficient. Therefore, the current intensity Io is increased so that the voltage between the gate G and the source S becomes equal to or higher than the threshold voltage. However, if this voltage is too high, the voltage between the gate G and the source S will exceed the breakdown voltage V _{GS max} , causing the device to break. To prevent this, the Zener diode 104 is connected in parallel with the resistor R between the gate G and the source S. Therefore, considering the product of R and Io, the following relation holds.

[Formula 2]

Where T is the pulse period of the input signal V _IN .

As a result, the gate is driven at a high speed so that the resistance value R between the drain D and the source S is reduced, and the FET Q2 functioning as the switching element can be made conductive.

The period T ₂ of the low-voltage input signal V _C shown in FIG. ₂ will be described below.

The transistor Q1 and the FET Q2 are turned off by applying a low voltage input signal V _C of "H" level to the input terminal 101.

The charge accumulated in the gate input capacitance C _i and the capacitive load C _L during the pulse-free period passes through the parasitic diode between the drain and the substrate through the high-voltage pulsed drain voltage "L" level at the drain D side 0V) side. The charge accumulated in the capacitive load on the source S side gradually discharges and the peak value of the pulse gradually decreases as shown by Pl and P2 in FIG. 2, and eventually reaches the V _L level.

According to the above-described embodiment, when a high voltage of 200-300 V is applied, the switch, which conventionally requires a very complicated structure, can be made to have a simple structure that can drive the driving element with a low voltage output state.

Next, FIG. 4 shows an example in which the control signal Vc of the transistor Q1 in FIG. 1 is a pulse signal synchronized with the pulse of the high-voltage input signal V _IN . This reduces the power driving the gate of FET Q2 during the conduction period T ₁ by taking the current Io flowing through transistor Q1 by the pulsed current. As shown in FIG. 4, a signal Vc input to the base of transistor Q1 conductive during the period T1 of the FET Q2 is composed of a pulse, the duration of its "L" level is t _0. At this time, under the condition that the MOS FET Q2 is sufficiently turned on and the gate voltage does not exceed the breakdown voltage (V _GSmax ), the following equation is satisfied similarly to the above.

Next, the case where the PNP transistor Q1 is used as the bipolar transistor of the current circuit and the P-channel FET 2Q is used as the switching element will be described with reference to FIGS. 5 and 6. FIG.

5, the source of the P-channel FET Q2 functions as the input terminal of the high voltage signal V _IN , its drain functions as the output terminal, and the diode 504 is connected between the gate and the source. The emitter of the transistor Q1 in the current control circuit emitter side is connected via a resistor 502 for controlling the intensity of the power source V _H and a current having the same level and the H level of the high voltage signal V _IN. FIG. 6 is a graph showing variations of the input signal V _IN , the control signal V _C, and the output signal V _OUT in such a circuit configuration. When the FET Q2 is in a conductive state (sixth-degree T ₁₎ functioning as a switching element, current control circuit is turned off. At this time, when a high voltage pulse is applied to V _IN , a potential difference is automatically generated between the source and the gate of the FET Q2 by the Zener diode (504 in FIG. 5), and the FET Q2 is turned on. When the FET Q2 is turned off as indicated by Vc in FIG. 6, a negative pulse synchronized with the high voltage signal V _IN is applied to the base 501 of the fifth-stage transistor Q1. At this time, even when the pulse amplitude of the high voltage signal V _IN becomes V _H , since there is no potential difference between the gate and the source thereof, the transistor Q 1 is turned on and the FET Q 2 is turned off and the potential at the gate of the FET Q 2 becomes V _H.

Next, the case where the voltage holding circuit is added to the switching circuit shown in Fig. 1 will be described with reference to Figs. 7 and 8. Fig.

Hereinafter, the case where the N-channel FET Q3 is used as the voltage holding circuit element will be described.

The transistor Q1 functioning as the current source element has the same function as the transistor Q1 shown in Fig. Here, the voltage Vc shown in Fig. 8 is applied to the input terminal 701. Fig. Period T in the _first similarly to the period T ₁ shown in FIG. 2 FET Q2 is on and, with the high voltage pulse-drain voltage V _IN is applied to the drain D side is the source voltage of the source S side is applied to the load C _L V _OUT .

In the period T ₂ , the FET Q2 is turned off in the same manner as the period T _{2 shown} in FIG. The charge accumulated in the capacitive load and the input capacitance during the period T _{1 is} discharged to the "L" level (0 V) side of the high-voltage pulse-shaped drain voltage V _IN through the parasitic diode of the FET Q2. At this time, the holding input signal V _S shown in Fig. 8 is applied to the gate G input terminal 702 of the FET Q3 functioning as the voltage holding element in order to fix the potential of the source S side. FET Q3 is turned on by the "H" level of the input signal V _S maintained.

As a result, the potential V _OUT of the drain of the FET Q3 is maintained at 0V. Therefore, as shown in Fig. 8, the potential V _OUT of the source S of the FET Q2 is held at the "L" level (0 V). As described above, the N-channel FET is used as the FET Q2. However, the P-channel FET may be used as well as the voltage holding circuit. Similarly, FETs may be used as well as transistors (NPN or PNP) in which diodes are connected in parallel.

FIG. 9 is a circuit diagram showing another embodiment of the present invention. FIG. In the circuit shown in Fig. 1, the FET Q2 is switched by the signal on the high voltage side of the source, whereas the FET Q2 in the circuit of the present invention is switched by the signal on the ground potential side. The resistor R and the zener diode have the same functions as those described in Fig.

The P-channel FET Q3 is a device for flowing only a current Io like the transistor Q1 shown in FIG. 1. This device is composed of a P-channel FET Q4 and an N-channel FET Q5 constituting a current mirror circuit together with the FET Q3 Shifted so as to be controlled by the signal voltage between the power supply voltage V _PD of the low voltage and the ground potential.

In addition, the applied drain voltage V _IN has the same waveform as that shown in Fig. And reference numeral 901 denotes a signal circuit for driving the N-channel FET Q5. For example, it includes a shift register circuit and a latch circuit, and has a function of converting a video signal input in series into a parallel signal and outputting the signal in parallel. The power supply voltage of this signal circuit is the low-voltage power supply voltage V _DD

As will be described later, in this circuit, the PN junction separation semiconductor layer is set to a voltage lower than the ground voltage so that the component separating PN junction is not biased in the forward direction even if the output voltage V _OUT is lowered to a value equal to or lower than the ground voltage.

The diode Dl in FIG. 9 is provided so that the output voltage V _OUT does not fall above the ground potential

FIG. 10 is a view showing a configuration example of a negative voltage circuit usable in the circuit shown in FIG. 9; FIG. This circuit includes a clock signal V _CLK applied to the capacitor C ₂ and a signal obtained by applying this clock signal V _CLK and inverted to the cathode side of the diode D2 by an inverter circuit composed of a P-channel FET Q7 and an N-channel FET Q6 The voltage of the P-conductivity type semiconductor layer for separating parts can be made lower than the ground voltage by about 7 V in accordance with the charge pump principle.

First and the other exemplary circuit diagram of the present invention turns 11 a diagram showing its operation waveform claim 12 degrees, V _IN is a pulse input voltage, V _OUT is the output voltage, V _C is the switching control voltage, V _H is the high voltage circuit V _DD is the power supply voltage of the low-voltage circuit (logic circuit). Q2 is an N-channel MOS transistor for switching, and Q3 is an N-channel MOS transistor arranged to control the switch to be in a cutoff mode or a conduction mode. D is a diode functioning as a current path of the ground when the source voltage of the MOS transistor Q2 falls. This also protects the gate of the MOS transistor. Q1 is a depletion type P-channel MOS transistor.

The operation modes of the circuit shown in FIG. 11 will be described below with reference to FIG. 12. FIG. Current is supplied from the depletion type MOS transistor to the gate of the MOS transistor Q2 by setting the switch to the conduction mode and setting the control voltage Vc to the " L " level. Therefore, when the voltage pulse is applied to the input terminal V _IN , the source voltage (output voltage V _OUT ) rises and the drain voltage (input voltage V _IN ) rises. When the input voltage V _IN falls, the parasitic diode existing between the substrate and the drain of the MOS transistor Q 2 is biased in the forward direction, so that the output voltage V _OUT also falls. That is, the input voltage pulse can be made to flow to the output side. On the other hand, by setting the switch to the cut-off mode and setting the control voltage Vc to the "H" level, the MOS transistor Q3 absorbs the current which keeps the source and gate of the MOS transistor Q2 at the ground level and turns off the MOS transistor. Therefore, even when the voltage pulse is applied to the input terminal V _IN , the source voltage (output voltage V _OUT ) does not rise and the drain voltage (input voltage V _IN ) rises. That is, it is possible to prevent the input voltage pulse from flowing to the output side.

In Fig. 11, an NPN transistor or an insulated gate bipolar transistor in which diodes are connected in parallel may be used as the switching MOS transistor Q2.

In the present invention, a depletion type MOS transistor or a junction gate type depletion type transistor is disposed between a drain and a gate as means for raising the gate potential at the time of rising of the drain potential. This provides an advantage that a constant current can be supplied regardless of the voltage between the gate and the source of the MOS transistor. Although the present invention uses a P-channel depletion type MOS transistor, the same effect can be obtained even when an N-channel depletion type MOS transistor having a gate and a source connected thereto is used

FIG. 13 is a circuit diagram of another embodiment of the present invention. FIG. In this embodiment, the resistance R is used as means for raising the gate potential at the time of rising of the drain potential. The resistor made of polycrystalline silicon has a small parasitic capacitance and can easily realize the maximum applied voltage, which is suitable for the resistance of this embodiment.

FIG. 14 is a circuit diagram of another embodiment of the present invention. FIG. In this embodiment, the capacitor C is used as a means for raising the gate potential at the time of rising of the drain potential. Therefore, this embodiment has an advantage that the driving current for turning on the MOS transistor Q2 can be reduced as compared with the embodiment shown in Figs. 11 and 13.

FIG. 15 is a circuit diagram of another embodiment of the present invention. FIG. In this embodiment, the diode D2 is used as a means for raising the gate potential at the time of rising of the drain potential. In the case of this embodiment, the diode D2 is used as the capacitor of the embodiment shown in FIG. In the case of using a diode, there is an advantage in that a high voltage between a gate and a drain can be easily used, so that a high-voltage input pulse can be processed.

FIG. 16 is a cross-sectional view showing a state in which the diode D1 and the FET Q2 of FIG. 9 are formed in the integrated circuit. As described above, the diode Dl functions as a holding circuit for preventing the output voltage V _{OUT from} becoming lower than the ground voltage. In the circuit shown in Fig. 16, the potentials of the P-conductivity-type semiconductor layers 1003 and 1006 for component separation are the same as the potentials of the component-isolating PN junctions 1003 and 1003 even when the output voltage V _OUT becomes lower than the ground voltage (Between the ground terminal 1004) is set to a value equal to or lower than the ground voltage so as not to be biased in the forward direction.

More specifically, this drawing is a cross-sectional view of a semiconductor device showing a connection point of V _SUB shown in FIG. 9 and FIG. 10, and schematically shows a wiring of a power source. The structure of the semiconductor device shown in this figure is a structure in which a semiconductor element is separated from a P-conductivity type semiconductor substrate 1003 by a P-conductivity type diffusion layer 1006. The N conductive type diffusion layer 1011 is a source, the P conductive type diffusion layer 1010 is a substrate, an N conductive type recycling layer 1007, and an N conductive type buried layer 1007. In this case, (1004) is a drain. On the other hand, the right side is a cross-sectional view of the diode D1 shown in Fig. 9, in which the P conductive type diffusion layer 1010 is the anode, and the N conductive type diffusion layers 1005, 1004 and 1007 are cathodes.

The sectional view of the present semiconductor device itself is well known. However, a feature of this structure is that the potential of the P-conductivity-type semiconductor layers 1006 and 1003 for component separation is set to a value lower than the ground voltage by V _L2, which is not equal to the ground voltage but functions as V _SUB . For example, the output voltage V _OUT becomes lower than the ground voltage, which means that the cathode region (1005, 1004, 1007) of the diode on the right side shown in FIG. 10 is lowered below the ground voltage it means.

In the conventional method, when the potential of the P conductivity type semiconductor substrate is set to the ground voltage, the PN between the P conductive layer 1003 and the cathode region is biased in the forward direction. Accordingly, there is a problem that a current flows through the P-conductivity-type semiconductor layer 1003 for part separation, and the parasitic bipolar transistor existing between the adjacent elements is turned on and malfunction occurs. This problem can be prevented by the structure of the present invention.

According to the junction capacitance with respect to the substrate, that is, the example shown in FIG. 10, the capacitance between the drain region 1004 of the MOS transistor and the substrate 1003 is reduced and the element separated by the PN junction can be driven at high speed Effect is also obtained.

An external power source must be used to set the voltage of the P-conductivity-type semiconductor layer for component separation to a value lower than the ground voltage by V _L2 . However, by using the negative voltage circuit as shown in FIG. 10, the voltage V _SB of the P-conductivity-type semiconductor layer for component separation can be obtained without using any external negative voltage source.

FIG. 17 is a cross-sectional view showing another embodiment by a method of applying a substrate voltage of the above-described semiconductor device, which is a wiring diagram of a power source.

The semiconductor device shown in this figure is a semiconductor device in which the components are separated from the P-conductivity type epitaxial layer 1002 and the P-type epitaxial layer 1002 similarly to the vertical MOS transistor (left side of the drawing) Type MOS transistor having a structure to be implemented by the conductive diffusion layer 1006 coexist. This figure is a diagram showing a method of applying a substrate voltage.

In the figure, as described above, since the P conductive type epitaxial layer 1002 and the P conductive type semiconductor layer function as the P conductive type semiconductor layer for component separation, the potential of this region is set to a value equal to or lower than the ground voltage Wiring is performed. In this constitutional example, the N-conductivity type layer 1000 functions as a collector, the P-conductivity type layer 1002 functions as a base, and the N-conductivity type layer 1004 easily operates as a parasitic bipolar transistor functioning as an emitter .

As described above, when the potential of the P-conductivity-type semiconductor used for component isolation in the PN junction-isolated semiconductor integrated circuit device is lowered to the ground voltage or lower, the potential of the output terminal is lowered to the ground voltage or lower It is possible to prevent the parasitic element from being turned on and causing a malfunction, and the potential of the P-conductivity-type semiconductor layer used for separating the components can be set to a lower value It is possible to obtain an effect that the element can be driven at a high speed.

Next, an example of using the switching circuit of the present invention in a display device will be described with reference to FIGS. 18 and 19. In this embodiment, a discharge cell is used as an example of the capacitive load

When the discharge cell is driven by the video signal, the discharge cells are arranged up and down as shown in FIG. 18, and the video signal is applied to the electrodes thereof. One of the discharge cells used in this embodiment has a three-electrode structure as shown in FIG. 18, and is composed of an anode electrode A, a cathode electrode K, and a sub anode electrode SA. Hereinafter, a case where the discharge cells are arranged in 3 x 3 in this embodiment will be described.

The basic structure of the display device includes an anode driving system for driving the anode A, a scanning signal generating block 614 for generating a signal to be applied to the cathode electrode K, and a display signal generating block (for generating a display signal applied to the sub- 613). Here, the anode driving system includes a power recovery circuit 600 for generating a high-voltage pulse V _TP (the same waveform as V _IN ) and recovering power at that time, a switching circuit having a pulse distribution function for supplying each of the lines for the anode electrode And a pulse gate generation circuit 615 for supplying a pulse distribution signal.

Normally, when the capacitive loading is driven, the load capacity and the table usable amount of the circuit are charged at the rise of the high voltage pulse, so that a temporary current flows. On the other hand, when the high voltage pulse falls, the charges accumulated in the above-mentioned capacity are discharged, so that a temporary charge flows. Since the discharge cell constitutes a capacitive load as a load, a temporary current flows and a power loss is very large.

In order to reduce the power consumed in the display device, the power recovery circuit is generally used as described above. Here, the power recovery circuit is a circuit comprising a coil, a capacitor, and a switching element, and stores the charge in the capacitor without consuming it in the resistor.

In order to recover the power with high efficiency, a power recovery circuit should be disposed and a high voltage signal must be collected at each of the anode electrodes A or distributed to each of the anode electrodes A. To this end, a pulse splitter is needed that is capable of recovering and distributing high voltage signals in both directions. The above-described switch according to the present invention can be used for the above-described purpose as described below.

18, a power recovery circuit is used to reduce the power of a signal applied to the anode electrode A, and a switching circuit group is disposed at the next stage. Hereinafter, the case where the discharge cell is turned on by the video signal will be described in detail.

When a discharge cell is turned on by a video signal, a method of displaying luminance while changing a period is generally used, for example, a time division method within a field time is used. To ²⁶ (0 to 6 bits): By this method, one field is for example divided into seven sort period, the ratio of the duration of 2 ^0: 2 ^1: 2 ^2: 2 ^3: 2 ^4: 2 ⁵ Respectively. By combining seven sort periods, 2 ⁷ = 128 gray levels can be displayed.

FIG. 19 is a time diagram according to this method. The corresponding voltage must be applied to the anode electrode A to turn on the discharge cell. Further, in order to display the luminance information, it is necessary to apply the towngene pulse V _T holding the discharge to the anode electrode A. The number of townsent pulses is specified according to the time division within the field time described above.

FIG. 19 is a diagram showing waveforms V _{AT1 to} V _AT3 showing the above-mentioned designation period. Here, it represents a 0 ^H ~ 24 ^H in the first field. Here, 1 ^H corresponds to 63.5 × 10 ^-6 sec.

Hereinafter, the period T _D of FIG. 19 will be described.

In this period, the discharge cell shown in FIG. 18 is in a state in which 2-bit information (b2 in FIG. 19) is turned on. That is, the Al of the first row of the node electrode A is set to the selected state by V _A1 , the pulse voltage V _Sl (70) is applied to the first row S _A1 of the sub anode SA, and the aus discharge cell 604 Is turned on. However, the pulse voltage VK1 applied to the first column, Kl, must be applied to the cathode electrode K.

If the above procedure is performed in the second row and the second column, the third row and the third column, etc. in the same manner as described above according to the timing chart shown in FIG. 19, the discharge cells 604, 605, 606, 608 and 611 are the application pulse voltages 71, 72, 73, 74 of the sub-anode SA, the voltage pulse train V _T1 , V _T2 , V _T3 of the anode electrode A, K by the voltage pulse _strings V _Kll , V _K2l , and V _K3l . This state is indicated by a hatched line in FIG.

The display signal generating block 613 generates voltage pulses V _S1 , V _S2 and V _S3 in response to the luminance signal of the image. On the other hand, the scan signal generating block 614 generates voltage pulses V _K1 , V _K2 and V _K3 applied to the other row of the cathode electrode K. The voltage pulses V _A1 , V _A2 and V _A3 in FIG. 19 are generated in the pulse gate generating circuit 615. The power circuit 600 performs generation and power recovery of the high voltage pulses (V _TP equal to V _IN ) of FIG. 19.

The switching pulse group 60 extracts the pulse train V _TP sequentially transmitted from the power number circuit 600 in response to pulses V _{A1 to} V _A3 of the pulse gates and obtains the town segment pulses V _{T1 to} V _T3 . The switching circuit 601 in the switching circuit group 60 receives the high voltage pulse V _TP from the power recovery circuit 600 via the terminal 62 and simultaneously outputs the pulse gate signal on the control line Cl of the pulse gate signal generation circuit to the terminal 61). Then, control is performed to turn on or off the high voltage pulse V _TP , and the town pulse V _AT1 on the output line Al is output.

The switching circuits 602 and 603 in the switching circuit group 60 also operate in the same manner.

As a result, the waveforms shown in FIG. 19 are applied to the anode electrode A and the cathode electrode K, respectively. In this way, the discharge cell selected in response to the signal applied to the sub anode electrode SA is turned on, so that the image on the display device can be reproduced.

Since the power recovery circuit requires an inductor, it is generally difficult to form an integrated circuit, and when the anode driver circuit is manufactured in the form of an IC, a power recovery circuit must be disposed for all the anode electrodes. On the other hand, when the switching circuit according to the present invention is arranged, since only one power recovery circuit is sufficient, it is possible to manufacture the anode driving circuit more easily in the form of an IC.

Although the discharge cell is used as a display element in the above-described embodiment, the switching circuit according to the present invention is not limited to the liquid crystal and EL (electroluminescence) driven by a method of sequentially applying pulse voltages intermittently And can also be used for driving other display elements such as a panel.

In the above embodiment, the switch circuit for controlling conduction and interruption of the high-voltage positive pulse signal has been described. Hereinafter, an example of the switch for controlling conduction and interruption of the high-voltage negative pulse signal will be described.

20 is a circuit diagram showing an embodiment of the present invention, wherein Q2 is an n-channel MOS transistor, its source is connected to a substrate, the input signal voltage V _IN is applied to the source side, and the output signal voltage V _OUT . Q1 is an N-channel MOS transistor, and when the transistor Q2 is forcibly turned off, it is used as a current sinker. Dl is a diode used to protect the gate of the transistor Q2, and the value of the voltage amplitude of V _IN and V _OUT can be set to be equal to or lower than the gate breakdown voltage of the transistor Q2. Dl is a Zener diode having a breakdown voltage of about 5 to 30V. Rl is a resistor used for suppressing the intensity of the current flowing through the transistor Q1 and is not necessary when the power consumption by the current flowing through the transistor Q1 is not a problem.

FIG. 21 is a timing diagram showing a method for driving the circuit shown in FIG. 20; FIG. Since the parasitic diode exists between the drain of the transistor Q2 and the substrate and the drain functions as a cathode and the substrate functions as an anode, when an input signal voltage V _IN having an amplitude V _H is applied, regardless of the state of the control signal voltage Vc When V _IN is in the high voltage state, the output signal voltage V _{OUT is} also in the high voltage state. If the input signal voltage when the falling V _IN control signal voltage Vc is the low voltage state (state where the transistor Q1 off), the voltage V _X is because it has to keep strength transistor is in the on state and the falling the output signal voltage V _OUT. However, when the control signal voltage V _C is in the high voltage state (the transistor Q 1 is in the ON state) when the input signal voltage V _IN falls, the transistor Q 2 is forcibly turned off, so that the output signal voltage V _OUT maintains a substantially high voltage state . Therefore, the input signal voltage V _IN and the output signal voltage V _OUT can be conducted or cut off according to the value of the control signal voltage Vc. Thereby, the switching circuit can control the fall of the output voltage in accordance with the input pulse input through the input terminal V _IN .

FIG. 22 is another timing diagram showing a method for driving the circuit shown in FIG. 20; FIG. According to the present driving method, the control signal voltage Vc is brought into a high voltage state in synchronization with the fall of the input voltage signal V _IN only during a period in which it is not desirable to lower the output signal voltage. Therefore, the loss of the current flowing through the transistor Q1 by the control signal voltage Vc can be reduced, and the power consumption of the circuit can be reduced.

FIG. 23 is a circuit diagram showing another embodiment of the present invention. FIG. In this embodiment, since the capacitor Cl is added between the high-voltage power supply V _H and the V _X portion in the circuit of the embodiment shown in Fig. 20, when the transistor Q1 is turned off and the input signal voltage V _IN falls, the transistor Q2 It becomes easier to turn on. In this embodiment, disposed between the high-voltage power supply V _X and the unit capacitor Cl, it may be disposed between the _X portion and the ground, such as V or Vc part the same effect.

FIG. 24 is a circuit diagram showing still another embodiment of the present invention. FIG. In this embodiment, the diode D2 is added to the diode D1 in the circuit of the embodiment shown in Fig. 20, and the electrons are connected in series in the opposite direction to the latter. Therefore, even when the driving method shown in FIG. 21 is used, loss of current flowing through the transistor Q1 can be excluded if the control signal voltage Vc is in a high voltage state.

FIG. 25 is a circuit diagram showing another embodiment of the present invention. FIG. In the present invention, the resistor R2 is used instead of the diode D1 in the circuit of the embodiment shown in Fig. 20. For example, when a polycrystalline silicon resistor is used as the resistor R2, the occupied area and the parasitic capacitance can be reduced as compared with the diode. However, if the resistance value of the resistor R2 is too large, the gate of the transistor Q2 can not be protected. On the other hand, if the resistance value of the resistor R2 is too small, the transistor can not be turned on when the input signal voltage _VIN falls. Therefore, care must be taken in setting the resistance value

FIG. 26 is a circuit diagram showing still another embodiment of the present invention. FIG. In the embodiment described in FIG. 20, even when the output signal voltage V _OUT is maintained, when the input signal voltage V _IN falls, a voltage drop of about 10% of the voltage amplitude of the input signal voltage V _IN appears on the output signal voltage V _OUT In the present invention, two P-channel MOS transistors Q3 and Q4 are connected to form a current mirror in order to prevent a voltage drop and maintain a high voltage state, and a current flowing through the transistor Q3 is controlled by an N-channel MOS transistor Q5 . The same driving method as described in FIGS. 21 and 22 can be used if the control signal voltage VC is formed by the first control signal voltage V _Cl and the second control signal voltage V _C2 in order to drive the circuit.

FIG. 27 is a circuit diagram showing still another embodiment of the present invention. FIG. In this embodiment, the P-channel MOS transistors Q6 and Q7 are connected to form a current mirror, and the N-channel MOS transistor Q8 is used as a means for supplying a current to the gate of the transistor Q2 and setting it to the ON state. In this embodiment, since the output signal voltage can be raised in the state where the transistor Q2 is turned on, the parasitic diode between the drain of the transistor Q2 and the substrate can be driven in the forward direction without biasing. Therefore, it is possible to prevent the switching speed of the transistor Q2 from lowering due to the accumulation of the minority carriers. In addition, it is possible to set the transistor Q2 in an on state, and by setting to a value higher than the maximum voltage V _DH of the high-voltage power supply V to the input signal voltage _H V _IN, the input signal voltage V _IN is, even if a high voltage input to low signal It is possible to transmit over a wide voltage range from terminal V _IN to output terminal V _OUT . When the P-channel MOS transistor Q9 and the N-channel MOS transistor Q10 constitute an inverter and the first control signal voltage V _C1 and the third control signal voltage V _C3 are connected to form the control signal voltage Vc, The same method as described in Fig. 22 can be used.

V _L represents the power supply voltage of the signal line.

FIG. 28 is a circuit diagram showing another embodiment of the present invention. FIG. The present invention has a configuration having the circuit functions shown in FIG. 26 and FIG. 27. A power supply voltage of the high voltage V _H1 and V _H2 may be set to the same level, by setting one of the power supply voltage of the high voltage V _H2 of the 5~20V degree higher than the other of the input signal voltage V _IN V _H1 It is also possible to set the transistor Q2 to the ON state when it becomes the high potential level. If the third control signal voltages V _Cl , V _C2 , and V _C3 are connected, the same driving method as described in FIGS. 21 and 22 can be used.

FIG. 29 is a view showing another embodiment of the present invention. This embodiment shows a switching circuit effective when both the input signal voltage V _IN and the output signal voltage V _OUT are used at a level below the gate breakdown voltage.

Figure 30 is a true-false table of the circuit shown in Figure 29. When both the control signal voltage V _CON and the input signal voltage V _IN are in the low voltage state, the output signal voltage V _OUT maintains the previous output signal voltage V _OUT .

FIG. 31 is a circuit diagram showing another embodiment of the present invention. FIG. The present embodiment shows a switching circuit effective when both the input signal voltage V _IN and the output signal voltage V _OUT are used at a gate internal pressure or lower.

Figure 32 is a true-false table of the circuit shown in Figure 31. When both the control signal voltage V _CON and the input signal voltage V _IN are in the low voltage state, the P-channel MOS transistor Q3 is turned on, and the output signal voltage V _OUT becomes the high voltage state.

FIG. 33 is a circuit diagram showing another embodiment of the present invention. FIG. The present embodiment shows a switching circuit in which an N-channel MOS transistor Q2 is replaced with an NPN transistor Q2 and a diode DQ1, and an N-channel MOS transistor Q1 is replaced with an NPN transistor Q1. Thus, the circuit described in the above embodiment can realize a circuit having the same effect by replacing the MOS transistor Q2 with a bipolar transistor and connecting the diodes in parallel.

FIG. 34 is a diagram showing another example of a switch for a negative high-voltage input signal. FIG. The switching element Q2 is a P-channel FET in which the source is the input signal terminal and the drain is the output terminal. A gate bias is applied between the drain and the gate, and a diode Dl is connected to protect against excessive voltage. The circuit for driving the gate of the transistor Q2 is an N-channel FET Q1. A resistor Rl that limits the circuit is connected to the source of the FET Q1. Hereinafter, the operation mode of the circuit shown in FIG. 34 will be described with reference to the timing chart shown in FIG. V _IN is a negative high voltage input signal, and Vc is an input signal for controlling the transistor Q1 shown in FIG. When the input signal Vc is at the " L " level, the transistor Q1 is turned off, no potential difference is generated between the gate and the source, and the transistor Q2 is turned off. Therefore, when the voltage of the input signal V _IN changes, the output signal V _OUT is maintained in the high potential state. On the other hand, when the control signal Vc becomes " H " level, the transistor Q1 is turned on. Therefore, the gate voltage of the transistor Q2 falls and a voltage is applied between the gate and the source. As a result, the transistor Q2 is turned on and a negative high voltage pulse is generated in the output signal V _OUT as shown in FIG. 35. Here, the diode Dl functions as a protection diode between the gate and the drain of the transistor Q2. The series connection of the two diodes D1 and D2 shown in FIG. 24, the connection of the resistor R2 shown in FIG. 25, the addition of the function of holding the output voltage shown in FIG. 26, And they are included in the present invention.

FIG. 36 is a block diagram showing an embodiment of a circuit configuration according to the present invention. FIG. The present embodiment is configured to determine whether the pulse output from the 3-pulse generator is transmitted to each of two or more loads by opening or closing the switching circuit SW according to the present invention. Opening and closing of the switching circuit is executed in accordance with a control voltage signal _{Vc (1), V C (} 2) ‥‥‥ Vc (N) transmitted by the drive circuit. The driving circuit transmits the data input through the data input terminal to the shift register using the clock signal, performs the serial-to-parallel conversion, synchronizes them with the latch signal, and at the same time transfers the data to the other switching circuit as the control signal voltage .

The circuit shown in FIG. 36 can realize a pulse generating circuit using a power recovery circuit when the load is large (JP-A-61-132997). At this time, the power transmitted from the pulse generator to the load is fed back to the pulse generator at the load. Thus, a capacitive load driving apparatus with low power consumption can be realized.

FIG. 37 is a circuit block diagram showing an embodiment in which the present invention is applied to a matrix display element. The present embodiment shows an example in which a method of driving a matrix display element using the switching circuit of the present invention is used for driving a display device exemplified in Japanese Patent Application No. 50-113686.

37, the discharge cell is composed of three electrodes, i.e., an anode, a cathode, and a supplementary anode. The discharge between the anode and the cathode is a display discharge, and the discharge between the auxiliary anode and the cathode is an auxiliary discharge and is not observed from the outside. A cathode resistor R _K is disposed to prevent simultaneous discharge and auxiliary discharge. When the anode voltage is V _A , the cathode voltage is V _K , and the auxiliary anode voltage is V _SA , the following procedure is required to increase the display discharge.

[1] An auxiliary discharge is started by setting the auxiliary anode voltage V _SA to a high level and the cathode voltage V _K to a low level,

[2] The auxiliary discharge is stopped and the display discharge is started by making the auxiliary anode voltage V _SA low, the cathode voltage V _K high, and the anode voltage high.

In the process [2], when the auxiliary anode voltage V _SA becomes a high level, the display discharge can not be started because the auxiliary discharge is not stopped even when the cathode voltage V _K becomes low and the anode voltage V _A becomes high.

When the above-described characteristic is realized for the discharge cells, by using the positive pulse for the anode voltage V _A and the pulse for the cathode voltage V _K as the scanning signal and using the pulse for the auxiliary anode voltage V _SA as the video signal, It is possible to cause the auxiliary discharge cell on the matrix to perform the display discharge. In the case of this embodiment, consumption of electric pulses in the anode driving circuit and the auxiliary anode circuit can be reduced as compared with the prior art. The driving circuit A is used as a switching circuit of the anode driving circuit in cooperation with the positive pulse switching circuit as shown in Fig. 1 and the driving circuit B is cooperated with the negative pulse switching circuit as shown in Fig. And is used as the switching circuit of the auxiliary anode driving circuit, and the conventional push-pull type driving circuit C is used for the cathode driving. Thus, a display device capable of driving with low power consumption can be realized. The driving method described in this embodiment can be applied to a general capacitive load driving device such as a plasma display, an EL (electroluminescence) display, a vacuum fluorescent display, a piezo electric device, and the like.

FIG. 38 is a diagram showing an example of a circuit for driving several electrodes according to the present invention, in which a switching circuit is inserted between the power recovery circuit and electrodes, and recovery power is recovered through this switching circuit.

The first switching circuit 1101, the diode 1102 and the inductor 1103 are connected in series to a power supply source 1111 constituted by a capacitor element for storing charges or a power source. This series circuit serves to charge the electrodes (causing the voltage rise at the electrodes). The output terminal 1116 of the inductor is connected to a plurality of electrodes 1112 of the display elements 604, 607, 610, ..., each of which is composed of a first unidirectional switch, i.e., a diode 1104 and an FET 1105, And are respectively connected to the corresponding series circuits. The output terminal 1116 of the inductor 1103 is also connected to a switching circuit 1113 which holds the terminal voltage at the level of the high voltage power supply 1115. [ The output of the first unidirectional switch (diode 1104, FET 1105) is connected to one of several address electrodes 1112, for example, of an AC type plasma display.

On the other hand, the circuit for collecting the electric charge accumulated in the electrode 1112 includes a switching circuit 1110, a diode 1109 and an inductor 1108 and an output terminal 1117 of a series circuit connected to the electric charge supply source 1111, And is configured to be connected to a series circuit composed of a two-way switch, i.e., a diode 1107 and a FET 1106, respectively. Here, the output terminal 1117 of the inductor 1108 is also connected to the switching circuit 1114 which maintains the output voltage at the level of the low-voltage power supply (here, the ground level). The outputs of the second unidirectional switches (the diode 1107 and the FET 1106) are connected to one of the electrodes 1112 (here, the address electrode 1112 of the AC type plasma display).

Here, the current path for charging and discharging the electrodes of the display element will be described with reference to FIG. 38.

First, the current path at the time of charging the electrode will be described. Here, one of the plurality of electrodes is set to a low level (ground level). At this time, the output terminal 1116 goes down to the low level simultaneously with turning on the corresponding FET 1105. Next, when the switching circuit 1101 is turned on, the electric charge accumulated in the electric charge supply source 1111 flows through the switching circuit 1101, the diode 1102 and the inductor 1103 to the unidirectional switch (diode 1104 and FET (1105) to charge the electrodes 1112 of the display elements 604, 607, and 610. According to the principle of the power recovery circuit, the voltage of the charge supply source 1111 becomes equal to 1/2 of the voltage of the high voltage power supply V _H , and the voltage rise is caused by the resonance between the electrode functioning as the capacitive load and the inductor 1103 And becomes the high voltage level V _H at the ground level. As described above, when the electrode is charged, a charge is supplied from the charge supply source 1111 to the electrode 1112 through the inductor 1103 and the first unidirectional switch (diode 1104 and FET 1105). When the voltage of the output terminal of the inductor 1103 rises to the high voltage level V _H , the circuit 1113 which holds the terminal voltage at the level of the high voltage power supply is turned on to maintain the voltage of the terminal 1116 at the high voltage level.

If some of the electrodes are not charged, the corresponding FET 1105 is turned off. Since the first unidirectional switch includes the diode 1104, the current is not inverted from the electrode 1112 to the terminal 1116. [

Next, a current path for discharging the charge accumulated in the electrode 1112 of the display element will be described. Here, it is assumed that several of the electrodes are at a high voltage level (voltage level V _H ). At this time, when the corresponding FET 1106 is turned on, the voltage of the terminal 1117 becomes a high voltage level at the same time as the current flows from the terminal 1117 through the FET 1106 and the diode 1107.

When the switching circuit 1110 is turned on, the charge accumulated in the electrode 1112 is supplied to the charge supply source 1111 through the FET 1106, the inductor 1008, the diode 1109, and the switching circuit 1110 . The voltage of the charge 1112 is lowered to a low voltage level (ground level) by the resonance of the inductor 1108 and the electrode which is a capacitive load. At this time, the circuit 1114 for holding the electrode at the low voltage level is turned on to maintain its voltage at the low voltage level. As a result, the charge accumulated in the electrode is recovered to the charge supply source 1111 via the second unidirectional switch (FET 1106 and diode 1107) and the inductor 1108.

If it is desired to maintain the voltage of the electrode at a high voltage level (V _H level), the FET 1106 is turned off. In this case, since the second unidirectional switch includes the diode 1107, no current flows to the terminal 1117. [

Here, an example of another embodiment of the present invention will be described using FIG. FIG. 40 shows a circuit in which the first unidirectional switch and the second unidirectional switch are configured by bipolar transistors 1301 and 1302, respectively. Since FETs 1105 and 1106 have a stray diode, diodes 1104 and 1107 are required to make them unidirectional. However, since no bipolar transistor 1301 and bipolar transistors 1302 exist in the bipolar transistor 1302, a single echo can be realized by itself.

Next, another embodiment of the present invention will be described using FIG. 41 shows voltage holding circuits 1401 and 1402 holding the electrodes 1112 of the display elements 604, 607 and 610 at a high voltage level V _H and a low voltage level (ground level) And the voltage holding circuit (corresponding to the circuits 1113 and 1114 in FIG. 38) is removed in the power recovery circuit. In the operation of the circuit shown in FIG. 38, if the voltage level of the electrode does not change, one of the FET 1105 and FET 1106 is turned off. However, as described with reference to FIG. 38, the voltage levels of the terminals 1116 and 1117 instantaneously change to a low voltage level or a high voltage level. At this time, since the inverse voltage is applied to the diode 1104 or 1107, they are not conducted, and when the voltages of the terminals 1116 and 1117 are simultaneously changed, the electrode temporarily becomes a floating state. In such a floating state, the voltage of the electrode may change for some reason. In order to prevent such variations, the voltage holding circuits 1401 and 1402 are connected to the respective electrodes in the circuit configuration shown in FIG. Thus, if the voltage of the electrode does not change, the electrode can be driven at a stable operating voltage by maintaining the electrode at a low voltage level or a high voltage level.

FIG. 42 is a view showing an embodiment of the present invention in the case of controlling the inductance value. FIG. A first unidirectional switch (diode 1104 and FET 1105) and a second unidirectional switch (switching FET 1106 and diode 1107) are connected to one of the corresponding electrodes. The number of electrodes driven by the power recovery circuit varies depending on the number of the first and second unidirectional switches turned on. Therefore, in this case, the load capacity appearing in the power recovery circuit changes. At this time, since the resonance frequency generated by the inductor and the electrode changes, the fall time of the high voltage pulse applied to the electrode changes. In this case, when the present invention is applied to the address electrode of the AC type plasma display, a malfunction occurs when the rising time and the falling time of the high voltage pulse are different, for example. Therefore, the number of the first and second unidirectional switches to be turned on is detected in advance, and the inductance value of the power recovery circuit is controlled according to the number of detection thereof. FIG. 42 is a diagram showing an example of a circuit configuration for realizing such control.

In the circuit shown in Fig. 42, a plurality of series circuits (in this example, three series circuits 1501, 1502, and 1503) each composed of a switching circuit 1101, a diode 1102 and an inductor 1103 ) Are connected in parallel. A plurality of series circuits (in this example, three series circuits 1504, 1505, and 1506) each composed of a switching circuit 1110, a diode 1109, and an inductor 1108 are connected in parallel. Here, the inductance values of the inductors 1103 and 1108 are different for each parallel circuit. For example, when the three inductance values form a binary system (binary value), the inductance value of all the circuits is changed to 7 stages by turning on / off the three switch circuits 1101 or 1110 Can be controlled. Hereinafter, assuming that the total number of the plurality of electrodes 1112 is N, the number of ON unidirectional switches is set to a value closest to a multiple of N / 7, and accordingly, the inductance value is controlled. Since the resonance frequency of the inductor and the electrode is formed by the root of the product of the inductance and the capacitance, the value of the product of the inductance and the capacitance is kept substantially constant by changing the inductance value in the above-mentioned seven stages, It remains constant. Therefore, even if an arbitrary number of unidirectional switches are turned on, by detecting the ON unidirectional switches and controlling the inductance value of the power recovery circuit in accordance with the number detected as described above, the rising and falling periods of the high voltage pulse are almost A constant pulse waveform can be obtained. Although three series circuits each consisting of the switching circuit 1101, the diode 1102 and the inductor 1103 are connected in parallel in the example of FIG. 42, the tolerance region of the rising and falling periods of the high voltage pulse The number of parallel circuits is limited to three.

One embodiment of a method for controlling a unidirectional switch will be described below using FIGS. 43 and 44. FIG.

FIG. 43 is a diagram showing an example of the circuit of the control section for the FETs 1105 and 1106 in the unidirectional switch. FIG. 43 shows an example of using an N-channel MOSFET as the FETs 1105 and 1106. The resistor 1604 and the protection diode 1603 are connected between the gate and the source of the FET 1105 and the gate of the FET is constituted by a constant current source circuit composed of a resistor 1601 and a PNP transistor 1602. On the other hand, the diode 1605 is connected between the gate and the source of the FET 1106, and the gate of the FET 1106 is driven by the FET 1606.

44 shows the voltage waveforms of the respective input terminals of the circuit shown in FIG. 43 and the waveforms of the voltages applied to the electrodes. FIG. 44 (a) and FIG. 44 44 (b) shows the input voltage waveform of the second unidirectional switch (the voltage waveform of the terminal 1117 in FIG. 43), and FIG. 44 (c) A waveform of a signal input to the gate 1615 of the voltage holding circuit (1113 in FIG. 43) for holding the turning terminal 1116 at the level of the high voltage power source is shown, 43 (e) shows the waveform of the signal input to the gate 1616 of the voltage holding circuit (1114 in FIG. 43) for holding the PNP transistor (FIG. 43 (F) shows the waveform of the signal input to the gate 1613 of the FET 1606 shown in FIG. 43 It indicates the type of claim 44 (g) turning a waveform of the voltage applied to the electrode (43 ° 1112).

Next, the control method of the circuit shown in FIG. 43 is explained using the input voltage waveform, the other control voltage waveform, and the output waveform in the periods I to XIII shown in FIG. First, it is assumed that the electrode 1112 is at a low voltage level in the period I. As shown in FIG. 44 (e), in the period II, the base 1612 of the transistor 1602 shown in FIG. 43 is in a low state. At this time, the transistor 1602 is turned on to supply the current to the gate of the FET 1105 through the resistor 1601 and the transistor 1602 at the high voltage power supply V _H. As a result, a voltage is generated across the resistor 1604 between the source and the gate of the FET 1105 and the FET 1105 is turned on. Since the voltage of the electrode 1112 is set to the low voltage level in the period I and the FET 1105 is turned on in the period II as shown in Fig. 44 (a), the voltage waveform of the terminal 1116 becomes the voltage waveform of the period II And is instantaneously lowered to the low voltage level at the start of the start. Next, since the power recovery circuit (switching circuit 1101 in FIG. 38) is turned on in period II, the voltage of the terminal 1116 rises in a sinusoidal manner. Here, the voltage of the input terminal (electrode) 1112 also rises in a sinusoidal manner as the diode 1104 and the FET 1105 are turned on.

On the other hand, as shown in FIG. 44 (f), the input signal of the gate 1613 of the FET 1606 becomes High in the period II. At this time, the FET 1606 is turned on and the voltage of the gate of the FET 1106 is lowered to a low voltage level. Here, as shown in FIG. 44 (b), since the voltage waveform of the terminal 1117 instantaneously rises to a high voltage level (to be described later) and then descends in a sinusoidal manner, The voltage is not generated, and the voltage of the gate of the FET 1106 also falls simultaneously, so that the FET 1106 is turned off.

Next, in the period III, since the voltage holding circuits 1113 and 1114 are turned on, the voltage of the terminal 1116 is held at the high voltage level V _H and the voltage of the terminal 1117 is held at the low voltage level. Here, in the period III, the FET 1105 is turned on and the FET 1106 is turned off, so that the voltage of the electrode 1112 becomes the high voltage level V _H.

As shown in FIG. 44 (a), in the period IV, the voltage of the terminal 1116 once falls to the low voltage level. However, since the reverse voltage is applied to the diode 1104, The charges stored in the electrode 1112 do not flow reversely through the capacitor 1116. Although the voltage of the terminal 1117 once rises to a high voltage level as shown in FIG. 44 (b), since the FET 1106 is turned off, no current flows from the electrode 1112 to the terminal 1117 as well. As described above, in the period IV, the electrode is in the floating state, and in the period III, the voltage becomes the high voltage level, so that the voltage of this electrode is maintained in the period IV.

The operation in the period V is the same as in the period III, and the voltage of the electrode is maintained at the high voltage level.

Next, in the period IV, the signal of the base 1612 of the transistor 1602 goes high, so that the transistor 1602 is turned off and the gate of the FET 1105 is turned off The current does not flow through. Therefore, since no current flows through the resistor 1604, the voltage of the gate of the FET 1105 becomes equal to the source thereof, and the FET 1105 is turned off. Also, as shown in FIG. 44 (f), the signal of the gate 1613 of the FET 1606 in the period VI becomes low. Thus, the FET 1606 is turned off. Here, as shown in FIG. 44 (b), when the voltage of the terminal 1117 rises to a high voltage level and then to a sinusoidal manner, the diode 1107 is turned on. At this time, the source voltage of the FET 1106 also falls in a sinusoidal manner. Here, a voltage is generated between the gate and the source of the FET 1106 by the diode 1605, and the FET 1106 is turned on. Therefore, since the electric charge accumulated in the electrode 1112 at the high voltage level in the period V flows out through the FET 1106 and the diode 1107 in the period VI, the electric charge of the electrode 1112 is lowered to the low voltage level in the sine-wave manner .

Next, in the period VII, the FET 1105 is turned off and a voltage is generated by the diode 1605 between the source and the gate of the FET 1106, so that the FET 1106 is turned on and the voltage of the electrode 1112 Is maintained at the low voltage level.

The operations in periods IX, X, and XI are the same as those in Periods II, III, VI, and VII, and their explanation is omitted.

Next, in the period XII, the voltage of the terminal 1116 is once lowered to the low voltage level and then raised to the high voltage level in the sine-wave manner. However, since the FET 1105 is turned off, no current flows to the electrode. Also, although the voltage of the terminal 1117 is once lowered to a high voltage level and lowered in a sinusoidal manner, a current does not flow from the terminal 1117 to the electrode because an inversion voltage is applied to the diode 1107. [ Therefore, in the period XII, the electrode is in the floating state, and in the period XI, the voltage of the electrode becomes the low voltage level, so that this low voltage is maintained in the electrode.

Since the operation in the period XIII is the same as in the period XII, its explanation is omitted.

The voltages of the terminals 1116 and 1117 are instantaneously set to the high voltage level or the low voltage level in the periods II, IV, VI, VII, X, and XII. This is because the charge stored in the electrode is supplied to the terminal 1116 or 1117 when one of the first unidirectional switch and the second unidirectional switch connected to several other electrodes is turned on. If all the unidirectional switches are off, this instantaneous deformation does not occur, but the desired voltage can never be obtained at the electrodes.

The above-described gate control circuits of the FETs 1105 and 1106 shown in FIG. 43 are merely examples, and the present invention is not limited to the gate drive circuit shown in FIG. For example, a gate control circuit may be formed using a level shift circuit, a photocoupler, or the like.

As described above, since the pulse width applied to the electrodes can be arbitrarily controlled, the switching circuit according to the present invention can perform power recovery with low power consumption and simple configuration.

In addition, a driving method and a driving circuit for driving a PDP (plasma display device) according to another embodiment of the present invention and a display device using the same will be described in detail with reference to the accompanying drawings.

First, the structure of the PDP will be described using FIGS. 52 and 53. FIG. FIG. 52 is an exploded perspective view showing the structure of a PDP. Reference numeral 800 denotes an X electrode, 801 denotes a Y electrode, 802 denotes an address electrode (A electrode), 803 denotes ribs, 804, 805 810 is a glass face plate, 811 is a substrate, and 812 is a dielectric layer. In FIG. 8A and FIG. 8B, reference numerals 806 and 806 denote R, G and B phosphors, respectively.

In the same figure, the structure of the PDP is such that a discharge space and an electrode are formed between two glass face plates and a gas is sealed in the discharge space, thereby generating a discharge and causing the phosphor coated on the inner wall surface in the discharge space to emit light. Therefore, since the PDP is a self-luminous display element, it has a feature that the quality of an image is high and a visible region is wide. In addition, since the structure is simple, it is suitable for a large-sized display, and is particularly suitable for use in a large display device.

52, two transparent electrodes (that is, an X electrode 800 and a Y electrode 801) are formed in parallel with each other on a glass face plate 810. These electrodes 800 and 801 are formed of two It is a medium-sized group. That is, bus electrodes are formed on the transparent electrodes 800 and 801 to reduce the resistance value of the electrodes. A dielectric layer 812 of MgO or the like is formed on these two pairs of electrodes. Therefore, this PDP is a surface-discharge type AC type PDP.

On the other hand, a rib 803 for forming a discharge space is formed on the substrate 811 by sandblasting or the like, and address electrodes (A electrodes) 802, R, G, and B phosphors 804, 805, and 806 are formed.

The glass face plate 810 and the substrate 811 are airtightly sealed and one or more gases including Xe, Ne, Ar, Kr, and He are mixed and sealed. Here, in order to excite the phosphors 804, 805, and 806, ultraviolet light emission of Xe atoms is generally used, so that Xe gas is always contained.

The discharge for display is performed by alternately applying a pulse voltage between the X electrode 800 and the Y electrode 801. As a result, a discharge occurs between these two electrodes 800 and 801 , Xe atoms are excited by electrons in the plasma. When this excited Xe atom transitions to the grounded state, ultraviolet rays are generated. The ultraviolet rays excite the phosphors 804, 805, and 806 to emit three primary colors, i.e., R, G, and B.

FIG. 53 is a view showing the wiring of the electrodes of the PDP 900 shown in FIG. 52.

In the same figure, an X electrode 800 and a Y electrode 801 shown in FIG. 52 are arranged in parallel in the PDP 900, and electrode terminals protrude from both the left and right sides of the PDP 900. The A electrodes 802 are arranged on both the upper and lower surfaces of the PDP 900, and the electrode terminals are alternately projected one above the other in the upper and lower directions because of the large number of electrodes. A discharge cell is formed at a junction of the X electrode 800, the Y electrode 801, and the A electrode 802.

Hereinafter, the set of all the discharge cells of this PDP will be referred to as " set ". On the other hand, the Y electrode 801 and the X electrode 800 are connected in common to the discharge cells arranged in the horizontal direction of the PDP 900, and the set of these discharge cells in the horizontal direction is referred to as " do. According to the structure of the PDP 900, it is not necessary that the Y electrodes are disposed in common in only one horizontal cell, and therefore the Y electrode 801 is connected to the electrode as a part of the middle set which constitutes a large set.

The Y electrode 801 can not be commonly connected to all of the cell sets because the pulse voltage of the scan function is applied to the middle set of the cells, Can be connected in common with all sets.

FIG. 45 is a diagram showing a driving signal waveform in the first embodiment of the driving method of the PDP according to the present invention. FIG.

In order to drive the PDP 900, both the light function and the display function must be executed. The write function is to form a charge on the wall surface of the selected discharge cell, and display only the discharge cells selected by the next display function. Therefore, the write function must be executed individually for all the discharge cells, and therefore, the scan function is performed for a set of cells (Y electrodes) of the PDP 900. [ The scanning function is to apply the pulse voltage of the scanning function to the middle set of cells and perform the writing function within this period. On the other hand, in a set of cells, the pulse voltage of the scanning function can be applied at different times to make a time lag. The selection of each discharge cell in the middle sum sum is distinguished by different A electrodes.

FIG. 45 shows a driving signal waveform of each electrode when one field of a signal is divided into 10 subfields and display of the divided 10 subfields is performed. Here, only one A electrode 802 is shown. The write data to be applied to the A electrode 802 is numbered from 1 to 10 indicating the number of subfields.

45 also applies a first pulse voltage (105A) of the scan function to the electrodes Y _l, one of the Y electrode 801 in the set of the cells in the. The pulse voltage 105A of the scan function coincides in time with the data corresponding to the first subfield of the A electrode 802, for example. Thus, Y _l pulse voltage (105A) of the scanning function of the electrode performs a write function of the first subfield. Is then applied to the other one of Y ₂ to Y electrodes of the electrode 801 has, like the pulse voltage (105A) of the scan function corresponding to one of the second subfield data in the A electrode 802.

On the other hand, the pulse voltage 107A of the scanning function is applied to the Yk electrode (one of the Y electrodes) which is one of the set of other cells, and this is applied at a time corresponding to the fifth subfield of the A electrode . The pulse voltage 107A applied to the Yk + 1 electrode which is the Y electrode next to the Yk electrode is also applied at the time corresponding to the seventh subfield of the A electrode 802. [ In addition, another one of the Y electrode _l in the other of the set of cells, a pulse voltage (108A), for example, the A electrode is applied to the time corresponding to the seventh subfield. A pulse voltage 108A of the scan function is similarly applied to the electrode of Y1 + 1 at a time corresponding to the seventh subfield of the A electrode.

In this way, while performing the scan function of the first sub-field in a set of arbitrary cells, the scan function of another sub-field is executed in a set of other cells. The pulse voltage of the scan function of the same subfield is scanned while jumping the write data applied to the A electrode 802 by the number of the subfields.

In Fig. 45, a pulse voltage of the display function is applied after the pulse voltage of the scan function. That is, it applies a pulse voltage (109A) of the display after the voltage pulse Y _l (105A) of the scanning function of the electrode. Only the example in which the pulse voltage 109A of the display function is only one is shown. A periodic pulse voltage is applied to the common X electrode (800).

Next, the operation for display will be described.

First, Y _l is applied to the pulse (105A) of the scan function to the electrode 1, if the data corresponding to the second sub-field is maintained at a write voltage (high voltage), Y _l and A electrodes of the A electrode 802 ( 802, so that the ions adhere to the Y ₁ electrode. Next, the X electrode 800 becomes a low voltage by the pulse voltage 13A, and the Y ₁ electrode is at a high voltage and the Y ₁ electrode is attached with ions. Therefore, the pulse voltage of the X electrode 800 Starts discharging. By this discharge, ions are attached to the X electrode 800 and electrons are attached to the Y ₁ electrode, respectively. Next, the Y electrode _l by a pulse (109A) of the display electrode of Y _l and up low potential, so the X electrode 800 is a high voltage pulse (109A) of the display is discharged in accordance with the memory effect. This discharge causes electrons to adhere to the X electrode 800 and ions to adhere to the Y ₁ electrode, respectively. Next, the pulse voltage of the X electrode also discharges. Next, the pulse voltage of the display function at Y _l is cut off. Therefore, since there is no memory effect, the pulse voltage 115A of the X electrode 800 is not discharged. That is, the display discharge is interrupted by blocking the pulse of the display function of the Y _l electrode. The phosphor within the discharge cell is excited by generating a pulse-like discharge between the X electrode 800 and the Y ₁ electrode to perform light emission display.

If it does not fire, the A electrode 802 when the voltage pulse (105A) of the scanning function of the Y electrode is _l is applied to the high voltage pulse. At this time, no discharge occurs between the Y ₁ electrode and the A electrode 802, so that ions do not adhere to the Y ₁ electrode. Therefore, even if the pulse voltage of the next X electrode 800 is applied, there is no memory effect, and therefore, no discharge occurs. Similarly, the pulse voltage 109A of the Y1 electrode and the pulse voltage 114A of the X electrode 800 are not discharged. A discharge for display does not occur between the X electrode 800 and the Y ₁ electrode, so that the phosphor in the discharge cell is not excited and the light emission display is not performed.

The control of the above-described light-emitting display is carried out in a set of all the cells, in the set of one cell, by the number of the subfields, and in accordance with the scan of the sum of the plurality of cells.

Next, a method of the priming function will be described using FIG. 45.

Y _l electrodes on before applying a pulse voltage (105A) of the scanning function to pre-attach the ions to the A electrode 802 and reduce the write voltage, by forming a space-charge to some extent in advance in the discharge cells to facilitate the discharge of the light The priming function is executed.

For this, (is the potential of the low duty refers to high and pulse than other potential that defines the pulse voltage) defined pulse voltage (102A) in the Y _l electrodes periodic pulse voltage (111A) and the same time of the X electrode 800 And a large potential difference is generated between the X electrode 800 and the Y ₁ electrode to discharge the same. Immediately after the priming function is terminated, the X electrode 800 and the Y ₁ electrode are at the same potential, and self erase discharge occurs. Here, the term self-erase discharge means that a voltage is generated and discharged by a charge formed on two electrodes by discharge after a pulse voltage is removed.

Due to the magnetic erasure discharge, the charges on the X electrode 800 and the Y ₁ electrode are erased, and the electric charge floating in the space becomes a potential difference between the Y ₁ electrode and the X electrode 800 and the electric potential of the A electrode 802, (802). Therefore, since the ions are attached to the A electrode 802 by this priming function, the pulse voltage applied to the A electrode 802 for the write function can be lowered.

Next, in Fig. 45, description will be given of execution of the auxiliary discharge function before applying the pulse voltage of the priming function.

The function by the auxiliary discharge, and applies a pulse voltage (101) of the auxiliary discharge function to electrodes Y _l to lower the voltage of the function of the priming pulse. This is because the discharge of the display function is always terminated by the pulse voltage of the X electrode 800, so that the same pulse voltage as the display function is applied to the pulse voltage 102A of the priming function using the residual wall charge of the display function of the previous sub- Y _l is to discharge by applying to the electrode. By this auxiliary discharge functions were attached to the ion electrode Y _l can execute the function of the priming discharge at a low voltage.

Next to the use of claim 45 will be explained with respect to light of the second sub-field to be applied to the Y electrode _l.

Applying a first pulse voltage (101A) of the auxiliary discharge function of the second subfield, the priming function of the pulse voltage (102A), the scanning function of the pulse voltage (105A), and display pulse voltage (109A) of which is applied to the Y _l electrodes The series of control of the first sub-field is terminated.

Next, in the second subfield, the pulse voltage 103A of the same auxiliary discharge function, the pulse voltage 104A of the priming function, the pulse voltage 106A of the scanning function, and the pulse voltage 109A of the display function are applied. Here, the pulse voltage 106A of the scan function is applied at a time corresponding to the second subfield of the write of the A electrode 802. [ However, the order number of the subfields does not necessarily have to be from 1 to 10, and during the period between the pulse voltage 105A of the scanning function of any subfield and the scanning function pulse of the next subfield,

k? n + p (1? p? k-1) (where k, n,

The pulse voltage of the light is applied as many times as the number of pulses. Here, k is the number of subfields, and n is an arbitrary integer. Thereby, the pulse voltage of the scanning function of the other subfields is not applied at the same time across all the Y electrodes 801. [

The periodic pulse voltage of the X electrode 800 shown in FIG. 45 does not overlap with the write pulse applied to the A electrode 802 in a temporal manner. In addition, Y _l is not the pulse voltage of the pulse voltage, and the priming feature of a display function to be applied to the electrode is not superimposed to the light pulse and the time is applied to the A electrode 802. Further, by setting the periodic pulse voltage 11 IA of the X electrode 800 and the pulse voltage 102A having the priming function applied to the Y ₁ electrode to the polarities opposite to each other in FIG. 45, a higher potential difference can be obtained have.

54 shows the scanning method of the first embodiment, in which the abscissa represents the time of two fields, and the ordinate represents the Y electrode of the center of the cell. In the drawing, the oblique lines show the application time of the scan function pulse voltage of the subfield to the set of each cell. In it the number of the number of subfields to 10, and the respective sub-fields by _{b 0, b l, b 2} , ‥‥‥, b 9.

As shown in FIG. 54, in order to scan one sub-field, approximately one field is required until the end of the set of all the cells. Also, it can be seen that scanning of a plurality of subfields is simultaneously performed when an arbitrary time is fixed. However, as shown in FIG. 45, the pulse voltages of the scan functions of other subfields are not overlapped temporally.

After the pulse voltage of the scan function, a pulse voltage of a display function is applied, and the number thereof is generally different for each subfield. Therefore, as shown in Fig. 54, it is general that the time interval between the pulse voltages of the scan function is different for each subfield in a set of one cell.

FIG. 55 is a diagram showing a driving signal waveform in the second embodiment of the driving method of the PDP according to the present invention, in which two X electrodes of X ₁ and X ₂ and two Y electrodes of Y ₁ and Y ₂ And a portion corresponding to FIG. 45 is denoted by the same reference numeral.

In FIG. 45, the periodic pulse voltage applied to the X electrode 800 is set to be the same in all sets of all cells, but in FIG. 55, the X electrodes are independent in the set of each cell, The presence or absence of a voltage is different. Here, for example, there is one X electrode and one Y electrode, such as electrode and the X _l Y _l electrodes, X ₂ and Y ₂ electrode is a part of the electrode set of the same cell.

In the same time with pulse voltage (102A) of the Y _l-priming function of the electrode, a pulse voltage (1100A) portion for X _l electrodes (not called negative pulse voltage means a duty is low pulse voltage than the other potential is low the pulse voltage) is applied, and , the front and rear of the display pulse voltage (109A) for the Y electrodes, _l is the only voltage pulses that may be emitted to the electrodes X _l (pulse voltage 1101). The pulse voltages of the plurality of X electrodes 800 are sequentially applied for a delay time equal to the delay time of the pulse voltage of the scan function for the plurality of Y electrodes 801.

56 shows a driving signal waveform in the third embodiment of the driving method of the PDP according to the present invention, which shows driving signal waveforms of the X electrode 800 and the Y ₁ to Y ₆ electrodes, The same reference numerals are given to parts corresponding to the figures.

In the first embodiment shown in FIG. 45, the pulse 102A of the priming function and the pulse voltage of the auxiliary discharge function are sequentially and temporally shifted from each other in accordance with the scanning order of the cells in the center of gravity. In the embodiment shown in FIG. 56 The pulse voltage of the priming function and the pulse voltage of the auxiliary discharge function are applied at the same time at least in the middle set of the cells, so that only the pulse voltage of the scan function deviates. This makes it possible to commonly use a circuit for generating pulses of priming function among a plurality of sets of cells, thereby reducing the number of circuits.

FIG. 57 is a view showing a driving signal waveform in the fourth embodiment of the driving method of the PDP according to the present invention, showing the driving signal waveforms of the X electrode 800 and the Y ₁ to Y ₃ electrodes, The same reference numerals are given to parts corresponding to the figures.

In the same figure, the pulse voltage of the scan function of the overlapping sum of one cell is periodically applied until the pulse voltage of the next priming function is applied without interruption. Instead, a pulse voltage 1300 of an erase function for stopping the display discharge is applied. This serves to distinguish wall charges by stopping discharge before wall charges are formed by pulses having a narrow pulse width, and neutralizing charges by floating them in the spaces of the discharge cells. Then, by distinguishing the wall charges, the memory effect is lost and the discharge for display is stopped.

FIG. 58 is a diagram showing the distribution of the application time of the pulse voltage of the display function of the subfield in each of the above embodiments. FIG.

In order to display an image, it is necessary to control the gradation. For this purpose, the gradation is controlled by changing the light emission luminance of each subfield and controlling the presence or absence of light emission thereof. In general, by forming the emission time width of each subfield (i.e., the brightness of the subfield) in the binary system, the maximum gradation can be displayed with as few subfields as possible.

However, when a moving picture is displayed, a so-called dynamic false contour is generated. Therefore, the emission time width of all the subfields is not set to be a binary system, only the lower subfield is set to be a binary system, It is common not to use the system as a whole. In FIG. 58, the emission time widths in the lower six subfields are set to be binary systems, and the emission time widths in the upper four subfields are made equal. Then, one pair (two) of the upper four subfields are arranged in the front and the back of the first field, respectively. In FIG. 58, it is possible to realize 256 gradations in 10 subfields.

FIG. 59 shows another gradation display method in which the number of subfields is 7, and only the emission time width of the lower three subfields is a binary system, and the emission time widths of the upper four subfields are all The same thing. One pair (two) of the upper four subfields are arranged in the front and rear of the first field, respectively. In this case, the gradation of 40 can be realized.

Fig. 60 is a diagram showing a first embodiment of a display device of a PDP according to the present invention, in which 1600A is a Y power recovery circuit, 1601A is a pulse voltage distribution circuit, 1602A is an X power recovery circuit, Reference numeral 1603A denotes an A driver circuit, 1604A denotes a shift register, 1605A denotes a display data signal generating circuit, and 1606A denotes a control signal generating circuit. . In the same figure, each X electrode of the PDP is directly connected to the X power recovery circuit 1602A in common. In this X power recovery circuit 1602A, a periodic pulse voltage is generated. Each of the Y electrodes of the cells in the center of the cell is independently connected to the pulse voltage distributing circuit 1601A and these are connected in common to the Y power recovering circuit 1600A which is a pulse voltage generating circuit of display function. The X power recovery circuit 1602A, the pulse voltage distribution circuit 1601A, and the Y power recovery circuit 1600A are controlled by a control signal generated by the control signal generation circuit 1606A.

On the other hand, the A electrode 802 is driven by the A driver circuit 1603A connected to the upper and lower terminals of the PDP panel 900, and the write signal is generated as a data signal according to the image in the display data signal generating circuit 1605A Parallel-converted and supplied to the A driver circuit 1603A.

FIG. 61 is a circuit diagram showing an embodiment of the Y-power recovery circuit 1600A and the pulse voltage distribution circuit 1601A in FIG. 60. Reference numerals 1700 and 1701 denote FETs, 1717 is a diode, 1716 is a capacitor, 1717 is a Y power recovery circuit 1600A, 1718 is a FET, 1709 is a holding circuit FET, 1710 to 1715 are a capacitor, And a part of the pulse voltage distribution circuit 1601A.

In the same figure, the Y power recovery circuit portion 1717 includes a capacitor 1716, two unidirectional switch circuits, FET 1700 and diode 1710, FET 1701 and diode 1711 and inductance 1702, And 1703, respectively.

The inductor 1702 and the Y electrode 801 are electrically connected to each other by supplying charges from the capacitor 1716 to the Y electrode 801 by the resonance of the capacitive load of the inductor 1702 and the Y electrode 801, The charge is again returned to the capacitor 1716 by the resonance of the capacitive load and the voltage of the Y electrode 801 is lowered. By applying a pulse voltage to the Y electrode 801 in this manner, charges are supplied from the capacitor 1716 and are recovered to the capacitor 1716, thereby realizing a drive circuit with a low power consumption.

On the other hand, the pulse voltage distribution circuit portion 1718 distributes the pulse voltage of the display function by the diode 1712, the FET 1704, the diode 1713 and the FET 1705, and supplies the pulse voltage of the scan function and the pulse voltage of the priming function The circuit for applying the pulse voltage includes a FET 1706 as a bi-directional switching circuit, a diode 1714 and a FET 1708, a diode 1715 connected in parallel, a holding circuit FET 1709 as a high voltage source, And a holding circuit FET 1707.

Next, the operation of the above-described embodiment will be described using the voltage waveform diagram of FIG. The voltage waveform applied to one of the Y electrodes 801 in the same drawing is shown, and the following description is made by dividing it into 11 periods I to IX.

Period I: The circuit output becomes VY ₂ level, and at that time, both FETs 1706 and 1708 are turned on (turned on). Here, when a bi-directional switch is connected to the power source of the voltage VY ₂ and a pulse voltage is applied to the other electrode, a voltage is leaked in due to the capacitive coupling in the panel, and this bidirectional switch voltage is discharged to the power source of VY ₂ do.

Period II: Pulse voltage of auxiliary discharge function, FET 1707 is turned on and maintained at a low voltage level.

Period Ⅲ: Same as Period I.

Period Ⅳ: a pulse voltage of the priming feature is a FET (1709) is held on the output voltage VY to _1.

Period V: Same as Period I.

Period VI: Pulse voltage of scan function, FET 1707 is turned on and maintained at a low voltage level.

Period VII: Period I Contingency Day.

Period VIII: Fall period of the waveform due to application of the display pulse voltage. The FET 1701 of the Y power recovery circuit portion 1717 and the FET 1705 of the pulse voltage distribution circuit portion 1718 are turned on and the inductance 1703 and the resonance of the capacitive load of the Y electrode 801 The potential of the electrode 801 goes down to a low voltage level sinusoidally. At this time, the charge accumulated in the Y electrode 801 is collected and accumulated in the capacitor element 1716 of the Y power recovery circuit portion 1717.

Period IX: The FET 1707 is turned on by keeping the pulse voltage of the display function at the low voltage level.

Period X is a rising period of the pulse voltage of the display function and the FET 1700 of the Y power recovery circuit portion 1717 and the FET 1704 of the pulse voltage distribution circuit portion 1718 are turned on. As a result, charge is supplied from the capacitor 1716 to the Y electrode 801 by the resonance of the capacitive load of the inductor 1702 and the Y electrode 801, and the potential rises sinusoidally up to the level VY ₂ .

Period XI: The period during which the pulse voltage of the display function is maintained at the level of the VY ₂ power supply, and is the same as the period I.

The subsequent application of the pulse voltage of the display function is a repetition of the operations in the periods VIII-XI. In addition, here, by providing a 1 has been described only for the waveforms of the two Y _l electrodes, a pulse voltage division circuit portion 1718 of the set of the cell, each in a set (Y electrode) of the respective cells, 45 It is possible to generate a pulse voltage to be applied to a set of other cells as shown in Fig. One or a plurality of Y power recovery circuits 1600A (FIG. 60) may be provided in the display device of the PDP.

FIG. 63 is a circuit configuration diagram showing another embodiment of the Y power recovery circuit 1600A and the pulse voltage distribution circuit 1601A shown in FIG. 60. Reference numeral 1901 denotes a holding circuit FET, and 1902 to 1904 1910 is a diode, 1909 is a FET, 1907 is a diode, 1907 is a diode, 1908 to 1910 are FET, 1911 is a diode, 1912 is a FET, 1913 is a diode, 1914 to 1916 denote FETs, 1917 denotes a diode, 1918 denotes a FET, 1919 denotes a diode, 1920 to 1922 denotes an FET, 1923 denotes a diode, 1924 denotes a capacitor, 1925 and 1926 are FETs and 1927 is a portion of the Y power recovery circuit 1600A and 1928 and 1929 are 1930 and 1930 are three electrodes Y ₁ and Y ₂ of the Y electrode 801, And Y ₃ , and the same reference numerals are given to portions corresponding to FIG. 61, and redundant explanations thereof are omitted.

This embodiment is different from that shown in FIG. 61 in that the holding circuit FET 1901 and the FET (not shown) are provided in the Y power recovery circuit portion 1727 in order to maintain the power supply voltage VY ₂ and the low voltage level (ground level) The FET 1909 and the FET 1904 are provided and the FET 1909, 1915, and 1921 are commonly used as the circuit for applying the signal of the voltage level VY ₁ or VY ₂ have.

Next, the operation of the above-described embodiment is divided into periods I to XIII using the voltage waveform diagram of FIG. 64. FIG. However, the voltage is so applied pulse voltage time is different, and applying a pulse voltage operation of the distribution circuit (1929) for applying a voltage waveform to the Y ₂ electrode in Y _l, Y ₃ electrode according to jungjip agreement Y electrode 801 of the cell Described in consideration of the waveform.

Period I: The FET 1915 is turned on. In this period I, the Y power recovery circuit portion 1927 operates because the auxiliary discharge function pulse voltage is applied to the Y ₁ electrode. However, the terminal (FET 1901) to which the pulse voltage of the priming function is applied is the power supply voltage VY ₂ .

Period II: FET 1915 is turned on. In this period II, since the pulse voltage of the scan function is applied to the Y electrode of the middle sum of one cell during the write period and the write data pulse voltage is applied to the A electrode, there is a voltage that flows into the Y ₂ electrode, And the FET 1926 are turned on, it is possible to emit the inflow voltage.

Period III: FETs 1901, 1912, 1914, and 1903 are turned on. In this period III, a periodic pulse voltage 2000 is applied to the X electrode and a pulse voltage 10A2 of the priming function is applied to the Y ₁ electrode. Therefore, the terminal (FET 1901) to which the pulse voltage 102A of the priming function is applied is raised to VY ₁ , and the FET 1915 is turned off. The introduction of the pulse voltage from the X electrode 800 can turn on the FETs 1901, 1912, 1914, and 1903 to conduct and discharge the FET 1902 in both directions with the power source of the voltage VY ₂ .

Period IV: Same as Period II.

Period V: During this period V, the auxiliary discharge function pulse voltage 101A is applied. When the voltage waveform is lowered, the FETs 1701 and 1914 are turned on. When this voltage waveform falls, the FET 1904 turns on do. When the voltage waveform rises, the FETs 1700 and 1912 are turned on. Alternatively, the FET 1916 may be turned on without operating the Y power recovery circuit portion 1927.

Period Ⅵ: Same as Period Ⅱ.

Period VII: FETs 1925 and 1915 are turned on. FET (1925) for generating a pulse voltage (102A) of the priming function is in synchronization with a periodic pulse voltage of the X electrode 800 are always on, the VY ₁ by controlling the on / off state of the FET (1915) A voltage pulse is selectively applied to the Y electrode 801. [

Period VIII: Same as Period II.

Period Ⅸ: Same as Periods I, II, and III.

Period X: The FET 1916 is turned on. In this period X, the pulse voltage 105A of the scanning function is applied, and the Y power recovery circuit portion 1927 is not operated.

Period XI: FET 1915 is turned on.

Period XII: Same as Period III.

Period XIII: FET 1915 is turned on.

Period X IV: Same as period V.

Period XV: Same as Periods II, III, and IV.

FIG. 65 is a diagram showing one embodiment of the X power recovery circuit 1602A shown in FIG. 60, wherein reference numeral 2100 denotes an FET, reference numeral 2101 denotes a diode, reference numeral 2102 denotes an inductor, reference numeral 2103 denotes a diode 2104 to 2106 are FETs, 2107 is an output voltage, and 2108 is a capacitor.

In the same figure, the configuration of this specific example is basically the same as the Y-power recovery circuit portion 1717 shown in FIG. 61, except that the inductors 2102 are commonly connected to the inductors 1702 and 1703, Is different.

Next, the operation of the above-described embodiment will be described with reference to FIG. 66 showing the output voltage waveform.

Here, in the steady state, the capacitor 2108 charges the electric charge with a potential of Vx / 2. In the period I (FIG. 66), the FET 2105 is turned on and the output voltage 2107 is held at the voltage V _X. In the next period II, the FET 2104 is turned on, and the output voltage 2107 is lowered to 0V by the resonance of the capacitive load of the inductor 2102 and the X electrode 800. In the next period III, the FET 2106 is turned on, and the output voltage 2107 is maintained at 0V. In the next period IV, the FET 2100 turns on, and the output voltage 2107 rises to the voltage Vx by the resonance of the inductive load of the inductor 2102 and the X electrode 800. In the next period V, the FET 2105 is turned on, and the output voltage is maintained at the voltage Vx.

As described above, in the X electrode 800, the periodic pulse voltage is repeated in the above procedure. In period II, the charge accumulated in the X electrode 800 is recovered by the capacitor 2108, and the charge is supplied from the capacitor 2108 to the X electrode 800 in the period IV. Therefore, the capacitor 2108 supplies the charge necessary for raising or lowering the voltage of the X electrode, thereby realizing a drive circuit with low power consumption.

FIG. 67 is a circuit configuration diagram showing one specific example of the A driver circuit 1603 for one A electrode 802 shown in FIG. 60, and reference numerals 2300 and 2301 denote FETs.

In Fig. 67, this specific example has a so-called push-pull circuit configuration, and the operation of this specific example will be described with reference to Fig. 68 showing its output waveform.

In the period I of FIG. 68, the FET 2301 is turned on to output a voltage of 0V. In the next period II, the FET 2300 is turned on to output the voltage V _A. In the next period III, the FET 2301 is turned on again to output a voltage of 0V again.

As described above, the FETs 2301 and 2300 are alternately turned on / off to output a pulse voltage corresponding to the data signal. When the FETs 2300 and 2301 are turned on at the same time, the circuit is broken.

FIG. 69 is a block diagram showing the main part of the second embodiment of the display device of the PDP according to the present invention, wherein reference numeral 2500 denotes a pulse voltage distribution circuit, and the same reference numerals are given to portions corresponding to FIG. It is omitted.

In the same figure, each of the X electrodes 800 of the PDP 900 is independent from one set of cells (that is, not commonly connected by a conductor as shown in FIG. 60) Each X electrode 800 is driven by the X power recovery circuit 1602A via the pulse voltage distributing circuit 2500, and the pulse voltage applied to the X electrode due to a set of cells is shifted in terms of time.

70 shows a circuit configuration diagram showing one specific example of the X power recovery circuit 1602A and the pulse voltage distribution circuit 2500 shown in FIG. 69, wherein 2600 is a FET, 2602 is a diode, 2601 are FETs, and parts corresponding to those in FIG. 65 are denoted by the same reference numerals, and redundant description is omitted.

In the same figure, the specific example shown in FIG. 65 is used as the X power recovery circuit 1602A. The pulse voltage distributing circuit 2500 of each X electrode 800 has the same circuit configuration and is composed of FETs 2600 and 2601 and a diode 2602. [

Next, the operation of this specific example will be described with reference to FIG. 71 showing the voltage waveforms of the respective portions of FIG. 70, but the operation of the X power recovery circuit 1602A is already described using FIG. 65 and FIG. 66 And D ₁ , D ₂ and D ₃ are input voltage waveforms of the FET 2670 of each pulse voltage distribution circuit 2500 and X ₁ , X ₂ and X ₃ are the input voltage waveforms of the respective pulse voltage distribution circuits 2500 Output waveform.

The output waveform 2107 consists of a periodic pulse voltage 2700. In order to stop one of the periodic pulse voltages 2700 by the pulse voltage distributing circuit 2500, the gate of the FET 2601 is supplied with a control pulse in synchronization with the fall of the periodic pulse voltage 2700, (2701). The application of the control pulse signal 2701 turns on the FET 2601 and the gate of the FET 2600 goes down to 0V at the same time as the periodic pulse 2700 falls. Therefore, the voltage between the gate and the source of the FET 2600 becomes 0V, and the FET 2600 is turned off. The periodic pulse voltage 2700 is cut off when the FET 2600 is turned off and the pulse voltage 2701 is not applied to the output waveform Xi (i = 1, 2, 3, ..., n).

On the other hand, the gate of the FET 2601 is set to 0V in order to pass the pulse voltage 2770 by the pulse voltage distributing circuit 2500. Then, the FET (2601) is off, and therefore the pulse voltage is 2700 V in the voltage level down to 0V _X goes down from the source of the FET (2600), the potential V _X to 0V. At this time, a voltage is generated in the diode 2602, and a voltage difference is generated between the gate and the source of the FET 2600, thereby turning on the FET 2600. When the FET is turned on, a periodic pulse voltage 2700 is applied to the X electrode 800 through the FET 2600.

FIG. 72 is a view showing a configuration of a television display device as one application example of a display device of a PDP according to the present invention. FIG.

In the same figure, the television display device 2803 uses the display device of the PDP according to the present invention. By receiving the broadcast wave signal from the antenna 2800 and tuning a desired channel by the tuner 2802, The video signal and the audio signal of this channel are supplied to the television display device 2803.

According to this configuration, television display with high luminance and high luminance and low power consumption can be realized by using the display device according to the present invention.

FIG. 73 is a diagram showing a configuration of a data monitor apparatus as another application example of the display apparatus of the PDP according to the present invention.

In the same figure, the data monitor 2901 uses a display device of the PDP according to the present invention, and outputs a data signal from a personal computer (also referred to as PC) 2900 to a data monitor 2901 . The data monitor device 2901 receives this signal and displays a data image such as an image / character or a graph. Also in this application example, since the display device according to the present invention is used, display with high luminous efficiency, high brightness, and low power consumption can be realized.

FIG. 74 is a view showing a configuration of a television monitor apparatus as another example of the display apparatus of the PDP according to the present invention. FIG.

In the same figure, the television monitor 3001 uses a display device of the PDP according to the present invention. The camera 3000 outputs a video signal to the television monitor 3001. The television monitor 3001 receives the video signal and displays an image captured by the camera 3000. [ Also in this application, since the display device according to the present invention is used, display with high luminous efficiency, high brightness, and low power consumption can be realized.

FIG. 75 is a view showing a configuration of a video display device used in a public place as another example of a display device of a PDP according to the present invention.

In the same figure, reference numeral 3100 denotes an image processing apparatus for displaying an image, and reference numeral 3101 denotes a video display apparatus using a display apparatus of a PDP according to the present invention. However, such a device is often used outdoors, and since a display device according to the present invention is used, display with high luminance, high luminous efficiency, and low power consumption can be realized.

As described above, according to the present invention, the period of the pulse voltage of the display function of the PDP can be lengthened without increasing the number of driver circuits, and the luminous efficiency can be improved, and the number of pulses can be increased to obtain a display with high luminance.

Claims (25)

A method of driving a display device that supplies power to a plurality of electrodes functioning as a capacitive load via a first switch group and recovers power from the electrodes through a second switch group, Filling each of the first and second electrodes through a first path from a charge supply source to each of the first number of electrodes; And discharging a second number of electrodes of the plurality of electrodes through a second path from each of the second number of electrodes to the charge supply source, wherein the first path comprises a first inductance and the second inductance, Wherein the second path comprises a corresponding switch and a second inductance of the second switch group, wherein the first inductance and the second inductance are different from each other, And the discharge is simultaneously performed. The method of claim 1, further comprising: detecting the first number of electrodes for charging and detecting the second number of electrodes for discharging; And controlling an inductance value in each of the first and second paths in accordance with the detected first and second number of electrodes. 1. A driving circuit for a display device having a plurality of electrodes for a display element functioning as a capacitive load, comprising: a charge supply source having one of a power supply and a charged capacitor; At least two of said plurality of electrodes being connected to said charge source at a first terminal, and at least two corresponding first unidirectional switches at its output terminal, said first switch having a first switch, a first diode and a first inductance element, A first series circuit connected to the first electrode, the first diode, and the corresponding first unidirectional switch being conductive when the at least two electrodes are charged; At least two of the plurality of electrodes being connected to the charge source at a first terminal, and at least two corresponding second unidirectional switches at an output terminal thereof, the second switch, the second diode and the second inductance element, And a second series circuit connected to the first electrode, the second diode, and the corresponding second unidirectional switch, when the at least two electrodes are discharged, and the second inductance and the second inductor And the second inductance are different from each other. 4. The inductance device according to claim 3, wherein the output terminal of the first inductance element is connected to a switching circuit for maintaining the output terminal of the first inductance element at a level of a high voltage power supply, and an output terminal of the second inductance element is connected to the output terminal of the second inductance element And a switching circuit for maintaining the output terminal at the level of the low voltage power source. The driving circuit of a display device according to claim 3, wherein each of the first and second unidirectional switches comprises a series circuit of a diode and an FET. The driving circuit of a display device according to claim 3, wherein each of the first and second unidirectional switches comprises a bipolar transistor circuit. 4. The inductance device according to claim 3, wherein a plurality of the first series circuits each having the first switch, the first diode and the first inductance element are connected in parallel, and the inductance values of the plurality of first inductance elements are And a plurality of second series circuits each including the second switch, the second diode and the second inductance element are connected in parallel, and the inductance value of the plurality of second inductance elements Is configured as a binary system. The plasma display apparatus according to claim 3, wherein each of the plurality of electrodes is connected to a voltage holding circuit for holding the level of the electrode at the level of the high voltage power source and a voltage holding circuit for holding the level of the electrode at the level of the low voltage power source And a driving circuit for the display device. The driving circuit of a display device according to claim 3, wherein the plurality of electrodes as display elements are address electrodes of an AC type plasma display. A display device comprising: a display device having a plurality of electrodes for a display element functioning as a capacitive load and having a switch inserted between the power recovery circuit and the electrodes; and a drive circuit for driving the display device, the display device comprising: a charge supply source; A first switch, a first diode, and a first inductor, the first switch being connected to the charge supply source, the output terminal being connected to a first number of the plurality of electrodes via a corresponding number of first unidirectional switches A first series circuit in which the first switch, the first diode, and the first unidirectional switch are conducted when at least one of the first number of electrodes is charged; A second switch, a second diode and a second inductor connected to the charge supply source and connected to a second number of the plurality of electrodes through a corresponding number of second unidirectional switches at an output terminal thereof And a second series circuit in which the second switch, the second diode, and the second unidirectional switch conduct when at least one of the second number of electrodes is discharged, and wherein the first inductor and the second inductor Are different from each other. 11. The inductor according to claim 10, wherein an output terminal of the first inductor is connected to a first switching circuit for maintaining the output terminal of the first inductor at a level of a high voltage power supply, and an output terminal of the second inductor is connected to an output terminal Is connected to a second switching circuit for holding the first power supply voltage at a level of the low voltage power supply. 11. The display device according to claim 10, wherein each of the first and second unidirectional switches includes a series circuit having a diode and an FET. 11. The display device according to claim 10, wherein each of the first and second unidirectional switches includes a bipolar transistor. 11. The inductor of claim 10, wherein a plurality of the first series circuits each having a first switch, a first diode and a first inductor are connected in parallel, and the inductance values of the plurality of first inductors are constituted by a binary system And a plurality of second series circuits each having a second switch, a second diode and a second inductor are connected in parallel, and the inductance values of the plurality of second inductors are constituted by a binary system / RTI > 11. The apparatus of claim 10, further comprising: a first voltage holding circuit connected to each of the electrodes and configured to maintain each of the electrodes at a level of a high voltage power supply; And a second voltage holding circuit connected to each of the electrodes and configured to maintain each of the electrodes at a level of a low voltage power source. 11. The display device according to claim 10, wherein the plurality of electrodes which are display elements are address electrodes of an AC type plasma display. A driving circuit of a display device which supplies power to a plurality of electrodes functioning as capacitive loads via a first switch group and recovers power from the plurality of electrodes through a second switch group, The first switch group being respectively coupled to the electrodes; The second switch group being respectively coupled to corresponding ones of the plurality of electrodes; A first path having a first inductance and having a first end coupled to the charge supply source via the first switch group and a second end coupled to the plurality of electrodes; And a second path having a second inductance and having a first end coupled to the charge supply source via the second group of switches and a second end coupled to the plurality of electrodes, Wherein a current is discharged from the charge supply source through the first path and a corresponding switch in the first switch group, and a current for discharging each of the plurality of electrodes flows from each of the plurality of electrodes to the second path And to flow to the charge supply source via a corresponding switch of the second switch group, charging a first number of electrodes of the plurality of electrodes and discharging a second number of electrodes of the plurality of electrodes simultaneously And a driving circuit for driving the display device. 18. The apparatus of claim 17, further comprising: means for detecting a first number of electrodes to be charged simultaneously and a second number of electrodes to be discharged; And means for controlling the inductance value in each of the first and second paths in accordance with the detected first and second number of electrodes. A charge supply source having a first charging terminal; A first diode, and a first inductor connected in series, wherein the first switch is connected to the first charging terminal, the first inductor is connected to the first output terminal, A first series circuit in which a first diode is configured to conduct current in a direction from the first switch to the first inductor; A second switch, a second diode, and a second inductor, the second switch being connected to the first charging terminal, the second inductor being connected to the second output terminal, A second series circuit in which a second diode is configured to allow a current to flow in the direction from the second inductor to the second switch, a second series circuit that is connected in series between the first output terminal and the second output terminal, A plurality of display elements each having a first electrode connected to the first unidirectional switch; A first end connected to the first output terminal, a second end connected to the first electrode and also to a first end of the second unidirectional switch, the first output terminal and the corresponding display element The first unidirectional switch being configured to selectively flow current between the first unidirectional switch and the second unidirectional switch; The first end of which is connected to the first electrode, the second end of which is connected to the second output terminal, and the current is selectively allowed to flow between the corresponding display element and the second output terminal, Wherein the first inductor and the second inductor are different from each other. 20. The display device according to claim 19, wherein the first and second unidirectional switches comprise one of a bipolar transistor and a field effect transistor connected in series with a diode. 21. The apparatus of claim 20, further comprising: a first switching circuit coupled to the first output terminal, the first switching circuit configured to maintain the first output terminal at a high voltage level; And a second switching circuit connected to the second output terminal and configured to maintain the second output terminal at a low voltage level. 20. The apparatus of claim 19, further comprising: a first voltage holding circuit coupled to the first electrode and configured to selectively maintain the voltage of the first electrode at a high voltage level; Further comprising a second voltage holding circuit connected to the first electrode and configured to selectively maintain the voltage of the first electrode at a low voltage level. 20. The battery pack according to claim 19, further comprising: the first series circuit connected between the first charging terminal and the first output terminal, and the second series circuit connected between the first charging terminal and the second output terminal, And a plurality of circuits are included. 24. The apparatus of claim 23, further comprising: a first switching circuit coupled to the first output terminal, the first switching circuit configured to maintain the first output terminal at a high voltage level; And a second switching circuit connected to the second output terminal and configured to maintain the second output terminal at a low voltage level. 18. The driving circuit of a display device according to claim 17, wherein each of said first and second switch groups includes a unidirectional switch.

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