EP0829846A2

EP0829846A2 - Driving method and circuit for display and display apparatus using thereof

Info

Publication number: EP0829846A2
Application number: EP97115719A
Authority: EP
Inventors: Akihiko no. 502 Daini-kiraku-haitsu Kougami; Keizou Suzuki; Michitaka Oosawa; Masaji Ishigaki; Kazutaka no. 304 Daijuusan-yamani-haitsu Naka; Hiroshi no. 105 Kopo-shimokurata Ootaka; Isamu Orita; Kouzou Sakamoto; Shigeo Mikoshiba; Tateaki Okabe; Masahiro Eto
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1996-09-17
Filing date: 1997-09-10
Publication date: 1998-03-18
Also published as: KR100279783B1; EP0829846A3; KR100299715B1; KR19980024595A

Abstract

In a method for driving a display device, by which energy stored in a plurality of electrodes serving as a capacitive load is recovered through switches, current paths for charging said electrodes from a charge supplying source differ from current paths for discharging the electrodes for the energy recovery.

Description

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The present invention relates to a driving method and a driving circuit for driving a display device serving as a capacitive loads, such as a PDP (a plasma display device) radiating light and displaying by using a discharging phenomenon, in which scanning and each pulse of the display is applied to a plurality of electrodes in a sequential order, and in addition thereto, relates to a display apparatus using thereof.

DESCRIPTION OF RELATED ART

Heretofore a switching circuit for passing-through or cutting-off an input signal by means of semiconductor elements is discussed in "How to use FETs" pp. 110-114, published by CQ Publishing Co. Ltd., 1983, in which a method is described, by which a small signal is inputted in the source MOS transistor and an output signal is taken out from the drain, whereby the potential of the body (substrate) is set with respect to the source or the drain so that the p-n junctions therebetween are never biased in the forward direction under any conditions and the signal conduction and cutting-off is controlled by the gate voltage.
However by the prior art technique any attention is paid neither to passing-through or cutting-off high voltage signals nor to utilizing positively a stray diode between the drain and the body.
Further, there are disclosed heretofore a method for driving a plurality of electrodes of display elements, which are capacitive loads, a method for driving a circuit therefor by means of simple push-pull circuits, and a method, by which an energy recovery circuit is used for reducing electric energy consumption.
In the former push-pull circuits, as indicated in Fig. 39, there are disposed switching circuit 1201 between a high voltage power supply 1115 and electrodes 1112 of display elements 604, 607, 6l0 and switching circuits 1202 between the electrodes 1112 and the ground level, and high voltage pulses are applied to the electrodes 1112 by on - off controlling these circuits 1201 and 1202. When the circuit is driven in this way, consumption energy for charging and discharging the electrodes increases.
Furthermore, there are two types in the PDP devices, such as a so-called AC type and a DC type.
In the AC type of the PDP, electrodes in a discharge space within the panel thereof are covered with a layer of dielectric and the electric charge of discharging comes and goes on the dielectric, therefore, it is called as alternating current type, i.e., the AC type. In the driving device/method with this AC type, the pulse for the display radiates light continuously by a memory effect by wall charges on the dielectric layer.
On a while, in the DC type of the PDP, the electrodes within the panel is exposed within the discharge space and the electric charge due to discharging penetrates through the electrodes to outer circuit. Therefore, this type of the PDP is called as the direct current type, i.e., the DC type, and the memory function of the display pulse is achieved by floating charge within the discharge space.
Moreover, as the driving method of the PDP, there were already known two methods, i.e., an address/display separating method and an address/display multiplex method, heretofore.
The address/display separating method is disclosed, for example, in JP - A - 4-195188 (1992).
Explaining this by referring to Fig. 46, one frame (FM) is divided into a plurality of sub-frames (SF1 through SF4), and each sub-frame is divided into an address cycle and a display cycle. In this address cycle, as shown in Fig. 3 (47), there are a priming period and a writing period, and in the priming period, discharging (PW) - erasure is carried out in all of the discharge cells. In the writing period, the electrode is selected by scanning each Y electrodes (Pf), and the wall charge is generated once in the discharge cell by the scanning pulse and the writing pulse coincident therewith. With the display pulse (Ps) in the next display cycle, only the discharge cell in which the wall charge is generated radiates light for display.
In this method, the address cycle and the display cycle are separated at the same time in all of the discharge cells and it needs a long time from generating the wall charge once to applying the display pulse during the address period, therefore it is the driving method applicable only to the PDP of the AC type in which the wall charge is used as the memory effect.
On the other hand, the address/display multiplex method of the driving method for the same AC type of PDP is disclosed in Japanese Patent No. 2,528,195.
Explaining this with reference to Fig.48, one frame is divided into a plurality of sub-frames, and time width of radiating light of each sub-frame constitutes a binary system. The each sub-frame is shifted in time on the lines of the electrodes, thereby driving the lines sequentially. Further, the driving wave-form within the sub-frame, as shown in Fig. 49, does the writing with a writing pulse (P_W) once, and the pulse (P_S) of display does not radiate light when an erasing pulse (P_E) is applied, otherwise, it radiate light when the erasing pulse (P_E) is not applied.
Further, since the memory effects is achieved by using a space charge in the driving method for the DC type of the PDP, the display pulse must be applied just after the addressing, therefore, all of those belong to a kind of the address/display multiplex method. Such the driving method is disclosed in JP - B - Hei 7-7246 (1995), in which the scanning pulse is applied to a cathode K, and just after this the pulse of the display is applied to an anode A. The scanning of the panel is carried out from the top to the bottom of the panel sequentially, taking the time of one field fully.

SUMMARY OF THE INVENTION

By the latter method, by which energy recovery circuit is used, it is possible to decrease significantly this consumption energy for charging and discharging the electrodes. For example, in JP - A - Sho 63-101897 (1988), there is described a method, by which electric charge stored in the electrodes and released therefrom at charging and discharging the electrodes is recovered by utilizing resonance of inductors and the electrodes which are capacitive loads. According to this example, it is disclosed that the circuit can be driven by an electric power a 1/10 time as small as that required by a prior art circuit.
On the other hand, when the electrodes which are capacitive loads are driven, it makes integration difficult to dispose an energy recovery circuit for each of the electrodes, because the energy recovery circuit includes an inductor and also it is not advisable with respect to the number of parts. Therefore it is preferable to dispose an energy recovery circuit in common for all the electrodes. In this case, for a driving method, by which presence of the high voltage pulse differs for different display elements, it is necessary to dispose a switching circuit between the energy recovery circuit and each of the electrodes. This switching circuit is disclosed in JP - A - Hei 2-92111 (1990). In this example it is also disclosed to recover energy stored and released at charging and discharging the electrodes through a switch.
A first object of the present invention is to provide a method for driving display elements, by which a simple circuit construction, in which electric power or energy consumption is low and width of the high voltage pulse can be controlled, is driven, and to provide a circuit for realizing same.
By the method for driving the electrodes by using push-pull circuits according to the prior art technique, there is a problem that charging and discharging electric power is great, which increases energy consumption of the whole device. For example, heretofore high withstand voltage driver ICs are used usually in this type of driving circuits, an energy consumption of the high withstand voltage driver ICs increases with increasing frequency driving pulse. This may give rise to cases where the high withstand voltage driver ICs are damaged by heat produced therein, which impairs remarkably reliability of the device.
Further, the method for recovering energy stored and released at charging and discharging the electrodes by using switching circuits according to the prior art technique is one, by which only presence or absence of the applied high voltage pulse is controlled and neither rise nor fall of the pulse is controlled for the purpose of controlling the pulse width. Depending on the mode of driving a display device, presence or absence of the high voltage pulse is not controlled but the pulse width of the high voltage pulse should be controlled. For example, for address electrodes of an AC type plasma display, it is necessary to control the pulse width of the high voltage pulse according to signals to be displayed. For such driving, it is necessary to control rise or fall of the pulse. However, heretofore, nothing is mentioned thereon.
Consequently the first object of the present invention is to provide a driving method having a low electric power consumption in spite of the pulse width which can be arbitrarily selected and a circuit for realizing same.
The first object can be achieved by a more concrete driving method, by which drive of a plurality of electrodes of display elements, which are capacitive loads, is effected by a method for recovering energy through switches so that current paths for charging the electrodes differ from current paths for discharging them.
It can be achieved also by effecting simultaneously charging and discharging of the electrodes of the display elements.
Further, it can be achieved also by detecting the number of electrodes, which are being charged, and the number of electrodes, which being discharged, among the electrodes of the display elements and by controlling inductance values for energy recovery, depending on the numbers thus detected.
Still further, the first object can be achieved by a more concrete construction, in which series circuits, each of which includes a first switch, a first diode, and a first inductor, are connected with a power supply or a charged capacitive element and output terminal thereof is connected with at least two electrodes through at least two first unidirectional switches, the first switch, the first diode, and the first unidirectional switches being conductive, when the electrodes are being charged; and
series circuits, each of which include a second switch, a second diode, and a second inductor, are connected with the power supply or the charged capacitive element and the output terminal thereof is connected with at least two electrodes through at least two second unidirectional switches, the second switch, the second diode, and the second unidirectional switches being conductive, when the electrodes are being discharged.
Further it can be achieved by connecting a switching circuit with the output terminal of the first inductor, which switching circuit holds at the level of the high voltage power supply, and a switching circuit with the output terminal of the second inductance element, which switching circuit holds it at the level of the low voltage supply.
Still further it can be achieved by constructing the first and second unidirectional switches by using series connecting circuits, each of which includes a diode and an FET.
Still further it can be achieved by constructing the first and second unidirectional switches by using bipolar transistor circuits.
Still further it can be achieved by constructing each of the plurality of series circuits by a first switching circuit, a first diode, and a first inductor, reciprocals of inductance values of a plurality of first inductors forming approximately a binary system, and each of the plurality of series circuits by a second switching circuit, a second diode, and a second inductor, the inductance values of a plurality of second inductors forming approximately a binary system.
Still further it can be achieved by connecting each of the electrodes of the display elements with a voltage hold circuit holding it at the level of the high voltage power supply and another voltage hold circuit holding it at the level of the low voltage power supply.
Still further it can be achieved by making the electrodes of the display elements serve as address electrodes of an AC type plasma display.
Further, in the prior art mentioned in the above, because the period of the display pulse is short, the space charge within the discharge cell becomes large number, thereby showing a drawback of low efficiency in light radiation. Furthermore, it has a drawback that large number of the display pulses cannot be applied thereto. Moreover, since it is impossible to apply the pulses to be applied to the electrodes in common, there is a drawback that the circuits increases in the number thereof.
Also hereinafter, the drawbacks of the driving methods of the prior art, in particular relating to the PDPs of the AC type and the DC type, which are mentioned in the above, will be also explained in more detail.
In the address/display separating method for the AC type PDP shown in the Fig. 46, more than 70% of the time of one field is necessary for the time of the address cycle, therefore, the time of the display cycle becomes less than 5 msec. In order to increase the brightness in light emission, a large number of the display pulse, such as 500 pulses, must be inserted within the period between those display cycles. For that reason, the period of the display pulse becomes short, such as around 10 µsec. If the period of the display pulse is short, the number of discharging increases in a unit of time. Thereby the space charges in the discharge cell increases in the number thereof so as to decelerate electron of discharge. For that reason, a probability of excitation of a gas in the panel, i.e., Xe atom, becomes small, and the light emission efficiency is reduced.
On the contrary of this, if making the time width of the display cycle longer, light emission efficiency is improved, however, the number of the display pulses comes to be small and the brightness of the light emission is decreased. For the purpose of enlarging the time period of the display pulses as well as increasing in the number of thereof, it is only enough to enlarge the time width of the display cycle. However, if doing so, the time width of the address cycle becomes too short, thereby causing the discharge mischievously, during the operation of writing of the wall charge generation. Accordingly, in the address/display separation method for the AC type PDP, there is a limitation in further increase in the light emission efficiency and in the brightness thereof.
On the other side, in the address/display multiplex method for the AC type PDP shown in the Figs. 48 and 49, almost of the time period of the one frame can be utilized for the time of display. Accordingly, it is possible to elongate the period of the display pulse and to increase the number of the pulses applied. However, because the display is the matrix panel, the writing pulse P_W and the erasing pulse P_E must be applied to the X electrodes and the Y electrodes independently and respectively. Moreover, since those pulses P_W and P_E are driving the electrodes in the sequential order, as shown in the Fig. 48, a driver circuit is necessary for each one of those electrodes, thereby increase the number of the circuitry.
Further, in the driving method for the DC type PDP shown in Figs. 50 and 51, since the way of discharging is in the DC type, in order to increase the light emission efficiency, the pulse width of the display pulse applied to the anode must be very narrow, such as around 0.2 µsec., but if constructing the circuit for generating such the display pulse with an energy recovery circuit, there is a drawback that it also results in decrease-down in the recovery rate or efficiency thereof.
And, for performing the discharging with such the narrow pulse, there is also a problem that the voltage value of the pulse comes to be 300 V of high voltage, therefore, tolerance of the circuit elements used therein must be high enough against such the high voltage.
Furthermore, as a problem for the driving method by itself of such, the display pulses to be applied to the anodes are interrupted at the respective sub-fields and they are shifted one another in time for the respective electrodes. Therefore, the driving circuit is needed for each electrode, thereby increasing the number of the circuits thereof.
Accordingly, for dissolving such the problems mentioned in the above, an another object of the present invention is to provide a driving method , a driving circuit and an driving apparatus, in particular, for the PDP, with which the light emission efficiency is improved by elongating the period of the display pulse and high brightness can be obtained by increasing the number of the pulses applied, as well as the increase in the number of the circuits can suppressed.
For accomplishing the object mentioned above, in accordance with the present invention, there is provided a driving method for a plasma display panel having at least a plurality of cells, each of which has three electrodes (X electrode, Y electrode and A electrode) and a discharge space, at least a surface of at least two (X electrode and Y electrode) of said three electrodes, which surface is adjacent to said discharge space, being covered with an dielectric insulator, wherein a large set of cells including total body of said plurality cells is divided into a plurality of middle sets of cells, and the Y electrodes of said cells belonging to the same middle set of cells within said middle sets of cells are connected to one another with an electrode;
dividing information to be displayed on said plasma display panel into a plurality number (k) of sub-fields, which information is constructed with one or more fields; and
scanning one sub-field A (herein after, called "sub-field A") of said plurality of sub-fields by the middle set A (herein after, called "middle set A") of cells in said plurality of middle sets of cells, and scanning the sub-field(s) other than the sub-field A by any one of the middle sets of cells while the middle set(s) of cells other than the middle set A of cells scans said sub-field A.
Further, the scanning is carried out by applying a pulse voltage to at least any one of said Y electrode and said A electrode or both thereof.
Further, in accordance with the present invention, display is carried out during a period between the scanning which is carried out by at least one of said middle set of cells and a scanning which will be carried out next.
Further, in accordance with the present invention, said X electrodes of the cells belonging to said middle set of cells are connected with an electric conductor.
Further, in accordance with the present invention, the display function is carried out by applying a pulse voltage to at least any one of said X electrode and said Y electrode or both thereof.
Further, in accordance with the present invention, the display function is carried out by applying the pulse voltage to said X electrode and said Y electrode alternatively.
Further, in accordance with the present invention, a time region lies in a display period, and further comprises steps of:

applying a periodic pulse signal in common to said X electrode for assemblies of said middle sets of cells for the time range, in at least one or more assemblies of said middle sets of cells; and
applying a pulse voltage to said Y electrode, which voltage has at least the scanning function and the display function at same time or separately, in each middle set of cells of the assemblies of said middle sets of cells.

Further, in accordance with the present invention, said X electrodes of all the cells belonging to said large set of cells are connected with an electric conductor.
Further, in accordance with the present invention, the assembly of said middle sets of cells is said large set of cells.
Further, in accordance with the present invention, a pulse voltage having priming function is also applied to said Y electrode.
Further, in accordance with the present invention, while one of the middle sets of cells which are spatially neighboring to each other conducts the scanning function and the other thereof conducts the scanning function thereafter, the number k of the pulse voltages are applied to said A electrodes, where the k is the number of the divided sub-fields or an integral multiples thereof.
Further, in accordance with the present invention, the pulse voltage having the priming function overlaps the periodic pulse voltage to be applied to said X electrode at least one time in time.
Further, in accordance with the present invention, the periodic pulse voltage is applied to said X electrode at least for a time period of one field of the display information.
Further, in accordance with the present invention, the periodic pulse voltage applied to said X electrode is different from the pulse voltage applied to said Y electrode having the priming function, in polarity thereof.
Further, in accordance with the present invention, the periodic pulse voltage applied to said X electrode has a negative polarity, and the pulse voltage applied to said Y electrode having the priming function has a positive polarity.
Further, in accordance with the present invention, the periodic pulse voltages applied to said X electrode are differentiated in time between at least two of said middle sets of cells.
Further, in accordance with the present invention, in said sub-field, a first pulse voltage of the periodic pulse voltages is applied to said X electrode of any one of the middle sets of cells, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
Further, in accordance with the present invention, in said sub-field, the pulse voltage having the priming function is applied to said Y electrode of any one of the middle sets of cells, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
Further, in accordance with the present invention, in the assembly of at least one or more of said middle sets of cells, the pulse voltages having the priming function to said Y electrodes thereof are applied to them at a same time instance.
Further, in accordance with the present invention, while the pulse voltage having the scanning function of any one sub-field is applied to and then the pulse voltage having the scanning function of another sub-field than that sub-field is applied to said Y electrode of said middle sets of cells, a number of pulse voltages of the information to be displayed is applied to said A electrode, as defined in blow; $k × n + p (1 ≦ p ≦ k - 1)$
where k, n and p are positive integers.
Further, in accordance with the present invention, the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage having the scanning function and to be applied to said Y electrode of the middle set of cells do not overlap to each other in time.
Further, in accordance with the present invention, the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage of the display function and to be applied to said Y electrode of the middle set of cells do not overlap to each other in time.
Further, in accordance with the present invention, the pulse voltage to be applied to said A electrode does not overlap with the periodic pulse voltage applied to said X electrode and the pulse voltage having the display function and to be applied to said Y electrode in time.
Further, in accordance with the present invention, while applying the pulse voltage having the scanning function of any sub-field to said middle set of cells and applying periodically the pulse voltage having the display function thereafter, application of the periodic pulse voltage having the display function is terminated before the pulse voltage having the priming function for a next sub-field is applied.
Further, in accordance with the present invention, a pulse voltage having erasure function is applied between the pulse voltage having the display function and the pulse voltage having the priming function.
Further, in accordance with the present invention, a pulse voltage having preliminary discharge (or pre-discharge) function is applied after termination of the periodic pulse voltage having the display function and before application of the pulse voltage having the priming function.
Further, in accordance with the present invention, number of the pulse voltages having the display function is differentiated at least between the two of said sub-fields.
Further, in accordance with the present invention, the number of the pulse voltages having the display function is arranged into a ratio about 1:2:4 among at least three of said sub-fields.
Further, in accordance with the present invention, there is provided a display apparatus using a plasma display panel having at least a plurality of cells, each of which has three electrodes including X electrode, Y electrode and A electrode, and a discharge space, at least a surface of at least said X electrode and Y electrode, which surface is adjacent to said discharge space, being covered with an dielectric insulator, wherein a large set of cells including total body of said plurality cells is divided into a plurality of middle sets of cells, the Y electrodes of said cells belonging to the same middle set of cells within said middle sets of cells are connected to one another with an electrode, and information to be displayed on said plasma display panel is divided into a plurality number (k) of sub-fields, which information is constructed with one or more fields, comprising:

means for scanning one sub-field A (herein after, called "sub-field A") of said plurality of sub-fields by the middle set A (herein after, called "middle set A") of cells in said plurality of middle sets of cells; and
means for scanning the sub-field other than the sub-field A by any one of the middle sets of cells while the middle set of cells other than the middle set A of cells scans said sub-field A.

Further, in accordance with the present invention, the scanning is carried out by providing further means for applying a pulse voltage to at least any one of said Y electrode and said A electrode or both thereof.
Further, in accordance with the present invention, it is so constructed to able to include:

means for carrying out said scanning by at least one of said middle set of cells; and
means for carrying out the display function during a next scanning is carried out.

Further, in accordance with the present invention, said X electrodes of the cells belonging to said middle set of cells are connected with an electric conductor.
Further, in accordance with the present invention, further comprises means for the display function to apply a pulse voltage to at least any one of said X electrode and said Y electrode or both thereof.
Further, in accordance with the present invention, further comprises means for carrying out the display function by applying the pulse voltage to said X electrode and said Y electrode alternatively.
Further, in accordance with the present invention, wherein a time region lies in a display period, further comprises:

means for applying a periodic pulse signal in common to said X electrode for assemblies of said middle sets of cells for the time range, in at least one or more assemblies of said middle sets of cells; and
means for applying a pulse voltage to said Y electrode, which voltage has at least the scanning function and the display function at same time or separately, in each middle set of cells of the assemblies of said middle sets of cells.

Further, in accordance with the present invention, wherein a time region lies in a display period, further comprises:

Further, in accordance with the present invention, wherein said X electrodes of all the cells belonging to said large set of cells are connected with an electric conductor.
Further, in accordance with the present invention, wherein the assembly of said middle sets of cells is said large set of cells.
Further, in accordance with the present invention, further comprises means for applying also a pulse voltage having priming function to said Y electrode.
Further, in accordance with the present invention, further comprises:

means for conducting the scanning function on one of the middle sets of cells which are spatially neighboring to each other; and
means for applying a number k of the pulse voltages to said A electrodes, during conduction of the scanning function on the other, where the k is the number of the divided sub-fields or an integral multiples thereof.

Further, in accordance with the present invention, further comprises means for overlapping the pulse voltage having the priming function and the periodic pulse voltage to be applied to said X electrode at least one time in time.
Further, in accordance with the present invention, further comprises means for applying the periodic pulse voltage to said X electrode at least for a time period of one field of the display information.
Further, in accordance with the present invention, further comprises means for differentiating the periodic pulse voltage applied to said X electrode from the pulse voltage applied to said Y electrode having the priming function, in polarity thereof.
Further, in accordance with the present invention, further comprises:

means for making the periodic pulse voltage applied to said X electrode a pulse voltage of a negative polarity; and
means for making the pulse voltage applied to said Y electrode having the priming function a pulse voltage of a positive polarity.

Further, in accordance with the present invention, further comprises means for differentiating the periodic pulse voltages applied to said X electrode in time between at least two of said middle sets of cells.
Further, in accordance with the present invention, further comprises means for applying a first pulse voltage of the periodic pulse voltages to said X electrode of any one of the middle sets of cells, in said sub-field, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
Further, in accordance with the present invention, further comprises means for applying the pulse voltage having the priming function to said Y electrode of any one of the middle sets of cells, in said sub-field, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
Further, in accordance with the present invention, further comprises means for applying the pulse voltages having the priming function to said Y electrodes in the assembly of at least one or more of said middle sets of cells at a same time instance.
Further, in accordance with the present invention, further comprises:

means for applying the pulse voltage having the scanning function of any one sub-field to said Y electrode of said middle sets of cells; and
means for applying a number of pulse voltages of the information to be displayed to said A electrode, during applying the pulse voltage having the scanning function of another sub-field than that sub-field to said Y electrode of said middle sets of cells, wherein the number of pulse voltages is defined in below; $k × n + p (1 ≦ p ≦ k - 1)$
where k, n and p are positive integers.

Further, in accordance with the present invention, further comprises means for making the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage having the scanning function and to be applied to said Y electrode of the middle set of cells not to overlap to each other in time.
Further, in accordance with the present invention, further comprises means for making the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage of the display function and to be applied to said Y electrode of the middle set of cells not to overlap to each other in time.
Further, in accordance with the present invention, further comprises means for making the pulse voltage to be applied to said A electrode not to overlap with the periodic pulse voltage applied to said X electrode and the pulse voltage having the display function and to be applied to said Y electrode in time.
Further, in accordance with the present invention, further comprises:

means for applying the pulse voltage having the scanning function of any sub-field to said middle set of cells;
means for applying periodically the pulse voltage having the display function after the pulse voltage having the scanning function; and
means for terminating application of the periodic pulse voltage having the display function before the pulse voltage having the priming function for a next sub-field is applied.

Further, in accordance with the present invention, further comprises means for applying a pulse voltage having erasure function between the pulse voltage having the display function and the pulse voltage having the priming function.
Further, in accordance with the present invention, further comprises means for applying a pulse voltage having preliminary discharge function after termination of the periodic pulse voltage having the display function and before application of the pulse voltage having the priming function.
Further, in accordance with the present invention, further comprises means for differentiating number of the pulse voltages having the display function at least between the two of said sub-fields.
Further, in accordance with the present invention, further comprises means for arranging the number of the pulse voltages having the display function at a ratio about 1:2:4 among at least three of said sub-fields.
Further, in accordance with the present invention, wherein the means for conducting the display function in said middle sets of cells is so constructed that it applies the periodic pulse from a energy recovery circuit through a switch.
Further, in accordance with the present invention, wherein said plasma display panel is a AC type.
Further, in accordance with the present invention, wherein said display apparatus is a television display apparatus, a data monitor display apparatus, a television monitor display apparatus for displaying image signal from a camera, or an information display apparatus in public places.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a circuit diagram showing an embodiment of the present invention;
Fig. 2 is a time chart indicating a timing of operation thereof;
Fig. 3 is an equivalent circuit diagram at the charging of the circuit indicated in Fig. 1;
Fig. 4 is a time chart indicating a timing of operation of the circuit according to the present invention indicated in Fig. 1;
Fig. 5 is a circuit diagram showing another embodiment of the present invention;
Fig. 6 is a time chart indicating a timing of operation of the circuit construction indicated in Fig. 5;
Fig. 7 is a circuit diagram showing further another embodiment of the present invention;
Fig. 8 is a time chart indicating a timing of operation of the circuit construction indicated in Fig. 7;
Fig. 9 is a circuit diagram showing further another embodiment of the present invention;
Fig. 10 is a circuit diagram of a negative voltage circuit, which can be used in the circuit indicated in Fig. 9;
Fig. 11 is a circuit diagram of further another embodiment of the present invention;
Fig. 12 is a time chart indicating a timing of operation of the circuit construction indicated in Fig. 11;
Figs. 13, 14 and 15 are circuit diagrams showing still other embodiments of the present invention;
Fig . 16 is a cross-sectional view of an integrated circuit;
Fig. 17 is a cross-sectional view of further another embodiment of the integrated circuit;
Fig. 18 is a scheme showing the circuit construction, when the present invention is applied to a matrix display device;
Fig. 19 shows an example of voltage waveforms applied to different electrodes in the circuit in Fig. l8;
Fig. 20 is a circuit diagram showing an example of the switch for a negative pulse according to the present invention;
Fig. 21 is a time chart indicating a timing of operation of the circuit indicated in Fig. 20;
Fig. 22 is a time chart indicating another timing of operation;
Figs. 23, 24, 25, 26, 27 and 28 are circuit diagrams showing various embodiments of the present invention;
Fig. 29 is a circuit diagram showing the construction of a switch for a negative pulse for a low voltage pulse;
Fig. 30 is a truth-false table showing the operation of the circuit indicated in Fig. 29;
Fig. 31 is a circuit diagram showing further another embodiment of the present invention;
Fig. 32 is a truth-false table showing the operation of the circuit indicated in Fig. 31;
Fig. 33 is circuit diagram showing further another embodiment of the present invention;
Fig. 34 is a circuit diagram showing further another embodiment of the present invention;
Fig. 35 is a time chart indicating a timing of operation of the circuit indicated in Fig. 34;
Fig. 36 is a block diagram illustrating a circuit construction using the circuit indicated in Fig. 20;
Fig. 37 is a block diagram illustrating a circuit construction, when the present invention is applied to a matrix panel;
Fig. 38 is a diagram showing a circuit construction indicating an example of circuits using unidirectional switches according to the present invention;
Fig. 39 is a diagram showing a prior art circuit construction;
Fig. 40 is a diagram showing a circuit construction indicating an example of circuits, in which bipolar transistors are used, according to the present invention;
Fig. 41 is a diagram showing a circuit construction indicating an example of circuits, in which voltage hold circuits are disposed at each the electrodes, according to present invention;
Fig. 42 is a diagram showing circuit construction indicating an example of circuits for controlling inductance values according to the present invention;
Fig. 43 is a diagram showing a circuit construction indicating an example of control circuits for switching circuits according to the present invention;
Fig. 44 is a time chart for explaining operation of each of the switching circuits according to the present invention;
Fig. 45 shows wave-forms of driving signals at various electrodes in a second embodiment of a driving method for PDP in accordance with the present invention;
Fig. 46 shows one example of address/display multiplex driving method for AC type PDP of prior art;
Fig. 47 shows wave-forms of driving signals in the conventional driving method shown in Fig. 46;
Fig. 48 shows one example of address/display multiplex driving method for AC type PDP of prior art;
Fig. 49 shows wave-forms of driving signals in the conventional driving method shown in Fig. 48;
Fig. 50 shows one example of address/display separation driving method for DC type PDP of prior art;
Fig. 51 shows scanning process in the conventional driving method shown in Fig. 50;
Fig. 52 is an exploded perspective view for showing construction of PDP;
Fig. 53 shows wiring of electrodes in PDP shown in Fig. 52;
Fig. 54 shows scanning process in the driving method of PDP in accordance with the present invention;
Fig. 55 shows wave-forms of driving signals at various electrodes in a second embodiment of the driving method for PDP in accordance with the present invention;
Fig. 56 shows wave-forms of driving signals at various electrodes in a third embodiment of the driving method for PDP in accordance with the present invention;
Fig. 57 shows wave-forms of driving signals at various electrodes in a fourth embodiment of the driving method for PDP in accordance with the present invention;
Fig. 58 shows one concrete embodiment of a method of gradation display in the driving method for PDP in accordance with the present invention;
Fig. 59 shows another concrete embodiment of a method of gradation display in the driving method for PDP in accordance with the present invention;
Fig. 60 shows construction of the second embodiment of a display apparatus of PDP in accordance with the present invention;
Fig. 61 shows circuit construction of one concrete example of a Y energy recovery circuit and a pulse voltage distributing circuit shown in Fig. 60;
Fig. 62 shows voltage wave-forms for explanation of operation of the concrete example shown in Fig. 61;
Fig. 63 shows circuit construction of another concrete example of the Y energy recovery circuit and the pulse voltage distributing circuit shown in Fig. 60;
Fig. 64 shows voltage wave-forms for explanation of operation of the concrete example shown in Fig. 63;
Fig. 65 shows circuit construction of one concrete example of a X energy recovery circuit shown in Fig. 60;
Fig. 66 shows voltage wave-forms for explanation of operation of the concrete example shown in Fig. 65;
Fig. 67 shows circuit construction of one concrete example of an A electrode driving circuit shown in Fig. 60;
Fig. 68 shows voltage wave-forms for explanation of operation of the concrete example shown in Fig. 67;
Fig. 69 shows construction of a second embodiment of a display apparatus of PDP in accordance with the present invention;
Fig. 70 shows circuit construction of one concrete example of a pulse voltage distributing circuit shown in Fig. 46;
Fig. 71 shows voltage wave-forms for explanation of operation of the concrete example shown in Fig. 70;
Fig. 72 is a system block diagram showing an application of the display apparatus of PDP in accordance with the present invention;
Fig. 73 is a system block diagram showing another application of the display apparatus of PDP in accordance with the present invention;
Fig. 74 is a system block diagram showing other application of the display apparatus of PDP in accordance with the present invention; and
Fig. 75 is a system block diagram showing further other application of the display apparatus of PDP in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinbelow some embodiments of the present invention will be explained in detail, referring to the drawings.
Fig. 1 is a circuit diagram showing a switching circuit, which is an embodiment of the present invention, and Fig. 2 is a time chart indicating a timing of operation thereof.
In Fig. 1, Q1 represents a PNP type transistor as a bipolar transistor for the current circuit stated above; Q2 an N channel MOS FET acting as a driving element, which passes-through or cuts-off high voltage signals; and C_L a capacitive load.
In the basic circuit described in the present embodiment, the FET Q2 plays the role of the switch, which passes-through and cuts-off a high voltage pulse V_IN by the gate V_G Of the FET Q2 according to a low voltage input signal V_C(101). At the conduction the high voltage pulse V_IN is applied from the drain D side to the source S side and thus the FET Q2 has a function to feed the capacitive load C_L.
Now the operation thereof will be explained, according to the time chart indicated in Fig. 2.
Since the transistor Q1 works in the emitter grounded type, an "L" level (V_H-V_DD) of V_C indicated in Fig. 2 is applied to the base B so that the transistor Q1 is turned on. The voltage at the emitter E is higher than the base voltage by about 0.7 V, if the transistor is a silicon element. The difference between this emitter voltage and the high power supply voltage V_H is applied across a resistor 102, producing a current I_O.
The current I_o flows out from the collector C of the transistor Q1 and passes through a resistor R, while charging the gate input capacitance C_i of the FET Q2. In this way a voltage is generated between the base and the source of the FET Q2.
Fig. 3 shows an equivalent circuit of the circuit charging the gate input capacitance C_i of the FET Q2. The gate voltage V_G is given by the following equation.
where ${τ = C}_{i} R$
; R is the resistance of the resistor R in Fig. 1; and I_O represents the intensity of the current.
τ in the above equation indicates the rise time constant of the FET Q2. Supposing that the resistance R is e.g. 30 kΩ and C_i is e.g. 100 pF, τ is equal to 3 µsec. As it can be seen from Eq. (1), it is possible to determine the current intensity I_O and the time constant τ independently from each other. In order to drive the FET Q2 with a high speed, the rise time constant τ should be as small as possible.
Concretely speaking, since the gate input capacitance C_i is determined by the structure of the element. However, if the resistance R is small, the voltage between the gate G and the source S of the FET Q2 is lower than the threshold value (V_TH) and thus the conduction is insufficient. Therefore the current intensity I_O is increased so that the voltage between the gate G and the source S is above the threshold value stated above. However, if this voltage is too high, the voltage between the gate G and the source S exceeds the withstand voltage V_GS max and destroys the element. In order to prevent it, a Zener diode 104 is connected in parallel with the resistor R between the gate G and the source S. Consequently, concerning the product of R and I_O, the following relation is valid:
where T represents the pulse period of the input signal V_IN.
In this way it is possible to drive the gate with a high speed to reduce the resistance R between the drain and the source S so that the FET Q2 serving as the switching element is in the conductive state.
Now the T₂ period of the low voltage input signal V_C in Fig. 2 is explained.
The transistor Q1 and the FET Q2 are in the cut-off state by applying the low voltage input signal V_C at the "H" level to the input terminal 101.
The electric charge stored in the capacitive load C_L and the gate input capacity C_i is discharged towards the "L" level (OV in Fig. 2) of the high voltage plase-shaped drain voltage on the drain D side during a period of time where there is no pulse, passing through the parasitic diode between the drain and the body. When the electric charge stored in the capacitive load on the source S side is discharged gradually, the peak value of the pulse becomes lower and lower, as indicated by P1 and P2 in Fig. 2, and finally it reaches the V_L level.
According to the embodiment described above, in the case where a high voltage of 2OO-3OOV is applied, the switch, which required heretofore a more complicated construction, can have a more simple construction capable of driving the driving element at the output stage with a low voltage.
Next Fig. 4 indicates an example, in the case where the control signal V_C for the transistor Q1 in Fig. 1 is a pulse signal synchronized with the pulse of the high voltage input signal V_IN. This reduces the electric power for driving the gate FET Q2 during the conductive period T₁ by taking the current I_O flowing through the transistor Q1 by a pulsed current. As indicated in Fig. 4, the signal V_C inputted in the base of the transistor Q1 during the conductive period T₁ Of the FET Q2 is composed of pulses, whose duration at the "L" level is t₀. At this time, as a condition, under which the MOS FET Q2 is satisfactorily turned on and the gate voltage doesn't exceed the withstand voltage (V_GSmax), similarly to that described above, the following inequality should be valid;
Next a case where a PNP transistor (Q1) is used for the bipolar transistor for the current circuit described above and a P channel FET (Q2) for the switching element will be explained, referring to Figs. 5 and 6.
In Fig. 5, the source of the P channel FET (Q2) serves as the input terminal for the high voltage signal V_IN and the drain thereof as the output terminal, in which a diode 504 is connected between the gate and the source. The emitter side of the transistor Q1 in the current control circuit is connected with the power source V_H having the same level as the H level of the high voltage signal V_IN through a resistor 5O2 controlling the intensity of the current. Fig. 6 shows variations of the input signal V_IN, the control signal V_C and output signal V_OUT for this switching circuit construction. When the FET Q2 serving as the switching element is turned to the conductive state (T₁ in Fig. 6), it turns off the current control circuit. At this time when the high voltage pulse is applied to V_IN, a potential difference takes place automatically between the gate and the source of the FET Q2 owing to the Zener diode (504 in Fig. 5), which turns on the FET Q2. Then, when the FET Q2 is switched off, as indicated by V_C in Fig. 6, a negative pulse synchronized with the high voltage signal V_IN is applied to the base 501 of the transistor Q1 in Fig. 5. At this time the potential at the gate of the FET Q2 is V_H owing to the fact that the transistor Q1 is switched on and thus the FET Q2 is switched off, even if the pulse amplitude of the high voltage signal V_IN is V_H, because there is no potential difference between the gate and the source thereof.
Next a case where a voltage hold circuit is added to the switching circuit indicated previously in Fig. 1 will be explained, referring to Figs. 7 and 8.
A case where an N channel FET Q3 is used as a voltage hold circuit element will described.
The transistor Q1 serving as a current source element has the function as the same function as that of the transistor Q1 indicated in Fig. 1. Here the voltage V_C indicated in Fig. 8. is applied to the input terminal 701. In the period T₁, similarly to period T₁ indicated in Fig. 2, the FET Q2 is switched on and thus the high voltage pulse-shaped drain voltage V_IN applied to the drain D side produces the source voltage V_OUT on the source S side, which is applied to the load C_L.
Then, in the period T₂ also, similarly to the period T₂ indicating Fig. 2, the FET Q2 is switched off. The electric charge stored in the input capacitance and the capacitive load during the T₁ period is discharged towards the "L" level (OV) Of the high voltage pulse-shaped drain voltage V_IN, passing through the parasitic diode of the FET Q2. At this time in order to fix the potential on the source S side, a hold input signal V_S indicated in Fig. 8 is applied to the gate G input terminal 702 of the FET Q3 serving as the voltage hold element. The FET Q3 is switched on by the "H" level of the hold input signal V_S.
In this way the potential V_OUT at the drain of the FET Q3 is 0 V and held. Consequently, as indicated in Fig. 8, the potential V_OUT at the source S of the FET Q2 is fixed at the "L" level (0 V) and held. Although explanation has been made in the above by using an N channel FET for the FET Q2, a P channel FET can be operated similarly with the voltage hold circuit. Further, not only the FET but also a transistor (NPN or PNP), to which a diode is connected in parallel, can be operated similarly.
Fig. 9 is circuit diagram showing another embodiment the present invention. Contrarily to the fact that in the circuit indicated previously in Fig. 1 the FET Q2 is switched by a signal on the high voltage over source side, in the circuit in the present embodiment the FET Q2 is switched by a signal on the ground potential side. A resistor R and a Zener diode have the same functions as those explained, referring to Fig. 1.
A P channel FET Q3 is an element for witching the current I_O just as the transistor Q1 indicated in Fig. 1 and this element is driven with a level shifted so that it can be controlled by a signal voltage between the ground potential and the low voltage power source voltage V_PD by means of a P channel FET Q4 a N channel FET Q5 constituting a current mirror circuit together with the FET Q3 described above.
Further the applied drain voltage V_IN has the same wave-form as that indicated in Fig. 2. Reference numeral 901 represents a signal circuit for driving the N channel FET Q5. It includes e.g. a shift register circuit and a latch circuit and has a function to convert image signals inputted in serial into parallel signals to output the signals in parallel. The power source voltage for this signal circuit is the low voltage power source voltage V_DD.
In this circuit, as described later, the PN junction isolation semiconductor layer is set at a voltage lower than the ground voltage so that the PN junction for the component isolation is never biased in the forward direction, even if the output voltage V_OUT is lowered to a value below the ground voltage.
A diode D1 in Fig. 9 is provided so that the output voltage V_OUT doesn't drop beyond the ground potential.
Fig. 10 illustrates an example of the construction of a negative voltage circuit, which can be used in the circuit indicated in Fig. 9. This circuit can lower the voltage of the P conductivity type semiconductor layer for the component isolation to a voltage lower than the ground voltage by about 7 V according to the charge pump principle by using a clock signal V_CLK applied to a capacitor C_Z and a signal obtained by applying the clock signal V_CLK, whose sign is inverted by an inverter circuit constituted by an N channel FET Q6 and a P channel FET Q7, to the cathode side of a diode D2.
Fig. 11 is a circuit diagram of another embodiment of the present invention and Fig. 12 shows working waveforms therefor, in which V_IN indicates a pulse input voltage; V_CLK the output voltage; V_C the switch control voltage; V_H the power source voltage for a high voltage circuit; and V_DD the power source voltage for a low voltage circuit (logic circuit). Q2 indicates an N channel MOS transistor for switching and Q3 an N channel MOS transistor disposed for controlling the switch so as to be in the conductive mode or in the cut-off mode. D is a diode which acts as the current path to the ground, when the source voltage of MOS transistor Q2 is made fall. Further it is also possible to make it work for protecting the gate of the MOS transistor. Q1 is a depletion type P channel MOS transistor.
Hereinbelow the working mode of the circuit indicated in Fig. 11 will be explained, referring to Fig. 12. By the conductive mode of the switch, which sets the control voltage V_C at the "L" level, since current is supplied from the depletion type MOS transistor to the gate of the MOS transistor Q2, the MOS transistor Q2 is in the ON state. For this reason, when a voltage pulse is applied to the input terminal V_IN, the source voltage (output voltage V_OUT) rises, following the rise of the drain voltage (input voltage V_IN). When the input voltage V_IN falls, since parasitic diode existing between the drain and the body of the MOS transistor Q23 is biased in the forward direction, the output voltage V_OUT falls also, following it. That is, it is possible to make the input voltage pulse pass-through to the output side. On the other hand, by the switch cut-off mode, where the control voltage V_C is at the "H" level, it is performed by the MOS transistor Q3 to draw-in the current holding the gate and the source of the MOS transistor Q2 at the ground level so that the MOS transistor is in the OFF state. For this reason, even if a voltage pulse is applied to the input terminal V_IN, the source voltage (output voltage V_OUT) doesn't follow the rise of the drain voltage (input voltage V_IN) to rise. That is, it is possible to cut off the input voltage pulse so as not to make it pass-through to the output side.
In Fig. 11, an insulated gate type bipolar transistor or an NPN transistor, with which a diode is connected in parallel, may be used for the switching MOS transistor Q2.
In the present embodiment a depletion type MOS transistor or a junction gate type transistor of depletion type is disposed between the drain and the gate as means for raising also the potential at the gate at the rise of the potential at the drain. For this reason an advantage can be obtained that a constant
current can be supplied, almost independently of the voltage between the gate and the drain of the MOS transistor. Although in the present invention a P channel depletion type MOS transistor is used, the same effect can be obtained also if an N channel depletion type MOS transistor, in which the gate and source are connected, is used.
Fig. 13 is a circuit diagram of another embodiment of the present invention. In the present embodiment a resistor R is used as means for raising the potential at the gate at the rise of the potential at the drain. A resistor made of polycrystalline silicon, which has a small parasitic capacitance and with which a high maximum applicable voltage can be easily realized, is suitable this resistor.
Fig. 14 is a circuit diagram of still another embodiment of the present invention. In the present embodiment a capacitor C is used as means for raising the potential at the gate at the rise of the potential at the drain. For this reason the present embodiment has an advantage that the driving current for switching on the MOS transistor Q2 with respect to those required in the embodiments indicated in Figs. 11 and 13.
Fig. 15 is a circuit diagram of still another embodiment of the present invention. In the present embodiment a diode D2 is used as means for raising the potential at the gate at the rise of the potential at the drain. In the case of the present embodiment the diode D2 is used as the capacitor described in the embodiment indicated in Fig 14. The case where the diode is used has an advantage that a high voltage input pulse can be dealt with, because it is easy to use a high voltage between the gate and the drain.
Fig. 16 is a cross-sectional view of the state, where the FET Q2 and the diode D1 in Fig. 9 are formed in an integrated circuit. As described previously, the diode D1 acts as a hold circuit for preventing that the output voltage V_OUT is lowered to a value below the ground voltage. In the circuit indicated in Fig. 16, the potential of P conductivity type semiconductor layers 1OO3 and 1006 for the component isolation is set at a value below the ground voltage so that even if the output voltage V_OUT is lowered below the ground voltage, the PN junction for the component isolation (between 1003 and 1004) is never biased in the forward direction.
Explaining more in detail, the present figure shows the cross-sectional view of the semiconductor device indicating the connecting point of V_SUB indicated in Figs. 9 and 10 and a wiring scheme of the power source. The semiconductor device indicated in the present figure has a structure, in which the semiconductor element is isolated from the P conductivity type semiconductor substrate 10O3 by a P conductivity type diffusion layer 1OO6. The left side of the present figure shows a vertical type MOS transistor, in which the source is an N conductivity type diffusion 1011; the body is a P conductivity type diffusion 1010, and the drain is an N conductivity type diffusion layer 107 and an N conductivity type buried layer 1004. On the other hand the right side shows the cross-sectional view of the diode D1 indicated in Fig 9, in which the anode is a P conductivity type diffusion layer 1010, and the cathode is N conductivity type diffusion layers 105, 1OO4 and 1007.
The cross-sectional view itself of the present semiconductor device is heretofore well-known. However a feature of the present structure consists in that the potential of the P conductivity type semiconductor layers 1006 and 103 for the component isolation is not equal to the ground voltage but it is set a value lower the ground voltage by V_L2, serving as V_SUB. For example, when the output voltage V_OUT is lowered below the ground voltage, this means that the cathode region (1005, 1004 and 1007) of the diode on the right side in Fig. 10 is lowered below the ground voltage.
In the case, where the potential of the P conductivity type semiconductor substrate is set at the ground voltage, as it is case by the prior art method, the PN junction between the P conducivity type layer 1003 and the cathode region described above is biased in the forward direction. Therefore current flows through the P conductivity type semiconductor layer 1003 for the component isolation and a parasitic bipolar transistor existing between adjacent elements is turned to the ON state, which causes an erroneous operation, which gives rise to a problem. This can be prevented owing to the present structure.
Further, since the junction capacity with respect to the substrate, i.e. referring to the example indicated in Fig. 10, the capacity between the drain region 1004 of the MOS transistor and the substrate 1003, is reduced, another effect can be also obtained that the elements isolated by the PN junction can be driven with a high speed.
In order to set the voltage of the P conductivity type semiconductor layer for the component isolation at a value lower than the ground voltage by V_L2, an external power source may be used. However, by using the negative voltage circuit as indicated in Fig. 10, the object of obtaining the voltage V_SB Of the P conductivity type semiconductor layer for the component
isolation can be achieved without using any external negative voltage source.
Fig. 17 is a cross-sectional view of another embodiment of the semiconductor device described above by the method of applying the substrate voltage and a wiring diagram of the power source.
The semiconductor device indicated in the present figure is a semiconductor device, in which a vertical type MOS transistor (on the left side in the figure) in which an N conductivity type substrate acts as the drain, and a vertical type MOS transistor having a structure similar to that indicated on the left side in Fig. 10, in which the component isolation is effected by a P conductivity type epitaxial layer 10O2 and a P conductivity type diffusion layer 1006, coexist. The figure shows also the method of applying the substrate voltage therefor.
In the present figure, as described above, since the P conductivity type epitaxial layer 1002 and the P conductivity type diffusion layer 1006 act as the P conductivity type semiconductor layer for the component isolation, wiring is effected so as to set the potential of this region at a value below the ground voltage. In the present example of structure a parasitic bipolar transistor, in which an N conductivity type layer 1000 serves as the collector; the P conductivity type layer 102 as the base; and an N conductivity type layer 1004, is originally apt to work.
As described above, when generally the potential of the P conductivity type semiconductor used for the component isolation in a PN junction isolation type semiconductor integrated circuit device is lowered below the ground voltage, even if the potential at the output terminal is lowered below the ground voltage, depending on the state of the load, it is possible to prevent that the parasitic element is turned to the ON state by the fact that the PN junction for the component isolation is biased in the forward direction, which gives rise an erroneous operation, by setting the potential of the P conductivity type semiconductor layer used for the component isolation at a still lower value and further another effect can be obtained that the element can be driven with a high speed.
Next an example, in which present switching circuit is used in a display device, is explained, referring to Figs. 18 and 19. In the present embodiment discharge cells are used as an example of the capacitive load.
In the case where the discharge cells are driven by image signals, the discharge cells are arranged vertically and horizontally, as indicated in Fig. 18, and the image signals are applied to electrodes thereof. One of the discharge cells used in the present embodiment has a 3-electrode structure, as indicated in Fig. 18, and consists of an anode electrode A, a cathode electrode K and a sub-anode electrode SA. In the present embodiment a case where the discharge cells are arranged in 3 lines and 3 rows will be explained.
The basic construction of the display device consists of an anode driving system feeding the anode electrode A, a scanning signal generating block 614 for generating signals applied to the cathode electrode K and a display signal generating block 6l3 for generating display signals applied to the sub-anode electrode SA. Here the anode driving system consists of an energy recovery circuit 600, which generates a high voltage pulse V_TP (same wave-form as V_IN) and at the time recovers electric power, a group of switching circuits 60 having a pulse distributing function for feeding each of lines for the anode electrode and a pulse-gating generating circuit 615 for giving a pulse distributing signal.
In general, in the case where a capacitive load is driven, since the load capacity and stray capacity of the circuit are charged up at the rise of the high voltage pulse, transient current flows. Other hand, also at the fall of the high voltage pulse, since electric charge stored in the capacities described above is discharged, transient flows. Since the discharge cells as a load constitute a capacitive load, transient current flows and electric power consumption is very great.
In order to reduce electric power consumed in the display device, as described above, generally an energy recovery circuit is used. Here the energy recovery circuit is a circuit consisting of a coil, a capacitor and a switching element, which stores the electric charge in the capacitor described above without consuming it n the resistor.
In order to recover the electric power with a high efficiency, ii is necessary to dispose an energy recovery circuit and to recover the high voltage signal from each of the anode electrode A or distribute it to each of the anode electrodes A. For this purpose a pulse distributor is necessary, which can recover and distribute the high voltage signal in both the directions. The switch described above according to the
present invention can be used for this purpose, as described below.
In the example construction indicated in Fig. 18, in order to reduce the electric power of the signal applied to the anode electrode A, an energy recovery circuit is used and the group of switching circuits are disposed in the stage following it. Hereinbelow a case where the discharge cells are turned on by image signals will be explained in detail.
In the case where the discharge cells are turned by the image signal, in general a method, by which the luminance is displayed while transforming it into the time duration, e.g. the time sharing within a field time method is used. By this method one field is divided into e.g. 7 sorts of period, the ratio of the durations being selected so as to be 2⁰:2¹:2²:2³:2⁴:2⁵:2⁶ (0 to 6 bits). It is possible to display 2⁷ = 128 gray levels by combining the seven sorts of period.
Fig. 19 shows a time chart based on this method. In order to turn on the discharge cells, relevant voltages should be applied to the anode electrode A, the cathode electrode K and the sub-anode electrode SA. Further, in order to represent luminance information, it is necessary to apply townsend pulses V_T to hold the discharge at the anode electrode A. The number of the townsend pulses is assigned according to the time sharing within a field time described above.
Fig . l9 shows wave-forms V_AT1 to V_AT3 representing the assigned period described above. Here 0^H to 24^H within one field are indicated. Here 1^H corresponds to 63.5 x 10^-6 sec.
Hereinbelow a period T_D in Fig. l9 will be explained.
In this period of time the discharge cell indicated in Fig. 18 is in the state, where the bit 2 information (b2 of Fig. 19) is turned on. That is, the first line A1 of the anode electrode A is set at the selected state by V_A1 and when a V_S1 pulse voltage 70 is applied to the first row S_A1 of the sub-anode electrode SA, a discharge cell 604 is turned on. However, it is supposed that a pulse voltage VK1 given to the first line K1 is applied to the cathode electrode K.
When the procedure proceeds in the same way according to the time chart indicated in Fig 19 such as the second line and the second row, the third line and the third row, and so forth, discharge cells 604, 605, 606, 608 and 6l1 are turned on by applied pulse voltages 71, 72, 73 and 74 on the sub-anode SA, voltage pulse series V_T1, V_T2 and V_T3 on the anode electrode A, and voltage pulse series V_K11, V_K12 and V_K13 on the cathode K. This state is indicated by hatching in Fig. 18.
The display signal generating block 613 generates voltage pulses V_S1, V_S2 and V_S3, responding to the luminance signal of the image. On the other hand the scan signal generating block 614 generates voltage pulses V_K1 V_K2 and V_K3 applied to different lines of the cathode electrode K. Further voltage pulses V_A1, V_A2 and V_A3 in Fig. 19 are generated the pulse-gating generating circuit 615. The energy circuit 600 performs the electric energy recovery and the generation of the high voltage pulse in Fig. 19 (V_TP is same as V_IN).
The group of switching pulse 60 extracts pulse series V_TP coming successively from the energy recovery circuit 600, responding to pulse-gating pulses V_A1 to V_A3 to obtain townsend pulses V_T1 to V_T3. A switching circuit 601 in the group of switching circuit 60 receives the high voltage pulse V_TP from the energy recovery circuit 600 through a terminal 62. It receives at the same time the pulse-gating signal on a control line C1 of the pulse-gating signal generating circuit through a terminal 61. Then it performs the control of conduction or cut-off for the high voltage pulse V_TP to output the townsend pulse V_AT1 on an output line A1.
Switching circuit 6O2 and 603 in the group of switching circuits 60 work in the same way.
Consequently the relevant waveforms indicated in Fig. 19 are applied to the anode electrode A and the cathode electrode K. In this way the selected discharge cells are turned on, responding to the signal applied to the sub-anode electrode SA and thus it is possible to reproduce the image on the display device.
Since the energy recovery circuit requires an inductor, it is generally difficult to form an integrated circuit and it is not desirable to dispose an energy recovery circuit for every anode electrode at fabricating the anode driving circuit in the form of an IC. Contrarily thereto, in the case where there are disposed switching circuit according to the present invention, since only one energy recovery circuit is sufficient, an effect is obtained that anode driving circuit can fabricated more easily in the form of an IC.
Further, although in the embodiment described above explanation has been made for the case where discharge cells are used as display elements, it is a matter of course that the switching circuit according to the present invention can be used also for driving other display elements, e.g. panels constituted by EL (electroluminescence), liquid crystal, etc., driven by the method, by which pulse voltages are applied time sequentially and intermittently thereto.
Contrarily to the fact that in the above embodiment a switching circuit controlling the conduction and cut-off of the high voltage positive pulse signal has been described, hereinbelow an embodiment of a switch controlling the conduction and cut-off of a high voltage negative pulse signal.
Fig. 20 is a circuit diagram showing an embodiment of the present invention, in which Q2 is an N channel MOS transistor, whose source is connected with the body, and in which the input signal voltage V_IN is given to the source side and the output signal voltage V_OUT is taken out from the source side. Q1 indicates an N channel MOS transistor, which is used as a current drawing-in element, when the transistor Q2 is set forcedly sat the OFF state. D1 is diode used for protecting the gate of the transistor Q2, by means of which it is possible set the values of the voltage amplitude of V_IN and V_OUT below the gate withstand voltage for the transistor Q2. It is desirable that Dl is a Zener diode, whose break down voltage is about 5 to 30 V. R1 is resistor used for suppressing the intensity of the current flowing through the transistor Q1 and it is unnecessary, in the case where electric power consumption due current flowing through the transistor Q1 produces no problem.
Fig. 21 is a time chart showing the method for driving the circuit indicated in Fig. 20. Since there exists a parasitic diode between the drain of the transistor Q2 and the body, in which the drain acts as the cathode and the body acts as the anode, when the input signal voltage V_IN having an amplitude V_H is given thereto, in the high voltage state of V_IN the output signal voltage V_OUT is also in the high voltage state, independently of the state of the control signal voltage V_C. When the input signal voltage V_IN falls, if the control signal voltage V_C is in the low voltage state (transistor Q1 is turned off), since the voltage V_X has a tendency to be maintained, the transistor is turned to the ON state and the output signal voltage V_OUT also falls. However, when the input signal voltage V_IN falls, if the control signal voltage V_C is in the high voltage state (transistor Q1 is turned on), since the transistor Q2 is turned forcefully to the OFF state, the output signal voltage V_OUT holds almost the high voltage state. Consequently it is possible to whether the input signal voltage V_IN and the output signal voltage V_OUT pass-through or cut-off, depending on the value of the control signal Voltage V_C. In this way it can function a switching circuit for controlling the falling of output voltage with respect to the input pulse inputted through the input terminal V_IN.
Fig. 22 is also another time chart showing the method for driving the circuit indicated in Fig. 20. By the present driving method, only during the period of time, where it is not desired to fall the output signal voltage, the control signal voltage V_C is turned to the high voltage state in synchronism with the fall of the input voltage signal V_IN. In this way a loss current flowing through the transistor Q1 due to the control signal voltage V_C is reduced, which can decrease the electric power consumption of the circuit.
Fig. 23 is a circuit diagram showing another embodiment of the present invention. In the present embodiment a capacity C1 is added between the V_X section and the high voltage power source V_H in the circuit of the embodiment indicated in Fig. 20 so that when the transistor Q1 is in the OFF state and when the input signal voltage V_IN falls, the transistor Q2 is more easily turned on. Although in the present embodiment the capacity C1 is located between the V_X Section and the high voltage power source, the same effect can be obtained also by locating it between the V_X section and the ground or the V_C section, etc.
Fig. 24 is a circuit diagram of still another embodiment of the present invention. In the present embodiment a diode D2 is added to the diode D2 in the circuit of the embodiment indicated in Fig. 20, the former being connected in series in the reverse direction with the later. For this reason, even if the driving method indicated in Fig. 21 is used, it is possible to eliminate the loss current flowing through the transistor Q1, when the control signal voltage V_C is in the high voltage state.
Fig. 25 is a circuit diagram showing still another embodiment of the present invention. In the present invention a resistor R2 is used instead of the diode D1 in the circuit of the embodiment indicated in Fig. 20. For example, in the case where a polycrystal-line silicon resistor is used for the resistor R2, it is possible to reduce the occupied area and the parasitic capacity with respect to those of the diode. However, when the resistance of the resistor R2 is too great, it cannot serve as a protection for the gate of the transistor Q2 and on the contrary, when it too small, it is not possible to turn the transistor to the ON state, when the input signal voltage V_IN falls. For this reason attention should be paid to the setting of the resistance.
Fig . 26 is a circuit diagram showing still another embodiment of the present invention. Contrarily to the fact that in the embodiment indicated in Fig. 20, etc., even if it is tried to hold the output signal voltage V_OUT, when the input signal voltage V_IN falls, a voltage drop of about 10% of the voltage amplitude of the input signal voltage V_IN takes place in the output signal voltage V_OUT, in the present embodiment two P channel MOS transistors Q3 and Q4 are connected to form a current mirror circuit and the current flowing through the transistor Q3 is controlled by an N channel MOS transistor Q5 in order to prevent this voltage drop and to hold the high voltage state. In order to drive the present circuit, the same driving method as those indicated in Figs. 21 and 22 can be used, if a first control signal voltage V_C1 and a second control signal voltage V_C2 to form the control signal voltage VC.
Fig. 27 is a circuit diagram showing still another embodiment of the present invention. In the present embodiment P channel MOS transistors Q6 and Q7 connected to form a current mirror and an N channel MOS transistor Q8 are used as means for supplying current to the gate of the transistor Q2 to set at the ON state. In the present embodiment, since the output signal voltage can rise in the state where the transistor Q2 is in the ON state, it can be driven without biasing parasitic diode between the drain of the transistor Q2 and the body in the forward direction. For this reason it is possible to prevent the lowering in the switching speed of the transistor Q2 due to the accumulation of minority carriers. Further, since the transistor Q2 can be set in the ON state, by setting the high voltage power source V_H at a value higher than the maximum voltage V_DH of the input signal voltage V_IN, even if the input signal voltage V_IN is in the high state, it is possible to transfer small signals from the input terminal V_IN to the output terminal V_OUT over a wide voltage range. Further a P channel MOS transistor Q9 and an N channel MOS transistor constitute an inverter and if a first control signal voltage V_C1 and a third control signal voltage V_C3 are connected to form the control signal voltage V_C, the same driving method as those indicated in Figs. 21 and 22 can be used.
V_L represents the power source voltage for the signal line.
Fig. 28 is a circuit diagram showing still another embodiment of the present invention. The present invention has a structure having the circuit functions indicated in Figs. 26 and 27. The high voltage power source voltages V_H1 and V_H2 may be set at a same level, but by setting one of the high voltage power source voltages V_H2 at a value higher than the other V_H1 by about 5 to 20 V, it is possible also to set the transistor Q2 at the ON state, when the input signal voltage V_IN is in the high potential level. If three control signal voltages V_C1, V_C2, V_C3 are connected, the same driving method as those indicated in Figs. 21 and 22 can be used.
Fig. 29 is a circuit diagram showing still another embodiment of the present invention. The present embodiment is a switching circuit useful, in the case where both the input signal voltage V_IN and the output signal voltage V_OUT are used at levels below the gate withstand voltage.
Fig. 30 is a truth-false table for the circuit indicated in Fig. 29. In the case where both the control signal voltage V_C and the input signal voltage V_IN are in the low voltage state, the output signal voltage V_OUT holds the state of the preceding output signal voltage V_OUT.
Fig. 31 is a circuit diagram showing still another embodiment of the present invention. The present embodiment is also a switching circuit useful for the case where both the input signal voltage V_IN and the output signal voltage V_OUT are used below the gate withstand voltage.
Fig. 32 is a truth-false table for the circuit indicated in Fig. 31. In the case where both the control signal voltage V_CON and the input signal voltage V_IN are in the low voltage state, since the P channel MOS transistor Q3 is turned on, the output signal voltage V_OUT is in the high voltage state.
Fig. 33 is a circuit diagram showing still another embodiment of the present invention. The present embodiment is a switching circuit, in which the N channel MOS transistor Q2 is replaced by an NPN transistor Q2 and a diode DQ1 and the N channel MOS transistor Q1 is replaced by an NPN transistor Q1. In this way the circuits described in the above embodiments can realize circuits having the same effects by replacing the MOS transistor Q2 by a bipolar transistor, with which a diode is connected in parallel.
Fig. 34 shows another example of the switch for the negative high voltage input signal. The switching element Q2 is a P channel FET, in which the drain is the input signal terminal and the source is the output terminal. A gate bias is given between the source and the gate and further a diode D1 for the protection against excessive voltage is connected. The circuit for driving the gate of the transistor Q2 is an N channel FET Q1. A resistor R1 for limiting current is connected with the source of the FET Q1. Now the working mode of the circuit indicated in Fig. 34 will be explained, referring to a time chart indicated in Fig. 35. V_IN represents a negative high voltage input signal and V_C an input signal for controlling the transistor Q1 indicated in Fig. 34. When the input signal VC is at the "L" level, since the transistor Q1 is turned off, no potential difference is produced between the gate and the source and thus the transistor Q2 is turned off. For this reason, if the voltage of the input signal V_IN varies, the output signal V_OUT is kept in the high potential state. On the other hand, when the control signal V_C is at "H" level, the transistor Q1 is turned on. For this reason the gate voltage of the transistor Q2 falls, and a voltage is applied between the gate and the source. In this way the transistor Q2 is turned to the ON state and a negative high voltage pulse is produced in the output signal V_OUT, as indicated in Fig. 35. Here the diode D1 acts as a protection diode between the gate and the source of the transistor Q2. The connection of the two diodes D1 and D2 in series indicated in Fig. 24, the connection of the resistor R2 indicated in Fig. 25, the addition of the function of holding the output voltage indicated in Fig. 26, etc. can be applied to the circuit indicated in Fig. 34, as they are and are included in the present invention.
Fig. 36 is a block circuit diagram illustrating an embodiment of the circuit construction according to the present invention. The present embodiment is so constructed that it is determined by a switching circuit SW opened or closed according to the present invention whether a pulse outputted by a pulse generator should be transmitted to each of more than 2 loads. The opening and shutting of the switching circuit is effected on the basis of control signal voltages VC(1), VC(2), ---, VC(N) transmitted by a driving circuit. The driving circuit transfers data inputted through a data input terminal in a shift register by using a clock signal to subject them to a serial-parallel transformation and carries out a function to transmit them simultaneously to different switching circuits as the control signal voltage while synchronizing them by means of a latch signal.
In addition, in the circuit indicated in Fig. 36, in the case where the loads are capacitive, the pulse generating circuit can be realized by using an energy recovery circuit (JP-A-61-132997). In this case the electric power transferred from the pulse generator to the loads is returned again from the loads to the pulse generator. In this way a capacitive load driving device of low electric power consumption can be realized.
Fig. 37 is a circuit block diagram showing an embodiment, in which the present invention is applied to matrix display elements. The present embodiment shows an example, in which a method for driving a matrix display device using switching circuits according to the present invention is used for driving the display device described in Japanese patent application No. 50-113686 as an example.
As indicated in Fig. 37, a discharge cell consists of three electrodes, i.e. an anode, a cathode and an auxiliary anode. While discharge between the anode and the cathode is a display discharge, discharge between the auxiliary anode and the cathode is an auxiliary discharge, which is not observed from the exteriors. A cathode resistor R_K is disposed, in order to prevent that the display discharge and the auxiliary discharge take place simultaneously. Denoting the anode voltage by V_A, the cathode voltage by V_K and the auxiliary anode voltage by Y_SA, in order to give rise to the display discharge, the following procedure is necessary. That is,

(1) start the auxiliary discharge by setting the auxiliary anode voltage V_SA at the high level and the cathode voltage V_K at the low level, and then
(2) stop the auxiliary to start the display discharge by setting the auxiliary anode voltage V_SA at the low level, the cathode voltage V_K at the low level and the anode voltage at the high level.

When in step (2) the auxiliary anode voltage V_SA remains at the high level, even if the cathode voltage V_K remains at the low level and the anode voltage V_A is turned to the high level, the auxiliary discharge is not stopped and the display discharge cannot be started.
Utilizing the feature described above of the discharge cell, it is possible to make an arbitrary discharge cell on a display matrix perform the display discharge by using a positive pulse for the anode voltage V_A and a negative pulse for the cathode voltage V_K as the scan signal and a negative pulse for the auxiliary anode voltage V_SA as the image signal. In the case of the present embodiment it is possible to reduce the electric pulse consumption in the anode driving circuit and the auxiliary anode circuit with respect to that required according to the prior art technique. A driving circuit (A) incorporating positive pulse switching circuits as indicated in Fig. 1 is used as the switching circuit for the anode driving circuit; a driving circuit (B) incorporating negative pulse switching circuits as indicated in Fig. 20 is used as the switching circuit for the auxiliary anode driving circuit; and a prior art push-pull type driving circuit (C) is used for driving the cathode. In this way it is possible to realize a display device permitting low electric power consumption drive. Further the driving method described in the present embodiment can be applied to general capacitive load driving devices such as plasma displays, EL (electroluminescence) displays, vacuum fluorescent displays, piezo electric devices, etc.
Fig. 38 is a diagram showing an example of the circuit for driving a plurality of electrodes according to the present invention, in which switching circuits are inserted between an energy recovery circuit and the electrodes, charging and discharging energy being recovered through these switching circuits.
At first a switching circuit 1101, a diode 1102, and an inductor 1103 are connected in series to a power supply or a charge supplying source 1111 which is formed by a capacitor element storing charges therein. This series circuit plays a role for supplying charges to the electrodes (producing voltage rise at the electrodes). The output terminal 1116 of the inductor is connected with first unidirectional switches, i.e. series circuits, each of which consists of a diode 1104 and an FET 1105, corresponding to a plurality of electrodes 1112 of display elements 604, 607, 610..., respectively. The output terminal 1116 of the inductor 1103 is connected further with a switching circuit 1113 for holding the terminal voltage at the level of a high voltage power supply 1115. The output of each of these first unidirectional switches (diode 1104 and FET 1105) is connected e.g. with one of the plurality of address electrodes 1112 of an AC type plasma display.
On the other hand, a circuit for recovering electric charge stored at the electrodes 1112 is formed in a manner that the output terminal 1117 of a series circuit of a switching circuit 1110, a diode 1109 and an inductor 1109, which is connected with the charge supplying source 1111, is connected with second unidirectional switches, i.e. series circuits, each of which consists of an FET 1106 and a diode 1107. Here the output terminal 1117 of the inductor 1108 is connected also with a switching circuit 1114 for holding the terminal voltage at the level of a low voltage power supply (here ground level). The output of each of these second unidirectional switches (FET 1106 and diode 1107) is connected with one of the electrodes 1112 (here address electrodes 1112 of the AC type plasma display).
Now current path for charging and discharging the electrodes of the display elements will be explained, using Fig. 38.
At first, the current path, when the electrodes are being charged, will be explained. Now it is supposed that one of the plurality of electrodes is at the low level (ground level). In this case, the output terminal 1116 falls instantaneously to the low level by switching-on the FET 1105 corresponding thereto. Next, when the switch circuit 1101 is turned on, charge stored in the charge supplying source 1111 is transferred into the unidirectional switches (diodes 1104 and FETs 1105) through the switching circuit 1101, the diode 1102 and the inductor 1103, by which the electrode 1112 of the display elements 604, 607, 610 are charged. According to the principle of the energy recovery circuit, the voltage of the charge supplying source 1111 is equal to a half of that of the high voltage power supply V_H, and the voltage rise reaches the high voltage level V_H from the ground level owing to resonance of the inductor 1103 and the electrodes serving as a capacitive load. As described above, when the electrodes are being charged, electric charges flow from the charge supplying source 1111 into the electrodes 1112 through the inductor 1103 and the first unidirectional switches (diodes 1104 and FETs 1105). When the voltage at the output terminal of the inductor 1103 is raised up to the high voltage level V_H, the circuit 1113 for holding the terminal voltage at the level of the high voltage power supply is switch-on and holds the voltage of the terminal 1116 at the high voltage level V_H.
When some of the electrodes are not to be charged, the FETs 1105 corresponding thereto are switched-off. Since these first unidirectional switches include the diodes 1104, there is no reverse current from the electrodes 1112 to the terminal 1116.
Next the current path, when electric charge stored in the electrodes 1112 of the display elements is released, will be explained. Now it is supposed that some of the plurality of the electrodes are at the high voltage level (voltage level V_H). At this time, when the FETs 1106 corresponding thereto are switched-on, current flows into the terminal 1117 through the FETs 1106 and the diodes 1107 and the voltage at the terminal 1117 reaches instantaneously the high voltage level V_H.
Then, when the switching circuit 1110 is switched-on, electric charge stored in the electrodes 1112 flows into the charge supplying source 1111 through the FETs 1106, the diodes 1107, the inductor 1108, the diode 1109, and the switching circuit 1110. The voltage of the electrodes 1112 is lowered to the low voltage level (ground level) owing to resonance of the inductor 1108 and the electrodes which are capacitive loads. At this time, the circuit 1114 for holding the electrodes at the low voltage level is turned on to thereby hold the voltage thereof at the low voltage level. In this ways electric charge stored in the electrodes is recovered in the charge supplying source 1111 through the second unidirectional switch (the FET 1106 and the diode 1107) and the inductor 1108.
When it is desired that the voltage of the electrodes is held at the high voltage level (V_H level), the FETs 1106 are switched-off. Also in this case, since the second unidirectional switch includes the diode 1107, no current flows into the terminal 1117.
Now an example of another embodiment of the present invention is shown by using Fig. 40. Fig. 40 is a circuit diagram, in which the first unidirectional switch and the second unidirectional switch are constructed by using bipolar transistors 1301 and 1302, respectively. Since the FETs 1105 and 1106 have stray diodes, in order to make them unidirectional, the diodes 1104 and 1107 are necessary. On the contrary, since there exist no stray diodes in the bipolar transistors 1301 and 1302, it is possible to realize unidirectional switches by using them only.
Next an example of still another embodiment of the present invention is shown by using Fig. 41. Fig. 41 shows a circuit, in which each of the electrodes 1112 of the display elements 604, 607, 610 is connected with voltage hold circuits 1401 and 1402 holding them at the high voltage level V_H and the low voltage level (ground level), respectively, and the voltage hold circuits (corresponding to the circuits 1113 and 1114 in Fig. 38) in the energy recovery circuit are removed. In the operation of the circuit indicated in Fig. 38, when the voltage level of the electrodes doesn't vary, either one of the FET 1105 and the FET 1106 remains in the state where it is switched-off. However, as explained with respect to Fig. 38, the voltage level of the terminal 1116 or 1117 is changed instantaneously into the low voltage level or the high voltage level. At this time, since a reverse voltage is applied to the diodes 1104 or 1107, they are not conductive and the electrodes are temporarily placed in a floating state when the voltages of the terminals 1116 and 1117 vary instantaneously. In such a floating state, there may be a case where the voltage of the electrodes varies for some reason. In order to prevent such a variation, in the circuit construction indicated in Fig. 41, the voltage hold circuits 1401 and 1402 are connected with each of the electrodes. In this way, it is possible to drive the electrodes at stable working voltages by holding them at the low voltage level or the high voltage level when the voltage of the electrodes doesn't vary.
Fig. 42 is a diagram showing an embodiment, in case where the inductance value is controlled according to the present invention. A first unidirectional switch (the diode 1104 and the FET 1105) and a second unidirectional switch (the switching FET 1106 and the diode 1107) are connected with corresponding one of the electrodes. The number of electrodes driven by the energy recovery circuit varies, depending on the number of these first and second unidirectional switches switched-ON. Consequently, in this case, load capacitance seen from the energy recovery circuit varies. At that time, the resonance frequency produced by the inductor and the electrodes varies, and hence the rise time and the fall time of the high voltage pulse applied to the electrodes vary. In such a case, when the present invention is applied to address electrodes of an AC type plasma display, for example, if there are different rise times and fall times of the high voltage pulse, this may cause an erroneous operation. Therefore the number of the first and second unidirectional switches to be switched-on is previously detected and the inductance value of the energy recovery circuit is controlled depending on the detected number thereof. Fig. 42 is a diagram indicating an example of the circuit construction for realizing such a control.
In the circuit indicated in Fig. 42, a plurality of series circuits (in this example three series circuits 1501, 1502r 1503) each formed by a switching circuit 1101, a diode 1102 and an inductor 1103 are connected in parallel. Further, a plurality of series circuits (in this example three series circuits 1504, 1505, 1506) each formed by a switching circuit 1110, a diode 1109 and an inductor 1108 are connected in parallel, Here the inductance values of the inductors 1103 and 1108 are different among the parallel circuits. For example, if 3 inductance values form a binary system (binary values), it is possible to control the inductance value of the whole circuit in 7 stages by on - off controlling the 3 switching circuits 1101 or 1110. Now, supposing that the total number of the plurality of electrodes 1112 is N, the number of the unidirectional switches switched-on is set at a value closest to a multiple of N/7 and the inductance value is controlled depending thereon. Since the resonance frequency of the inductor and the electrodes is defined by the root of a product of inductance and capacitance, the value of the product of inductance and capacitance is kept almost constant by varying the inductance value in these 7 stages, in order to keep the resonance frequency almost constant. In this way, even if an arbitrary number of unidirectional switches are switched-on, it is possible to obtain a pulse wave-form having almost constant rise and fall time periods of the high voltage pulse by detecting the number of unidirectional switches switched-on and controlling the inductance value of the energy recovery circuit depending on the detected number as described above. Although 3 series circuits, each of which consists of the switching circuit 1101, the diode 1102 and the inductor 1103, are connected in parallel in the example of Fig. 42, the number of the parallel circuits is determined by a tolerable error region of the rise and fall time periods of the high voltage pulse, and so the number of the parallel circuits is not restricted to 3.
Now an example of the method for controlling the unidirectional switches will be explained by using Figs. 43 and 44.
Fig. 43 indicates an example of the circuit of a control portion for the FETs 1105 and 1106 in the unidirectional switches. Fig. 43 shows an example in which N channel MOS FETs are used for the FETs 1105 and 1106. A resistor 1604 and a protection diode 1603 are connected between the gate and the source of the FET 1105 and the gate of this FET is driven by a constant current source circuit formed by a resistor 1601 and a PNP transistor 1602. On the other hand, a diode 1605 is connected between the gate and the source of the FET 1106 and the gate of the FET 1106 is driven by an FET 1606.
Fig. 44 shows voltage waveforms at the respective input terminals of the circuit indicated in Fig. 43 and a wave-form of the voltage applied to the electrodes (A) of Fig. 44 indicates an input voltage wave-form for the first unidirectional switch (voltage wave-form at the terminal 1116 in Fig. 43); (B) of Fig. 44 an input voltage wave-form for the second unidirectional switch (voltage wave-form at the terminal 1117 in Fig. 43); (C) of Fig. 44 a wave-form of a signal inputted to the gate 1615 of the voltage hold circuit (1113 in Fig. 43) for holding the terminal 1116 at the level of the high voltage power supply; (D) of Fig. 44 a wave-form of a signal inputted to the gate 1616 of the voltage hold circuit (1114 in Fig. 43) for holding the terminal 1117 at the level of the low voltage power supply; (E) of Fig. 44 a wave-form of a signal at the base of the PNP transistor 1602 in the constant current source circuit in Fig. 43; (F) of Fig. 44 a wave-form of a signal inputted to the gate 1613 of the FET 1606 in Fig. 43; and (G) of Fig. 44 a wave-form of the voltage applied to the electrode (1112 in Fig. 43).
Next a method for controlling the circuit indicated in Fig. 43 will be explained by using the input voltage wave-form, the different control voltage wave-forms, and the output wave-form in periods of time from I to XIII in Fig. 44. At first, it is supposed that the electrode 1112 is at the low voltage level in the period of time I. As indicated in (E) of Fig. 44, in the period of time II, the base 1612 of the transistor 1602 in Fig. 43 is turned to the Low state. At this time, the transistor 1602 is switched-on and current flows from the high voltage power supply V_H into the gate of the FET 1105 through the resistor 1601 and the transistor 1602. Thus a voltage is produced between the gate and the source of the FET 1105 across the resistor 1604, and the FET 1105 is switched-on. Since the voltage of the electrode 1112 was at the low voltage level in the period of time I and the FET 1105 is switched-on in the period of time II, as indicated in (A) of Fig. 44, the voltage wave-form at the input terminal 1116 is instantaneously lowered to the low voltage level in an extremely short part at the beginning of the period of time II. Next, since the energy recovery circuit (switching circuit 1101 in Fig. 38) is switched-on in the period of time II, the voltage at the input terminal 1116 rises in a sinusoidal fashion. Here the voltage at the input terminal (electrode) 1112 rises also in a sinusoidal fashion due to the fact that the diode 1104 and the FET 1105 are switched-on.
On the other hand, as indicated in (F) of Fig. 44, the input signal at the gate 1613 of the FET 1606 is turned to the high state in the period of time II. At this time the FET 1606 is switched-on and the voltage at the gate of the FET 1106 is lowered to the low voltage level. Now, since the voltage wave-form at the input terminal 1117 is raised instantaneously to the high voltage level (explained later) and falls thereafter in a sinusoidal fashion, as indicated in (B) of Fig. 44, no voltage is produced between the gate and the source of the FET 1106 and thus the FET 1106 is switched-off due to the fact that the voltage at the gate of the FET 1106 falls also at the same time.
Next, in the period of time III, since the voltage hold circuits 1113 and 1114 are switched-on, the voltage at the input terminal 1116 is held at the high voltage level V_H, while the voltage at the input terminal 1117 is held at the low voltage level. Here, in the period of time III, since the FET 1105 is switched-on and the FET 1106 is switched-off, the voltage at the electrode 1112 is at the high voltage level V_H.
Next, in the period of time IV, the voltage at the input terminal 1116 is lowered once to the low voltage level as indicated in (A) of Fig. 44, but charge stored in the electrode 1112 flows never reverse into the input terminal 1116 even if the FET 1105 is switched-on due to the fact that a reverse voltage is applied to the diode 1104. Further, although the voltage at the input terminal 1117 is raised once to the high voltage level as indicated in (B) of Fig. 44, but no current flows from the electrode 1112 into the input terminal 1117 due to the fact that the FET 1106 is switched-off. As described above, in the period of time IV, the electrode is in a floating state and since the voltage was at the high voltage level in the period of time III, this voltage of the electrode is maintained in the period of time IV.
The operation in the period of time V is identical to that in the period of time III and the voltage at the electrodes is held at the high voltage level.
Next, in the period of time IV, since the signal at the base 1612 of the transistor 1602 is at the high state as indicated in (E) of Fig. 44, the transistor 1602 is switched-off and no current flows through the gate of the FET 1105. Consequently since no current flows through the resistor 1604, the voltage at the gate of the FET 1105 is same as that at the source thereof and the FET 1105 is switched-off. Further, in the period of time VI, the signal at the gate 1613 of the FET 1606 is at the Low state as indicated in (F) of Fig. 44. Consequently the FET 1606 is switched-off. Now, when the voltage at the input terminal 1117 is raised to the high voltage level and lowered thereafter in a sinusoidal fashion as indicated in (B) of Fig. 44, the diode 1107 is turned-on. At this time, the voltage at the source of the FET 1106 is lowered also in a sinusoidal fashion. Here a voltage is produced between the gate and the source of the FET 1106 by the diode 1605 and the FET 1106 is switched-on. Consequently charge stored in the electrode 1112, which was at the high voltage level in the period of time V, flows out through the FET 1106 and the diode 1107 in the period of time VI and hence the voltage at the electrode 1112 is lowered in a sinusoidal fashion to the low voltage level.
Next, in the period of time VII, since the FET 1105 is switched-off and the voltage between the gate and the source of the FET 1106 is maintained by the diode 1605, the FET 1106 is kept in an on state and so the voltage of the electrode 1112 is held at the low voltage level.
Since operation in the periods of time IX, X and XI is identical to that explained for the periods of time II, III, VI and VII, explanation thereof will be omitted.
Next, in the period of time XII, the voltage at the input terminal 1116 is once lowered to the low voltage level and raised thereafter in a sinusoidal fashion to the high voltage level. However, since the FET 1105 is switched-off, no current flows into the electrode. Further the voltage at the input terminal 1117 is once raised to the high voltage level and lowered thereafter in a sinusoidal fashion, but since a reverse voltage is applied to the diode 1107, no current flows from the input terminal 1117 into the electrode. Consequently, in this period of time XII, the electrode is in a floating state and since the voltage at the electrode was at the low voltage level in the period of time XI, this low voltage is maintained at the electrode.
Since operation in the period of time XIII is identical to that explained for the period of time VII, explanation thereof will be omitted.
It was stated that the voltages of the input terminals 1116 and 1117 are turned instantaneously to the low voltage level or the high voltage level in the periods of time II, IV, VI, VII, X, and XII. This is because if either one of the first unidirectional switches and the second unidirectional switches connected with a plurality of different electrodes is switched-on, charge stored in the electrodes flows into the input terminal 1116 or 1117. Although no such instantaneous variation is produced when all the unidirectional switches are switched-off, nevertheless a desired voltage can be obtained at the electrodes.
The gate control circuits for the FETE 1105 and 1106 indicated in Fig. 43 stated previously are only an example and the present invention is not restricted to the gate driving circuits indicated in Fig. 43. For example, the gate control circuit may be formed by using level shift circuits, photocouplers, or the like.
As described above, since the width of pulses applied to the electrodes can be controlled arbitrarily, the switch circuit according to the present invention is capable of performing energy recovery with low electric power consumption and with a simple structure.
Moreover, hereinafter, detailed description of other embodiments in accordance wit the present invention, i.e., a driving method and a driving circuit for driving, in particular, the PDP (plasma display device) and a display apparatus using thereof, will be given by referring to attached drawings.
First of all, an explanation on the construction of a PDP will be given by referring to attached Figs. 52 and 53.
In Fig. 52 showing the construction of the PDP in an exploded perspective view, a reference numeral 800 denotes a X electrode, 801 a Y electrode, 802 an address electrode (A electrode), 803a rib, 804, 805 and 805 respective phosphors of R (Red), G (Green) and B (Blue), 810 a glass plate, 811 a substrate, and 812 an dielectric layer.
In the same figure of the construction of the PDP, a discharge space and electrodes are defined between two pieces of the glass plates, and a gas is enclosed into the discharge space, thereby causing generation of discharge and light emission of the phosphors which are painted on the interior wall-surface within the discharge space. Accordingly, because the PDP is a self light-emitting element, it has a feature that quality of image is high and view field thereof is wide. Further, it has relatively simple in construction and is suitable for large-sizing, in particular, for use in a large-sized display device.
In Fig. 52, on the glass plate 810 are formed two of the transparent electrodes (i.e., the X electrode 800 and the Y electrode 801) in parallel to each other, and those electrodes 800 and 801 are duplicated in structure thereof. Namely, on those transparent electrodes 800 and 801 are formed bus electrodes to decrease resistance value of thereof. Further, on two pair of those electrodes is formed a dielectric layer 812, such as of MgO. Accordingly, the PDP is the AC type PDP of a surface discharge type.
Meanwhile, on the substrate 811 are formed the ribs 803 for forming the discharge spaces therebetween, such as by sand blasting method, etc., in which the address electrodes (the A electrodes) 802 and the phosphors 804, 805 and 806 of R, G and B are formed on the bottoms of the respective spaces.
The glass plate 810 and the substrate 811 are sealed airtightly, and one or more kinds of the gases, including Xe, Ne, Ar, Kr, He are combined and enclosed therein. Here, since the ultraviolet light radiation of the Xe atom is utilized for excitation of the phosphors 804, 805 and 806, generally, the Xe gas must be enclosed.
Discharge for the display is carried out by applying pulse voltages to the X electrode 800 and the Y electrode 801 alternatively, thereby causing the discharge between those two electrodes 800 and 801 to excite the Xe atom with electron in plasma. When the excited Xe atom transits to ground state, the ultraviolet light is radiated. The ultraviolet light excites the phosphors 804, 805 and 806, thereby causing emission of three primaries, i.e., R, G and B.
Fig. 53 shows wiring of the electrodes of the PDP 900 shown in Fig. 52.
In the same figure, the X electrode 800 and the Y electrode 801 shown in Fig. 52 are disposed in parallel on the PDP 900, and terminal electrodes are taken from both sides of the PDP, i.e., the right-hand side and left-hand side thereof. The A electrodes 802 are disposed on both surface, upper surface and bottom surface of the PDP 900, and the terminal electrodes thereof are taken from every two of them alternatively, for a large number of the electrodes. A discharge cell is constituted at a junction point of the X electrode 800, the Y electrode 801 and the A electrode 802.
Here, it is assumed that an assembly of all discharge cells of the PDP is "a large set" of cells. On the other hand, the Y electrode 801 and the X electrode 800 are connected in common with the discharge cells which are disposed in the horizontal direction of the PDP 900, and it is assumed that the assembly of the discharge cells in the horizontal direction is "a middle set" of cells. Depending on the construction of the PDP 900, the Y electrode is not necessarily disposed in common for only one (l) horizontal cells, therefore, the middle set is a part constituting the large set, and it is defined that the Y electrodes are connected with an electrode.
In the middle set of cells, for applying the pulse voltages of scanning function, the Y electrodes 801 cannot be connected in common to a whole of the large set of cells, however, the X electrodes 800 can be connected in common to a whole of the large set of cells in inside or outside of the PDP 900.
Fig. 45 is a figure which shows wave-forms of driving signals in a first embodiment of driving method for PDP in accordance with the present invention.
Basically, both a writing function and a display function must be carried out for driving the PDP 900. The writing function means a function of forming electric charge on the wall-surface of the discharge cell which is selected, so as to cause only the selected discharge cell to radiate a light in the display function coming next. Accordingly, the writing function must be performed for all of the discharge cells separately, therefore, the scanning function must be conducted for the middle set of cells (the Y electrodes) of the PDP 900. The scanning function means a function of applying the pulse voltage of scanning function to the middle set of cells, within the time period of which the writing function is conducted. And, in the middle set of cells other than this, the pulse voltage of scanning function is applied at different time instance to shift in time. The selection of respective discharge cells of the middle set is performed by the A electrode which differentiates in same.
Fig. 45 shows the wave-forms of the driving signals of the respective electrodes, when a signal of one (1) field is divided into ten (10) sub-fields and the display is carried out on the divided ten (10) sub-fields. Here, only one of the A electrodes 802 is shown. Writing date to be applied to the A electrode 802 is attached with a reference numeral 1 though 10 for indicating the number of the sub-fields.
In Fig. 45, first of all, the pulse voltage 105A of scanning function is applied to the electrode Y1 which is one of the Y electrodes 801 in the middle set of cells. The pulse voltage 105A of scanning function coincides with the data in time, corresponding, for instance, to the first sub-field of the A electrode 802. Accordingly, the pulse voltage 105A of scanning function to the Y1 performs the writing function of the first sub-field. Next, to the Y2 electrode, which is one of the others of the Y electrode 801, the pulse voltage 105A of scanning function is applied to the A electrodes 802, in the same manner, corresponding to the data of the first sub-field thereof.
On the other hand, the pulse voltage 107A of scanning function is applied to Yk electrode (i.e., a one of the Y electrodes), which belongs one of the other middle sets of cells, and this is applied at the time corresponding to the fifth sub-field of the A electrode. And, the pulse voltage 107A to be applied to Y electrode next to the Yk electrode, i.e., to Yk+1 electrode, is also applied at the time corresponding to the fifth sub-field of the A electrode 802. Further, to the Y1 electrode of another one of the other middle sets of cells is applied the pulse voltage 108A at the time corresponding to, for example, the seventh sub-field of the A electrode. And, to the electrode of Yl+1, the pulse voltage 108A of scanning function is applied to the seventh sub-field of the A electrode in the same manner.
In this manner, while the scanning function of the first sub-field in a certain middle set of cells is performed, the scanning function of an another sub-field in an another middle set of cells is carried out. And, the pulse voltage of scanning function of the same sub-field performs scanning of the writing data to be applied to the A electrode 802 at the interval of the number of the sub-fields.
In Fig. 45, after the pulse voltage of scanning function, the pulse voltage of display function is applied. Namely, after the pulse voltage 105A of scanning function of the Y1 electrode, the pulse voltage 109A of display function is applied. Here, only an example is shown in which the pulse voltage 109A of the display function is only one. To the common X electrode 800 is applied a periodic pulse voltage.
Next, operation for the display will be explained.
First, the pulse 105A of scanning function is applied to the Y1 electrode, and when the data corresponding to the first sub-field of the A electrode 802 is held at a writing voltage (i.e., a high voltage), discharge is caused between the Y1 electrode and the A electrode 802, thereby adhering ion to the Y1 electrode. Next, the X electrode 800 is decreased down to a low voltage with the pulse voltage 113A, and since the Y1 electrode is at the high voltage and in addition thereto the ion is adhered onto the Y1 electrode, the pulse voltage 113A of the X electrode 800 begins discharging due to the memory effect. By this discharge, the ion is adhered onto the X electrode 800 and the electron onto the Y1 electrode, respectively. Next, the Y1 electrode comes down to low potential with the pulse 109A of display function at the Y1 electrode while the X electrode increases up to the high voltage level, therefore, the pulse 109A of display function carries out the discharging due to the memory effect. With this discharging, the electron is adhered onto the X electrode 800 and the ion onto the Y1 electrode, respectively. Next, the pulse voltage at the X electrode also discharges in the same manner. Next, the pulse voltage of display function is terminated at the Y1 electrode. Accordingly, there is not the memory effect, therefore, the pulse voltage 115A at the X electrode 800 does not discharge any more. In other words, the discharging for display is terminated by the termination of the pulse of display function at the Y1 electrode. By causing the discharging between the X electrode 800 and the Y1 electrode in such pulsative fashion, the phosphors within the discharge cells are excited to perform the light emission display.
In case of no light emission, the high voltage pulse is not applied to the A electrode 802, when the pulse voltage 105A of scanning function of the Y1 electrode is applied. In this time, no discharging occurs between the Y1 electrode and the A electrode 802, nor no adhesion of the ion occurs onto the Y1 electrode. Accordingly, if the pulse voltage to the next X electrode 800 is applied, no discharging is caused because there is no memory effect. In the same manner, the pulse voltage 109A to the next Y1 electrode and the pulse voltage 114A to the X electrode 800 never cause the discharging. Because there is no discharging for display is occurred between the X electrode 800 and the Y1 electrode, no phosphors within the discharge cells are excited to perform the light emission display.
The control of writing and light emission display mentioned in the above is performed by number of the sub-field in a single one of the middle sets of cells, and is performed as whole of the large set of cells in compliance with the scanning of the plurality of the middle sets of cells.
Next, a methodology of priming function will be explained by referring to Fig. 45.
Before applying the pulse voltage 105A of scanning function to the Y1 electrode, the priming function is performed for the purpose of decreasing the writing voltage by adhering ion onto the A electrode 802 in advance, thereby to bring the discharging for writing easy by generating spatial electric charge within the discharge cell to a certain amount in advance.
For the purposes, a positive pulse voltage 102A (the positive pulse voltage means a high pulse in which the electric potential of a low duty is higher than other electric potential) is applied to the Y1 electrode at the same time of the periodic pulse voltage 111A to the X electrode 800 so as to cause a great difference in the electric potential between the X electrode 800 and the Y1 electrode for discharge. Just after completion of this priming function, the X electrode 800 and the Y1 electrode are same in the electric potential, therefore a self-erase discharging occurs. Here, the self-erase discharging means a discharge which is caused by a voltage due to the electric charges generated on the two electrodes through the discharge after removing the pulse voltage.
By this self-erase discharging, the electric charge on the X electrode 800 and the Y1 electrode is erased, and the electric charge floating in the space is adhered onto the A electrode 802 due to the electric potential difference between the electric potential at the Y1 electrode and at the X electrode 800 and that of it to the potential at the A electrode 802. Accordingly, with this primary function, by which the ion is adhered onto the A electrode 802, it is possible to decrease the pulse voltage applied to the A electrode 802 for the writing function.
Next, in Fig. 45, a preliminary (or pre-discharge) function will be explained, which function is conducted before the application of the pulse voltage for the priming function.
With this preliminary discharge function, for decreasing the voltage of the pulse of priming function, the pulse voltage 101A of preliminary discharge function is applied to the Y1 electrode. That is, since the discharge for the display function is always completed with the pulse voltage of the X electrode 800, the discharging is caused by applying the pulse voltage being equal to that for the display function to the Y1 electrode in advance to the pulse voltage 102A of priming function, utilizing the remaining wall electric charge of the display function in the previous sub-field. With this preliminary discharge function, it is possible to adhere the ion onto the Y1 electrode, thereby to carry out the discharging for the priming function with the lower voltage.
Next, the writing of the second sub-field to be applied to the Y1 electrode will be explained by referring to Fig. 45.
By terminating the application of the pulse voltage 101A of preliminary discharge function of the first sub-field to be applied to the Y1 electrode, the pulse voltage 102A of priming function, the pulse voltage 105A of scanning function, and the pulse voltage 109A of display function, then a series of controlling of the first sub-field is completed.
Next, in the second sub-field, the same pulse voltage 103A of preliminary discharge function, the pulse voltage 104A of priming function, the pulse voltage 106A of scanning function, and the pulse voltage 109A for display function are applied. Here, the pulse voltage 106A for scanning function is applied at the time corresponding to that of the second sub-field of the writing to the A electrode 802. However, there is no need that the sub-fields be necessarily from 1 to 10 in the order thereof, and a number of writing pulse voltages are applied to the A electrode 802 during the time period between the pulse voltage 105A of scanning function of a certain sub-field and the pulse of scanning function of the next sub-field, as defined in blow; $k × n + p (1 ≦ p ≦ k - 1)$
where k, n and p are positive integers. However, here, k is the number of the sub-field, and n is an arbitrary positive number. By this, the pulse voltages of scanning to the different sub-fields are never applied at the same time instance all over the whole Y electrodes 801.
In the above, the periodic pulse voltage to the X electrode 800 shown in Fig. 45 is made not to overlap with the writing pulse applied to the A electrode 802 in time. Further, the pulse voltage of display function applied to the Y1 electrode and the pulse voltage of priming function are also made not to overlap with the writing pulse applied to the A electrode 802 in time. Further, by making the periodic pulse voltage 111A to the X electrode 800 in Fig. 45 and the pulse voltage 102A of priming function applied to the Y1 electrode opposing to each other in the polarity thereof, it is possible to obtain the higher difference in electric potential therebetween.
In Fig. 54 showing the scanning method of the first embodiment, the horizontal axis denotes the time for length of two fields, and the vertical axis the Y electrodes of the middle set of cells. Further, lines inclined in the figure follow the applying timing of the pulse voltage for scanning function of the sub-field, for each middle set of cells. Here, the number of the sub-fields is ten (10), and the respective sub-fields are indicated by b0, b1,.....and b9.
As shown in Fig. 54, for scanning one sub-field, it take about a time of one field until completing all the middle sets of cells. And, if fixing a certain time instance, it can be understood that scanning of many sub-fields is carried out at the same time. However, as shown in Fig. 45, there is no case in which the pulse voltages of scanning function for the different sub-fields overlap in time.
After the pulse voltage of scanning function, the pulse voltage of display function is applied, and the number thereof is generally different for each sub-field. Accordingly, as shown in Fig. 54, it is general that the time interval between the pulse voltages of scanning is different for each sub-field in one of the middle sets of cells.
In Fig. 55 showing the wave-forms of driving signals in a second embodiment of the driving method of PDP in accordance with the present invention, there are shown the wave-forms of driving signals at two X electrodes, i.e., X1 and X2, and two Y electrodes, i.e., Y1 and Y2, and the portions corresponding to those in Fig. 45 are attached with the same reference numerals.
Although it is assumed that the periodic pulse voltages applied to the X electrodes 800 are same for all of the middle sets of cells in Fig. 45, however, the X electrodes are independent in the respective middle sets of cells in Fig. 55, therewith showing the embodiment in which the presence of the pulse voltages to be applied is different. Here, one X electrode and one Y electrode belong to the same middle set of cells, for example, the X1 electrode and the Y1 electrode, the X2 electrode and the Y2 electrode, and so on.
A negative pulse voltage 1100A (the negative pulse voltage means a low pulse in which the electric potential of a low duty is lower than other electric potential) is applied to the X1 electrode at the same time instance of the pulse voltage 102A of priming function to Y1 electrode, and only the pulse voltage (i.e., the pulse voltage 1101A) having possibility of emitting light is applied to the X electrode before or after the pulse voltage 109A of display function to the Y1 electrode. And, the pulse voltages to the plural X electrodes 800 are applied sequentially with delay time which is equal to that of the pulse voltages of scanning function to the plural Y electrode 801.
In Fig. 56 showing the wave-form of driving signals of a third embodiment of the driving method of PDP in accordance with the present invention, the wave-form of driving signals at the X electrode 800 and the electrodes Y1 through Y5 are shown, and the portions corresponding to those in Fig. 45 are attached with the same reference numerals.
Although the pulse 102A of priming function and the pulse voltage of preliminary discharge function are sequentially shifted in time to one another in accordance with the order of the scanning for the middle sets of cells in the first embodiment shown in Fig. 45, however, in the embodiment shown in Fig. 56, at least the pulse voltage of priming function and the pulse voltage of preliminary discharge function in the middle sets of cells are applied at the same time instance, and only the pulse voltage of scanning function is shifted. With this, it becomes possible to utilize the circuitry for generating the pulse of priming function in common for the plurality of middle sets of cells, thereby reducing the number of the circuits thereof.
In Fig. 57 showing the wave-form of driving signals of a fourth embodiment of the driving method of PDP in accordance with the present invention, the wave-form of driving signals at the X electrode 800 and the electrodes Y1 through Y3 are shown, and the portions corresponding to those in Fig. 45 are attached with the same reference numerals.
In the same figure, the pulse signal of scanning function for one middle set of cells is periodically applied without stopping until the next pulse signal of priming function is applied. In place of this, a pulse signal 1300 of erase function for stopping the discharge for display is applied. This is for playing a role of distinguishing the wall electric charge, by stopping the discharge before the wall electric charge is caused by a pulse having narrow pulse width thereby neutralizing by floating electric charge in the space of the discharge cells. And, by distinguishing the wall electric charge, the discharge for display is stopped since the memory effect is lost.
Fig. 58 shows distribution of application time of the pulse voltages of display function for the sub-fields in the respective embodiments mentioned above.
For displaying a picture, there is a necessity of controlling gradation. For that purpose, the gradation is controlled by controlling the presence of the emission light thereof, with differentiating the brightness in the light emission of the respective sub-fields. Generally, the time width of the light emission of each sub-field (i.e., the brightness of the sub-field) is formed by a binary system, thereby it is possible to display the gradation at the most, with number of the sub-fields as small as possible.
However, in the display of moving picture, because a so-called dynamic false contours appears, it is not general to apply the binary system for the time width of light emission of all the sub-fields, but it is only applied to the lower sub-fields but not to the upper ones. In Fig. 58, the binary system is applied to the time width of light emission of six (6) lower sub-fields, and the time width of light emission is equal to all of four (4) upper sub-fields. And, a pair (2) of the upper four (4) sub-fields is positioned respectively, at a front portion and a rear portion of a one (1) field. With such the embodiment shown in Fig. 58, 256 gradation can be achieved by ten (10) of the sub-fields.
In Fig. 59 showing another one of the display method of gradation, the number of the sub-fields is set at seven (7), and the binary system is applied only to the time width of light emission of the lower three (3) sub-fields, while the time width of light emission is equal for all the upper four (4) sub-fields. And, a pair (2) of the upper four (4) sub-fields is positioned respectively, at a front portion and a rear portion of a one (1) field. In this case, 40 gradation can be achieved.
In Fig. 60 showing structure of a first embodiment of a display apparatus for PDP in accordance with the present invention, a reference numeral 1600A denotes a Y power recovery circuit, 1601A a pulse voltage distributing circuit, 1602A a X energy recovery circuit, 1603A an A driver circuit, 1604A a shift register, 1605A a display data signal generating circuit, and 1606A a control signal generating circuit, and the portions corresponding to those in Fig. 9 (53) are attached with the same reference numerals, for eliminating duplication in explanation.
In the same figure, respective X electrodes of the PDP are connected, in common, to the X energy recovery circuit 1602A, directly. In the X energy recovery circuit 1602A, the periodic pulse voltage is generated. The Y electrodes of the middle sets of cells are connected to the pulse voltage distributing circuit 1601A one by one, independently, and those are connected in common to the Y energy recovery circuit 1600A which constitutes a pulse voltage generating circuit for display function. The X energy recovery circuit 1602A, the pulse voltage distributing circuit 1601A and the Y energy recovery circuit 1600A are controlled by the control signals which are generated from the control signal generating circuit 1606A.
On the other hand, the A electrodes 802 are driven with the A driver circuit 1603A connected at upper and lower terminals of the PDP panel 900, in which the writing signals are generated as data signals responding to the picture from the display data signal generating circuit 1605A, and are applied to the A driver circuit 1603A through serial/parallel conversion.
In Fig. 61 showing a circuitry construction of examples of the Y energy recovery circuit 1600A and the pulse voltage distributing circuit 1601A shown in Fig. 60, reference numerals 1700 and 1701 denote FETs, 1707 a hold circuit FET, 1708 a FET, 1709 a hold circuit FET, 1710 through 1715 are diodes, 1716 a condenser, 1717 a portion of the Y energy recovery circuit 1600A, and 1718a portion of the pulse voltage distributing circuit 1601A.
In the same figure, the portion 1717 of the Y energy recovery circuit is constructed with the capacitor 1716 and two (2) unidirectional switch circuits, which are formed by the FET 1700 and the diode 1710, the FET 1701 and the diode 1711, and inductors 1702 and 1703.
Due to resonance between the inductor 1702 and a capacitive load of the Y electrode 801, the electric charge is supplied from the capacitor 1716 to the Y electrode 801 to increase the voltage thereof, and due to the resonance between the inductor 1703 and the capacitive load of the Y electrode 801, the electric charge is turned back to the capacitor 1716 again to decrease the voltage of the Y electrode 801. In this manner, by supplying the electric charge from the capacitor 1716 and recovering it back to the capacitor 1716 with application of the pulse voltage on the Y electrode 801, the driving circuit of low energy consumption can be realized.
On the other hand, the portion 1718 of the pulse voltage distributing circuit distributes the pulse voltages of display function through the diode 1712 and the FET 1704 as well as the diode 1713 and the FET 1705, and the circuit for applying the pulse voltages of scanning function and the pulse voltages of priming function are constructed with a parallel connection of bi-directional switching circuits of the diode 1714 and the FET 1706, as well as the FET 1708 and the diode 1715, and the hold circuit FET 1709 to a high voltage source and the hold circuit FET 1707 to a low voltage source.
Next, operation of the embodiment mentioned above will be explained by referring to voltage wave-forms shown in Fig. 62. Here, in the same figure, the voltage wave-from is shown which is applied to one of the Y electrodes 801, and explanation will be given separately on the divided eleven periods I through XI.
Period I: A circuit output is at a level VY2, and in this time both FETs 1706 and 1708 are conductive (in ON state). Here, the bi-directional switch is connected to the power source of the voltage VY2, since there is leaking-in of voltage due to capacitive coupling within the panel if the pulse voltage is applied to another electrode, i.e., the bi-directional switch is for escaping it to the power surce of voltage VY2.
Period II: It is of the pulse voltage of preliminary charge function, and it is held at the low voltage level through turning ON of the FET 1707.
Period III: Same to the period I.
Period IV: It is of the pulse voltage of priming function, and it is held at the output voltage VY1 through turning ON of the FET 1709.
Period V: Same to the period I.
Period IV: It is of the pulse voltage of scanning function, and it is held at the low voltage level through turning ON of the FET 1707.
Period VII: Same to the period I.
Period VIII: It is a period of fall-down of the wave-form by applying the pulse voltage of display. The FET 1701 of the Y energy recovery circuit 1717 and the FET 1705 of the pulse voltage distributing circuit 1718 are turned ON, and the potential at the Y electrode 801 is decreased down to the low voltage level in sinusoidal fashion by the resonance between the inductor 1703 and the capacitance load of the Y electrode 801. In this time, the electric charge stored in the Y electrode 801 is recovered and stored into a capacitor element 1716 of the Y energy recovery circuit 1717.
Period IX: FET 1707 is turned ON by holding the pulse voltage of display function at the low level.
Period X: It is a rise-up period of the pulse voltage of display function, and the FET 1700 of the Y energy recovery circuit 1717 and the FET 1704 of the pulse voltage distributing circuit 1718 are turned ON. Thereby, the electric charge is supplied from the capacitor 1716 to the Y electrode 801 by the resonance between the inductor 1702 and the capacitance load of the Y electrode 801, and the electric potential increase up to the level VY2 in the sinusoidal fashion.
Period XI: It is a hold period in which the pulse voltage of display function is held at the level VY2 of the power source, and same to the period I.
In application of the pulse voltage of display function hereinafter, the operation of the periods VIII through XI are repeated. Further, though here is explained only about the wave-form of the Y1 electrode of one of the middle sets of cells, however, with provision of the pulse voltage distributing circuit 1718 respectively for each middle set of cells (i.e., Y electrode), it is possible to generate the pulse signal to be applied to the other middle sets of cells as shown in Fig. 45. Further, it is enough to provide one or more of the Y energy recovery circuits 1600 (in Fig. 60) for the display apparatus of PDP.
In Fig. 63 showing a circuitry construction of other examples of the Y energy recovery circuit 1600A and the pulse voltage distributing circuit 1601A shown in Fig. 60, reference numeral 1901 denotes a hold circuit FET, 1902 through 1904 FETs, 1905 diode, 1906 a FET, 1907 a diode, 1908 through 1910 FETs, 1911 a diode, 1912 a FET, 1913 a diode, 1914 through 1916 FETs, 1917 a diode, 1918 a FET, 1919a diode, 1920 through 1922 FETs, 1923 a diode, 1924 a capacitor, 1925 and 1926 FETs, 1927 a portion of the Y energy recovery circuit 1600A, 1928, 1929 and 1930 respective portions of the pulse voltage distributing circuit 1601A corresponding to the three electrodes Y1, Y2 and Y3 of the Y electrodes 801, and the portions corresponding to those in Fig. 61 are attached with the same reference numerals, for eliminating duplication in explanation.
Difference of this embodiment comparing to that shown in Fig. 61 lies in that, in Fig. 63, there are additionally provided the hold circuit FET 1901 and the FET 1902, and the FET 1903 and the FET 1904 in the Y energy recovery circuit 1927, in order to hold at the source voltage VY2 and the lower voltage level (i.e., the ground level), and in that the FETs 1909, 1915 and 1921 are used in common as a circuit for applying the signal of the voltage level VY1 or VY2.
Next, operation of the embodiment mentioned above will be explained by referring to voltage wave-forms shown in Fig. 64 by dividing into periods I through XIII. However, since the time duration of applying the pulse voltage differs depending on the Y electrodes of the middle sets of cells, the operation of the pulse voltage distributing circuit 1929 for applying the voltage wave-form to the Y2 electrode will be explained by taking into the consideration the wave-forms of the voltages applied to the Y1 and Y3 electrodes.
Period I: The FET 1915 is turned ON. In this period I, the Y energy recovery circuit 1927 is operating since it is in duration in which the pulse voltage of preliminary discharge function is applied to the Y1 electrode, however, the terminal (i.e., the FET 1901) on which the pulse voltage of priming function is applied is fixed at the source voltage VY2.
Period II: The FET 1915 is turned ON. In this period II, there is the leaking-in voltage into the Y2 electrode, since the pulse voltage of scanning function is applied to the Y electrode of any one the middle sets of cells during the writing period and the pulse voltage of writing data is applied to the A electrode, however, it can escape through the capacitor 1924 and the FET 1926 which is turned ON.
Period III: The FETs 1901, 1912, 1914 and 1903 are turned ON. In this period III, the periodic pulse voltage 2000 is applied to the X electrode and the pulse voltage 102A of priming function to the Y1 electrode, respectively. Accordingly, the terminal (i.e., the FET 1901) to which the pulse voltage 102A of priming function is applied increases up to the level VY1, and the FET 1915 is turned OFF. The leaking-in of the pulse voltage from the X electrode 800 can escape by turning ON the above FETs 1901, 1912, 1914 and 1903 to conduct to the electric source of the voltage VY2 in both directions.
Period IV: Same to the period II.
Period V: In this period V in which the pulse voltage 101A of preliminary discharge function is applied, the FETs 1704 and 1914 are turned ON at the fall-down of the voltage wave-form, and the FET 1904 is turned ON when the voltage wave-form falls down. Further, at the rise-up of the voltage wave-form, the FETs 1700 and 1916 are turned ON. Or the FET 1916 may be turned ON without actuating the Y energy recovery circuit 1917.
Period VI: Same to the period II.
Period VII: The FETs 1925 and 1915 are turned ON. The FET 1925 which generates the pulse voltage 102A of priming function is turned ON in synchronism with the periodic pulse voltage onto the X electrode 800 always, therefore, the voltage pulse of VY1 is selectively applied to the Y electrode 801 by controlling the ON/OFF condition of the FET 1915.
Period VIII: Same to the period II.
Period IX: Same to the periods I, II and III.
Period X: The FET 1916 is turned ON. In this period X, in which the pulse voltage 105A of scanning function is applied, the Y energy recovery circuit 1927 is not actuated.
Period XI: The FET 1915 is turned ON.
Period XII: Same to the period III.
Period XIII: The FET 1915 is turned ON.
Period XIV: Same to the period V.
Period XV: Same to the periods II, III and IV.
In Fig. 65 showing a concrete embodiment of the energy recovery circuit 1602 shown in Fig. 60, a reference numeral 2100 denotes a FET, 2101 a diode, 2102 inductor, 2103 a diode, 2104 through 2106 FETs, 2107 a output voltage, and 2108 a capacitor.
In the same figure, basically, the concrete construction of this embodiment is nearly equal to the Y energy recovery circuit 1717 shown in Fig. 61, however, it differs from it in a respect that only one inductor 2102 is used in common for the inductors 1702 and 1703.
Next, an operation of this embodiment mentioned above will explained by referring to Fig. 66 which shows wave-forms of output voltages therein.
Now, under steady state, the capacitor 2108 is charged up with electric charge at electric potential of VX/2. In the period I (see Fig. 66), the FET 2105 is in conductive (ON) and the output voltage 2107 is held at voltage VX. In the next period II, the FET 2104 turns ON, then due to the resonance between the inductor 2102 and the capacitance load of the X electrode 800, the output voltage 2107 decreases down to 0 V. In the following period III, the FET 2106 turns ON and holds the output voltage 2107 at 0 V. And in the following period IV, the FET 2100 turns ON, and due to the resonance between the inductance 2102 and the X electrode 800, the output voltage 2107 increases up to the voltage VX. Further, in the following period V, the FET 2105 turns ON and holds the output voltage at VX.
In this manner, on the X electrode 800, the periodic pulse voltage is repeated in the process mentioned above. And in the period II, the electric charge stored in the X electrode 800 is recovered into the capacitor 2108, and in the period IV, the electric charge is supplied from the capacitor 2108 to the X electrode 800. Accordingly, since the electric charge being necessary for the rise-up and fall-down of the voltage at the X electrode is supplied from the capacitor 2108, the driver circuit operable with low energy consumption can be realized.
In Fig. 67 which shows the circuit construction of a concrete embodiment of the A driver circuit 1603 for one of the A electrodes 802 shown in Fig. 60, reference numerals 2300 and 2301 denote FETs.
In Fig. 67 the embodiment is constructed with a so-called push-pull circuit, and an operation of it will be explained by reference to Fig. 68 which shows output wave-forms thereof.
In the period I of the Fig. 68, the FET 2301 is turned ON so as to output the voltage 0 V. In the following period II, the FET 2300 is turned ON to output the voltage VA V. Further, in the following period II, the FET 2301 is turned ON to output the voltage of 0 V again.
In this manner, by turning ON/OFF the FETs 2301 and 2300 alternatively, the pulse voltage corresponding to the data signal is outputted. The circuit is broken when turning ON those FETs 2300 and 2301 at the same time, therefore, it is protected from such condition by making it as an inhibit mode.
Fig. 69 is a block diagram showing a principle part in the second embodiment of the display apparatus of PDP in accordance with the present invention, wherein a reference numeral 2500 denotes the pulse voltage distributing circuit, and the portions corresponding to those in Fig. 60 are attached with the same reference numerals, for eliminating duplication in explanation.
In the same figure, the respective X electrodes 800 of the PDP are independent by the middle sets of cells one by one (i.e., they are not connected with the conductor in common as shown in Fig. 60), therefore, the respective X electrodes 800 are driven by a X energy recovery circuit 1602 through the pulse voltage distributing circuit 2500 and the pulse voltages applied to the X electrodes are shifted in time by the middle sets of cells.
Fig. 70 shows circuit construction of a concrete embodiment of the X energy recovery circuit 1602 and the pulse voltage distributing circuit 2500 shown in Fig. 69, wherein a reference numeral 2600 denotes a FET, 2602 a diode, and 2601 a FET, and the portions corresponding to those in Fig. 65 are attached with the same reference numerals, for eliminating duplication in explanation.
In the same figure, as the X energy recovery circuit 1602 is used the concrete embodiment which is shown in Fig. 64. Further, the pulse voltage distributing circuits 2500 for the respective X energy recovery circuits 1602 have the same circuit construction, each of which is constructed with the FETs 2600 and FETs 2601 and the diode 2602.
Next, an operation of this embodiment will be explained by reference to Fig. 71 which shows the voltage wave-forms at various portions in Fig. 70, however, the operation of the X energy recovery circuit 1602 is that which has been already explained by reference to Figs. 65 and 66, and D1, D2 and D3 show input voltage wave-forms of FETs 2601 of the respective pulse voltage distributing circuits 2500, and X1, X2 and X3 output wave-forms of the respective pulse voltage distributing circuits 2500.
An output wave-from 2107 is formed with the periodic pulse voltages 2700. Now, for the purpose of terminating one of the periodic pulse voltages 2700 by the pulse voltage distributing circuit 2500, a control pulse signal 2701 is applied to the gate of the FET 2601 in synchronism with the fall-down of the periodic pulse voltage 2700. With application of this control pulse signal 2701, the FET 2601 turns ON and the gate of the FET 2600 decreases down to 0 V at the same time of fall-down of the periodic pulse 2700. Accordingly, the voltage between the gate and the source of the FET 2600 becomes 0 V, and the FET 2600 turns OFF. When the FET 2600 turns OFF, the periodic pulse voltage 2700 is interrupted, thereby no pulse voltage 2701 is applied to the output wave-form Xi (here, i = 1, 2, 3....., n).
On a while, for the purpose of passing the pulse voltage 2700 by the pulse voltage distributing circuit 2500, the gate of the FET 2601 is made to 0V. Then, the FET 2601 turns OFF, and the source of the FET 2600 decreases from potential VX to 0 V following the pulse voltage 2700 which decreases from the VX to 0V in voltage level. In this time, voltage occurring in the diode 2602 causes the voltage difference between the gate and the source of the FET 2600, thereby the FET 2600 turns ON. When the FET turns ON, the periodic pulse voltage 2700 passes through the FET 2600 and is applied to the X electrodes 800.
Fig. 72 shows construction of a television display apparatus as one of applications of the display apparatus of PDP in accordance with the present invention.
In the same figure, the television display apparatus 2803 is that which uses the display apparatus of PDP in accordance with the present invention, wherein a broadcasting radio signal is received by an antenna 2800 and a desired channel is selected by a tuner 2802, thereby image or picture signal and audio signal of the channel are supplied to the television apparatus 2803.
With such the construction, by using the display apparatus in accordance with the present invention, it is possible to achieve display of television, with high efficiency in light emission, high brightness and low energy consumption.
Fig. 73 shows construction of a data monitor apparatus as another application of the display apparatus of PDP in accordance with the present invention.
In the same figure, the data monitor apparatus 2901 is that which uses the display apparatus of PDP in accordance with the present invention, wherein the image data signal is outputted from a personal computer 2900 and is supplied to the data monitor 2901. The data monitor apparatus 2901 which receives the signal displays data picture including figures/characters/letters and graphs, etc. With this example of applications, since the display apparatus in accordance with the present invention is used, it is possible to achieve display, with high efficiency in light emission, high brightness and low energy consumption.
Fig. 74 shows construction of a television monitor apparatus as further other application of the display apparatus of PDP in accordance with the present invention.
In the same figure, the television monitor apparatus 3001 is that which uses the display apparatus of PDP in accordance with the present invention, wherein the image signal is outputted from a camera 3000 is supplied to the television monitor apparatus 3001. The television monitor apparatus 3001 receives the image signal and display the picture taken by the camera 3000. In this application, since the display apparatus in accordance with the present invention is used, it is possible to achieve display, with high efficiency in light emission, high brightness and low energy consumption.
Fig. 75 shows construction of a picture display apparatus for use in public place as further other application of the display apparatus of PDP in accordance with the present invention.
In the same figure, a reference numeral 3100 denotes the picture processing apparatus for display of picture, and a reference numeral 31001 denotes the image display apparatus 3101 which uses the display apparatus of PDP in accordance with the present invention. Such the apparatus is mostly used outside in the open-air, however, since it used the display apparatus in accordance with the present invention, it is possible to achieve display of image, with high brightness, high efficiency in light emission, and low energy consumption.
As is fully explained in the above, in accordance with the present invention, it is possible to elongate the pulse voltage of display function for PDP so as to increase efficiency in light emission thereof, without increasing number of driving circuits, and further to obtain display of high brightness by increasing number of the pulses.

Claims

A driving method for a display device, by which energy is supplied and recovered to and from a plurality of electrodes serving a capacitive load through switches, comprising the steps of:
flowing current for charging said electrodes through a path from a charge supplying source by using resonance in said path to said electrodes; and

flowing current for discharging said electrodes through a different path from said electrodes to said charge supplying sources by using resonance in said different path.
A driving method for a display device according to Claim 1, wherein said charging and said discharging of said electrodes are effected at substantially same time.
A driving method for a display device according to Claim 1, further comprising the steps of detecting a number of electrodes for charging and a number of electrodes for discharging, and controlling an inductance value for the energy recovery depending on the detected numbers.
A driving circuit for a capacitive load, in which switches are inserted between an energy recovery circuit and said electrodes, said driving circuit comprising:
a series circuit including a first switch, a first diode and a first inductor, said series circuit being connected with a power supply or a charged capacitor and an output terminal thereof being connected with at least two of said electrodes through at least two first unidirectional switches so that, when said at least one of said two electrodes is charged, said first switch, said first diode and said first unidirectional switches are made conductive; and

another series circuits including a second switch, a second diode and a second inductor, said another series circuit being connected with said power supply or said charged capacitor and an output terminal thereof being connected with at least two of said electrodes through at least two second unidirectional switches so that, when said at least one of said two electrodes is discharged, said second switch, said second diode and said second unidirectional switches are made conductive.
A driving circuit for a capacitive load according to Claim 4, wherein an output terminal of said first inductor is connected with a switching circuit for holding- said output terminal of said first inductor at a level of a high voltage power supply, and an output terminal of said second inductor is connected with a switching circuit for holding said output terminal of said second inductor at a level of a low voltage power supply.
A driving circuit for a capacitive load according to Claim 4, wherein each of said first and said second unidirectional switches is formed by a series circuit of a diode and an FET.
A driving circuit for a capacitive load according to Claim 4, wherein each of said first and said second unidirectional switches is formed by a bipolar transistor circuit.
A driving circuit for a capacitive load according to Claim 4, wherein a plurality of said series circuits, each of which includes said first switching circuit, said first diode, and said first inductors, are connected in parallel, inductance values of said plurality of first inductors forming a binary system, and
a plurality of said another series circuits each of which includes said second switching circuit, said second diode, and said second inductors are connected in parallel, inductance values of said plurality of second inductors forming a binary system.
A driving circuit for a capacitive load according to Claim 4, wherein each of said plurality of electrodes is connected with a voltage hold circuit for holding levels of said electrodes at a level of said high voltage power supply and a voltage hold circuit for holding levels of said electrodes at a level of said low voltage power supply.
A driving circuit for a capacitive load according to Claim 4, wherein said electrodes of said plurality of display elements are address electrodes of an AC type plasma display.
A display apparatus having a display device which has a plurality of electrodes for display elements serving as a capacitive load, in which switches are inserted between an energy recovery circuit and said electrodes, and a driving circuit for driving said display, said driving circuit comprising:
a series circuit including a first switch, a first diode and a first inductor, said series circuit being connected with a power supply or a charged capacitive element and an output terminal thereof being connected with at least two of said electrodes through at least two first unidirectional switches so that, when said at least one of said two electrodes is charged, said first switch, said first diode and said first unidirectional switches are made conductive; and

another series circuits including a second switch, a second diode and a second inductor, said another series circuit being connected with said power supply or said charged capacitive element and an output terminal thereof being connected with at least two of said electrodes through at least two second unidirectional switches so that, when said at least one of said two electrodes is discharged, said second switch, said second diode and said second unidirectional switches are made conductive.
A display apparatus according to Claim 11, wherein an output terminal of said first inductor is connected with a switching circuit for holding said output terminal of said first inductor at a level of a high voltage power supply, and an output terminal of said second inductor is connected with a switching circuit for holding said output terminal of said second inductor at a level of a low voltage power supply.
A display apparatus according to Claim 11, wherein each of said first and said second unidirectional switches is formed by a series circuit of a diode and an FET.
A display apparatus according to Claim 11, wherein each of said first and said second unidirectional switches is formed by a bipolar transistor circuit.
A display apparatus according to Claim 11, wherein a plurality of said series circuits, each of which includes said first switching circuit, said first diode, and said first inductors, are connected in parallel, inductance values of said plurality of first inductors forming a binary system; and
a plurality of said another series circuits each of which includes said second switching circuit, said second diode, and said second inductors are connected in parallel, inductance values of said plurality of second inductance elements forming a binary system.
A display apparatus according to Claim 11, wherein each of said plurality of electrodes is connected with a voltage hold circuit for holding levels of said electrodes at a level of said high voltage power supply and a voltage hold circuit for holding levels of said electrodes at a level of said low voltage power supply.
A display apparatus according to Claim 11, wherein said electrodes of said plurality of display elements are address electrodes of an AC type plasma display.
A driving method for a plasma display panel having at least a plurality of cells, each of which has three electrodes (X electrode, Y electrode and A electrode) and a discharge space, at least a surface of at least two (X electrode and Y electrode) of said three electrodes, which surface is adjacent to said discharge space, being covered with an dielectric insulator, wherein a large set of cells including total body of said plurality cells is divided into a plurality of middle sets of cells, and the Y electrodes of said cells belonging to the same middle set of cells within said middle sets of cells are connected to one another with an electrode;
dividing information to be displayed on said plasma display panel into a plurality number (k) of sub-fields, which information is constructed with one or more fields; and
scanning one sub-field A of said plurality of sub-fields by the middle set A of cells in said plurality of middle sets of cells, and scanning the sub-field(s) other than the sub-field A by any one of the middle sets of cells while the middle set(s) of cells other than the middle set A of cells scans said sub-field A.
A driving method for a plasma display panel as defined in Claim 18, wherein the scanning is carried out by applying a pulse voltage to at least any one of said Y electrode and said A electrode or both thereof.
A driving method for a plasma display panel as defined in Claim 19, wherein display is carried out during a period between the scanning which is carried out by at least one of said middle set of cells and a scanning which will be carried out next.
A driving method for a plasma display panel as defined in Claim 20, wherein said X electrodes of the cells belonging to said middle set of cells are connected with an electric conductor.
A driving method for a plasma display panel as defined in Claim 21, wherein the display function is carried out by applying a pulse voltage to at least any one of said X electrode and said Y electrode or both thereof.
A driving method for a plasma display panel as defined in Claim 22, wherein the display function is carried out by applying the pulse voltage to said X electrode and said Y electrode alternatively.
A driving method for a plasma display panel as defined in Claim 21, wherein a time region lies in a display period, further comprising steps of:
applying a periodic pulse signal in common to said X electrode for assemblies of said middle sets of cells for the time range, in at least one or more assemblies of said middle sets of cells; and

applying a pulse voltage to said Y electrode, which voltage has at least the scanning function and the display function at same time or separately, in each middle set of cells of the assemblies of said middle sets of cells.
A driving method for a plasma display panel as defined in Claim 24, wherein said X electrodes of all the cells belonging to said large set of cells are connected with an electric conductor.
A driving method for a plasma display panel as defined in Claim 25, wherein the assembly of said middle sets of cells is said large set of cells.
A driving method for a plasma display panel as defined in Claim 21, wherein a pulse voltage having priming function is also applied to said Y electrode.
A driving method for a plasma display panel as defined in Claim 19, wherein, while one of the middle sets of cells which are spatially neighboring to each other conducts the scanning function and the other thereof conducts the scanning function thereafter, the number k of the pulse voltages are applied to said A electrodes, where the k is the number of the divided sub-fields or an integral multiples thereof.
A driving method for a plasma display panel as defined in Claim 27, wherein the pulse voltage having the priming function overlaps the periodic pulse voltage to be applied to said X electrode at least one time in time.
A driving method for a plasma display panel as defined in Claim 24, wherein the periodic pulse voltage is applied to said X electrode at least for a time period of one field of the display information.
A driving method for a plasma display panel as defined in Claim 29, wherein the periodic pulse voltage applied to said X electrode is different from the pulse voltage applied to said Y electrode having the priming function, in polarity thereof.
A driving method for a plasma display panel as defined in Claim 31, wherein the periodic pulse voltage applied to said X electrode has a negative polarity, and the pulse voltage applied to said Y electrode having the priming function has a positive polarity.
A driving method for a plasma display panel as defined in Claim 21, wherein the periodic pulse voltages applied to said X electrode are differentiated in time between at least two of said middle sets of cells.
A driving method for a plasma display panel as defined in Claim 21, wherein, in said sub-field, a first pulse voltage of the periodic pulse voltages is applied to said X electrode of any one of the middle sets of cells, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
A driving method for a plasma display panel as defined in Claim 27, wherein, in said sub-field, the pulse voltage having the priming function is applied to said Y electrode of any one of the middle sets of cells, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
A driving method for a plasma display panel as defined in Claim 27, wherein, in the assembly of at least one or more of said middle sets of cells, the pulse voltages having the priming function to said Y electrodes thereof are applied to them at a same time instance.
A driving method for a plasma display panel as defined in Claim 19, wherein, while the pulse voltage having the scanning function of any one sub-field is applied to and then the pulse voltage having the scanning function of another sub-field than that sub-field is applied to said Y electrode of said middle sets of cells, a number of pulse voltages of the information to be displayed is applied to said A electrode, as defined in blow; $k × n + p (1 ≦ p ≦ k - 1)$
where k, n and p are positive integers.
A driving method for a plasma display panel as defined in Claim 24, wherein the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage having the scanning function and to be applied to said Y electrode of the middle set of cells do not overlap to each other in time.
A driving method for a plasma display panel as defined in Claim 24, wherein the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage of the display function and to be applied to said Y electrode of the middle set of cells do not overlap to each other in time.
A driving method for a plasma display panel as defined in Claim 24, wherein the pulse voltage to be applied to said A electrode does not overlap with the periodic pulse voltage applied to said X electrode and the pulse voltage having the display function and to be applied to said Y electrode in time.
A driving method for a plasma display panel as defined in Claim 27, wherein, while applying the pulse voltage having the scanning function of any sub-field to said middle set of cells and applying periodically the pulse voltage having the display function thereafter, application of the periodic pulse voltage having the display function is terminated before the pulse voltage having the priming function for a next sub-field is applied.
A driving method for a plasma display panel as defined in Claim 24, wherein a pulse voltage having erasure function is applied between the pulse voltage having the display function and the pulse voltage having the priming function.
A driving method for a plasma display panel as defined in Claim 41, wherein a pulse voltage having preliminary discharge function is applied after termination of the periodic pulse voltage having the display function and before application of the pulse voltage having the priming function.
A driving method for a plasma display panel as defined in Claim 20, wherein number of the pulse voltages having the display function is differentiated at least between the two of said sub-fields.
A driving method for a plasma display panel as defined in Claim 44, wherein the number of the pulse voltages having the display function is arranged into a ratio about 1:2:4 among at least three of said sub-fields.
A display apparatus using a plasma display panel having at least a plurality of cells, each of which has three electrodes including X electrode, Y electrode and A electrode, and a discharge space, at least a surface of at least said X electrode and Y electrode, which surface is adjacent to said discharge space, being covered with a dielectric insulator, wherein a large set of cells including total body of said plurality cells is divided into a plurality of middle sets of cells, the Y electrodes of said cells belonging to the same middle set of cells within said middle sets of cells are connected to one another with an electrode, and information to be displayed on said plasma display panel is divided into a plurality number (k) of sub-fields, which information is constructed with one or more fields, comprising:
means for scanning one sub-field A of said plurality of sub-fields by the middle set A of cells in said plurality of middle sets of cells; and

means for scanning the sub-field other than the sub-field A by any one of the middle sets of cells while the middle set of cells other than the middle set A of cells scans said sub-field A.
A display apparatus using a plasma display panel as defined in Claim 46, wherein the scanning is carried out by providing further means for applying a pulse voltage to at least any one of said Y electrode and said A electrode or both thereof.
A display apparatus using a plasma display panel as defined in Claim 47, being so constructed to able to include:
means for carrying out said scanning by at least one of said middle set of cells; and

means for carrying out the display function during a next scanning is carried out.
A display apparatus using a plasma display panel as defined in Claim 48, wherein said X electrodes of the cells belonging to said middle set of cells are connected with an electric conductor.
A display apparatus using a plasma display panel as defined in Claim 49, further comprising means for the display function to apply a pulse voltage to at least any one of said X electrode and said Y electrode or both thereof.
A display apparatus using a plasma display panel as defined in Claim 50, further comprising means for carrying out the display function by applying the pulse voltage to said X electrode and said Y electrode alternatively.
A display apparatus using a plasma display panel as defined in Claim 49, wherein a time region lies in a display period, further comprising:
means for applying a periodic pulse signal in common to said X electrode for assemblies of said middle sets of cells for the time range, in at least one or more assemblies of said middle sets of cells; and

means for applying a pulse voltage to said Y electrode, which voltage has at least the scanning function and the display function at same time or separately, in each middle set of cells of the assemblies of said middle sets of cells.
A display apparatus using a plasma display panel as defined in Claim 52, wherein said X electrodes of all the cells belonging to said large set of cells are connected with an electric conductor.
A display apparatus using a plasma display panel as defined in Claim 53, wherein the assembly of said middle sets of cells is said large set of cells.
A display apparatus using a plasma display panel as defined in Claim 49, further comprising
means for applying also a pulse voltage having priming function to said Y electrode.
A display apparatus using a plasma display panel as defined in Claim 47, further comprising:
means for conducting the scanning function on one of the middle sets of cells which are spatially neighboring to each other; and

means for applying a number k of the pulse voltages to said A electrodes, during conduction of the scanning function on the other, where the k is the number of the divided sub-fields or an integral multiples thereof.
A display apparatus using a plasma display panel as defined in Claim 55, further comprising means for overlapping the pulse voltage having the priming function and the periodic pulse voltage to be applied to said X electrode at least one time in time.
A display apparatus using a plasma display panel as defined in Claim 52, further comprising means for applying the periodic pulse voltage to said X electrode at least for a time period of one field of the display information.
A display apparatus using a plasma display panel as defined in Claim 57, further comprising means for differentiating the periodic pulse voltage applied to said X electrode from the pulse voltage applied to said Y electrode having the priming function, in polarity thereof.
A display apparatus using a plasma display panel as defined in Claim 59, further comprising:
means for making the periodic pulse voltage applied to said X electrode a pulse voltage of a negative polarity; and

means for making the pulse voltage applied to said Y electrode having the priming function a pulse voltage of a positive polarity.
A display apparatus using a plasma display panel as defined in Claim 49, further comprising: means for differentiating the periodic pulse voltages applied to said X electrode in time between at least two of said middle sets of cells.
A display apparatus using a plasma display panel as defined in Claim 49, further comprising: means for applying a first pulse voltage of the periodic pulse voltages to said X electrode of any one of the middle sets of cells, in said sub-field, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
A display apparatus using a plasma display panel as defined in Claim 55, further comprising: means for applying the pulse voltage having the priming function to said Y electrode of any one of the middle sets of cells, in said sub-field, at a same time period to that of the pulse voltage having the scanning function which is applied to said Y electrode of the same middle set of cells in the same sub-field.
A display apparatus using a plasma display panel as defined in Claim 55, further comprising: means for applying the pulse voltages having the priming function to said Y electrodes in the assembly of at least one or more of said middle sets of cells at a same time instance.
A display apparatus using a plasma display panel as defined in Claim 47, further comprising:
means for applying the pulse voltage having the scanning function of any one sub-field to said Y electrode of said middle sets of cells; and

means for applying a number of pulse voltages of the information to be displayed to said A electrode, during applying the pulse voltage having the scanning function of another sub-field than that sub-field to said Y electrode of said middle sets of cells, wherein the number of pulse voltages is defined in below; $k × n + p (1 ≦ p ≦ k - 1)$
where k, n and p are positive integers.
A display apparatus using a plasma display panel as defined in Claim 52, further comprising means for making the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage having the scanning function and to be applied to said Y electrode of the middle set of cells not to overlap to each other in time.
A display apparatus using a plasma display panel as defined in Claim 52, further comprising means for making the periodic pulse voltage to be applied to said X electrode of any middle set of cells and the pulse voltage of the display function and to be applied to said Y electrode of the middle set of cells not to overlap to each other in time.
A display apparatus using a plasma display panel as defined in Claim 52, further comprising means for making the pulse voltage to be applied to said A electrode not to overlap with the periodic pulse voltage applied to said X electrode and the pulse voltage having the display function and to be applied to said Y electrode in time.
A display apparatus using a plasma display panel as defined in Claim 55, further comprising:
means for applying the pulse voltage having the scanning function of any sub-field to said middle set of cells;

means for applying periodically the pulse voltage having the display function after the pulse voltage having the scanning function; and

means for terminating application of the periodic pulse voltage having the display function before the pulse voltage having the priming function for a next sub-field is applied.
A display apparatus using a plasma display panel as defined in Claim 69, further comprising means for applying a pulse voltage having erasure function between the pulse voltage having the display function and the pulse voltage having the priming function.
A display apparatus using a plasma display panel as defined in Claim 69, further comprising means for applying a pulse voltage having preliminary discharge function after termination of the periodic pulse voltage having the display function and before application of the pulse voltage having the priming function.
A display apparatus using a plasma display panel as defined in Claim 48, further comprising means for differentiating number of the pulse voltages having the display function at least between the two of said sub-fields.
A display apparatus using a plasma display panel as defined in Claim 72, further comprising means for arranging the number of the pulse voltages having the display function at a ratio about 1:2:4 among at least three of said sub-fields.
A display apparatus using a plasma display panel as defined in Claim 48, wherein the means for conducting the display function in said middle sets of cells is so constructed that it applies the periodic pulse from a energy recovery circuit through a switch.
A display apparatus using a plasma display panel as defined in Claim 46, wherein said plasma display panel is a AC type.
A display apparatus using a plasma display panel as defined in one of Claims 46 through 75, wherein said display apparatus is a television display apparatus, a data monitor display apparatus, a television monitor display apparatus for displaying image signal from a camera, or an information display apparatus in public places.