KR100275958B1 - Microcomputer unit - Google Patents

Abstract

The present invention relates to a microcomputer unit, to efficiently configure the user's requirements, to change or to operate or update the program in a specific area, and to provide a variety of test methods at the time of testing The purpose is to increase test efficiency.

A first control signal including a clock and a selected address are input to the memory controller, and a data memory enable signal, a program memory enable signal, and a read / write control signal are output. A system mode control signal, an address / data input and a program memory enable signal are input to the system controller, and an external ROM mode enable signal, a pyrom mode control signal, and a first address are output. The selected memory, the data memory read / write control signal, the data memory bank enable signal, the data memory enable signal, and the read / write control signal are input to the data memory. The program memory bank enable signal, the program memory enable signal, the program memory read / write control signal, the pirom mode control signal, and the first address are input to the program memory. The pseudo program memory controller generates a second address, an address selection signal, a fourth control signal, a PPM mode request signal, a program memory bank enable signal, a data memory bank enable signal, and a data memory read / write control signal. A CPU address and a second address generated in the central processing unit are input to the first multiplexer, and are controlled by an address selection signal to output one of the CPU address and the second address as the selected address.

Description

Microcomputer unit

The present invention relates to a microcomputer unit, and more particularly to a microcomputer unit in which a data memory and a program memory are formed in a memory region of a contiguous address.

The microcomputer unit has two memories, a program memory and a data memory. The program memory stores a user program necessary for the control operation of the microcomputer unit, and the data memory is for temporarily storing data generated by the execution of the user program. The program memory uses ROM so that the program is preserved even when power is not supplied, and the data memory uses RAM (particularly SRAM).

A block diagram of such a conventional microcomputer unit is shown in FIG.

The first control signal 114 including the clock, the CPU address 112 generated by the CPU, and the external ROM mode enable signal 132 are input to the memory controller 102. The memory controller 102 generates a data memory enable signal 120, a program memory enable signal 122, and a read / write control signal 124 from the above-described input signals, thereby generating the system controller 104 and the data memory ( 106 and output to the program memory 108, respectively.

The system controller 104 receives a system mode control signal 116, an address / data input 118, and a program memory enable signal 122. The system controller 104 generates an external ROM mode enable signal 132, a pyrom mode control signal 126, and a first address 128 from the above-described input signals and outputs them to the program memory 108.

The system operation mode set by the system mode control signal 116 includes a single chip mode, a test mode, and a PROM mode. In single-chip mode, the program is accessed from the user ROM. In the pyrom mode, an address / data input 118 is received from a port and transferred to the program memory 108.

The address transmitted at this time is the first address 128 which is one of the outputs of the system controller 118. The first address 128 transfers all the addresses of the address / data input 118 input through the input / output port, but the CPU address 112 described above is used as the upper address according to a programming method, which is used in the pyrom mode. Except for the remaining operation modes.

The CPU address 112, the data memory enable signal 120, and the read / write control signal 124 are input to the data memory 106.

The program memory enable signal 122, the pirom mode control signal 126, and the first address 128 are input to the program memory 108.

The program memory 108 is an area in which a user program is stored. When the program memory enable signal 122 is activated, the first address 128 is decoded to select a corresponding word. When the external ROM mode enable signal 132 is activated, the program memory enable signal 122 is deactivated and a program stored in the external ROM is accessed through the input / output port. In the pyrom mode, programming of the program memory is performed by the pyrom mode control signal 126.

In the above-described conventional microcomputer unit, when the program memory uses a mask ROM or a one-time programmable ROM, data can not be erased. If flash memory or EEPROM is used, an additional device such as an eraser board is required to change program data.

In addition, in the test mode of a device that uses both command pins and function pins to reduce the external pin count, it is difficult to test the function pins used in combination with the command pins, which increases the test program size and the test time. There is a problem such as increasing.

Therefore, the present invention allows the user to efficiently set the environment settings, to change the program in a specific area to operate or update and program, and to provide a variety of test methods during testing to increase the test efficiency There is a purpose.

The present invention for this purpose comprises a memory controller, a system controller, a data memory, a program memory, a pseudo program memory controller, and a first multiplexer.

A first control signal including a clock and a selected address are input to the memory controller, and a data memory enable signal, a program memory enable signal, and a read / write control signal are output.

A system mode control signal, an address / data input and a program memory enable signal are input to the system controller, and an external ROM mode enable signal, a pyrom mode control signal, and a first address are output.

The selected memory, the data memory read / write control signal, the data memory bank enable signal, the data memory enable signal, and the read / write control signal are input to the data memory.

The program memory bank enable signal, the program memory enable signal, the program memory read / write control signal, the pirom mode control signal, and the first address are input to the program memory.

The pseudo program memory controller includes a second address, an address selection signal, a fourth control signal, a PPM mode request signal, a program memory bank enable signal, a data memory bank enable signal, a data memory read / write control signal. Generates.

A CPU address and a second address generated in the central processing unit are input to the first multiplexer, and are controlled by an address selection signal to output one of the CPU address and the second address as the selected address.

1 is a block diagram showing a conventional microcomputer unit.

2 is a block diagram illustrating a microcomputer unit in accordance with the present invention.

3 is a block diagram showing a pseudo program memory controller of the microcomputer unit according to the present invention;

4 shows a memory map of a microcomputer unit according to the invention.

When explaining the preferred embodiment of the present invention made as described above with reference to Figures 2 to 4 as follows.

2 is a block diagram showing a microcomputer unit according to the present invention.

The first control signal 114 including the clock and the selected address 238 are input to the memory controller 202. In addition, the memory control unit 202 outputs a data memory enable signal 120, a program memory enable signal 122, and a read / write control signal 124.

The system controller 204 receives a system mode control signal 116, an address / data input 118, and a program memory enable signal 122. In addition, the system controller 204 outputs an external ROM mode enable signal 132, a pyrom mode control signal 126, and a first address 128.

The data memory 206 includes a selected address 238 and a data memory read / write control signal 228, a data memory bank enable signal 226, a data memory enable signal 120 and a read / write control signal 124. Is input.

The program memory 208 includes a program memory bank enable signal 224 and a program memory enable signal 122, a program memory read / write control signal 222, a pyrom mode control signal 126, and a first address 128. Is input.

The program memory 208 is an area in which a user program is stored. When the program memory enable signal 122 is activated, the first address 128 is decoded to select a corresponding word. When the external ROM mode enable signal 132 is activated, the program memory enable signal 122 is deactivated and a program stored in the external ROM is accessed through the input / output port. In the pyrom mode, programming of the program memory is performed by the pyrom mode control signal 126.

The first program control signal 114, the PROM mode control signal 126, and the PPM mode enable signal 232 are input to the pseudo program memory controller 210. In addition, the pseudo program memory controller 210 includes a second address 230, an address selection signal 216, a fourth control signal 234, a PPM mode request signal 220, a program memory bank enable signal 224, and data. The memory bank enable signal 226 and the data memory read / write control signal 228 are output.

A CPU address 112 and a second address 230 generated from the CPU are input to the first multiplexer 212. The first multiplexer 212 is controlled by the address selection signal 216 to output one of the CPU address 112 and the second address 230 as the selected address 238.

The address selection signal 216 selects the second address 230 in the data transfer mode or the pyrom mode from the pseudo program memory to the program memory, and otherwise selects the CPU address 112.

3 is a block diagram showing a pseudo program memory control unit of the microcomputer unit according to the present invention.

The PPM control register 302 includes a bank number selection bit 322, a PPM mode enable signal 328, a first data movement enable signal 330, a second data movement enable signal 332, and a lower address selection signal. 334 is input. The first data movement enable signal 330 is a signal that enables data to move from the pseudo program memory (actually the data memory 206) to the program memory 208.

PPM address registers 304 and 306 are composed of a PPM high address register 304 and a PPM low address register 306. In this PPM upper address register 304, a data memory upper address 324 and a program memory upper address 326 are output.

The tristate buffer 316 is controlled by the load enable signal 338, and receives the PPM lower address from the PPM lower address register 306 and transmits the PPM lower address.

The output of the tristate buffer 316 is input to the counter 312. The counter 312 is synchronized with the clock signal CLK to perform a count operation, and is cleared by the PPM stop signal 236.

The comparator 314 compares the count signal value 336 of the counter 312 with the reference signal 340, where all bits have a logic 1 value, to generate a PPM stop signal 236.

The first signal generator 308 includes a bank number selection bit 322, a PPM mode enable signal 328, a data memory upper address 324, a program memory upper address 326, and a first control signal 114. The third control signal 214 is input.

The first signal generator 308 outputs a program memory bank enable signal 224 and a data memory bank enable signal 226.

The second signal generator 310 includes a PPM mode enable signal 328, a first data movement enable signal 330, a second data movement enable signal 332, a clock signal CLK, and a data memory bank in. The enable signal 226, the pirom mode control signal 126, and the first control signal 114 are input. The second signal generator 310 requests a program memory read / write control signal 222, a data memory read / write control signal 228, an address selection signal 216, a fourth control signal 234, and a PPM mode request. The signal 220 and the load enable signal 338 are output.

The second signal generator 310 is a block for controlling the operation of the PPM mode. When the PPM mode enable signal 328 is activated, the second signal generator 310 generates a PPM mode request signal 220 to the central processing unit. When the PPM mode permission signal 232 occurs, the operation of the PPM mode is performed.

The lower address selection signal 334 and the pirom mode control signal 126 are input to the AND gate 320.

The second multiplexer 318 is controlled by the output of the AND gate 320. The second multiplexer 318 is inputted with an upper address among the addresses of the address / data input 118 and a counter count value 336, and its output is combined with the output of the PPM upper address register 304 and the second address 230. ).

The PPM mode according to the present invention having the configuration as described above has all three operation modes. In the first operation mode, the contents of the data memory are accessed when the program memory is accessed. In the second operation mode, the data of the program memory is loaded into the data memory or the data of the data memory is written to the program memory. In the third mode of operation, there are two methods of programming: programming with addresses in sequential order and programming to specific addresses. Data is provided through the input / output port and data from the memory.

In FIG. 3, the number of bits of the data memory upper address 324 and the program memory upper address 326 is due to the structure of the memory map of the data memory 206 and the program memory 208.

4 shows a memory map of the data memory 206 and the program memory 208. As shown in Fig. 4, when the data memory area and the program memory area exist in consecutive address areas and use an 8-bit data bus and a 16-bit address bus, the data memory upper address 324 and the program memory upper address 326 are used. The number of bits of each of is determined as follows.

If the unit bank is 256 bytes and the total memory area is 64 kilobytes, the total number of banks is 256. If the data memory is composed of 64 banks, the number of bits M1 of the data memory upper address 324 is 2 ^M1 = 64, so that M1 = 6 bits. Since the program memory consists of the remaining 192 banks, the number of bits M2 of the program memory upper address 326 is 2 ^M2? 192, that is, M2 = 8 bits.

The above data memory upper address 324 and program memory upper address 326 are signals that enable the first bank of each memory area. In Fig. 3, the bank number selection bit 322 activates a predetermined number of banks. The number of banks to be activated at this time is equal to the value of the bank number selection bit 322 converted to a decimal number and 1 added thereto.

Therefore, the present invention allows the user to efficiently set the environment settings, to change the program of the specific area to operate or update and program, and to provide a variety of test methods at the time of testing to increase the test efficiency to provide.

Claims (2)

In a microcomputer unit, A memory controller which receives a first control signal including a clock and a selected address, and outputs a data memory enable signal, a program memory enable signal, and a read / write control signal; A system controller which receives a system mode control signal, an address / data input and a program memory enable signal, and outputs an external ROM mode enable signal, a pyrom mode control signal, and a first address; A data memory to which the selected address and data memory read / write control signal, data memory bank enable signal, and the data memory enable signal and read / write control signal are input; A program memory to which a program memory bank enable signal, the program memory enable signal, a program memory read / write control signal, the pyrom mode control signal, and the first address are input; A pseudo program memory controller for generating a second address, an address selection signal, a fourth control signal, a PPM mode request signal, the program memory bank enable signal, the data memory bank enable signal, and the data memory read / write control signal; ; A first multiplexer for inputting a CPU address and the second address generated in the central processing unit and controlled by the address selection signal to output one of the CPU address and the second address as the selected address; Microcomputer unit. The method of claim 1, wherein the pseudo program memory control unit, A PPM control register configured to output a bank number selection bit, a PPM mode enable signal, a first data movement enable signal, a second data movement enable signal, and a lower address selection signal; A PPM address register 306 for outputting a data memory upper address and a program memory upper address; A tri-state buffer controlled by the load enable signal and configured to receive and transfer a PPM lower address from the PPM address register; A counter to which the output of the tristate buffer is input and which is counted in synchronism with a clock signal; A comparator for generating the PPM stop signal when all the bits match and compare the count signal value of the counter with a reference signal having a logic 1 value; A first signal generator configured to generate the program memory bank enable signal and the data memory bank enable signal; A second signal generator for generating the program memory read / write control signal, the data memory read / write control signal, the address selection signal, the fourth control signal, the PPM mode request signal, and the load enable signal; A microcomputer, wherein an upper address among the addresses of the address / data input and the counter count value are input, and the output includes a second multiplexer which forms the second address together with the output of the PPM upper address register; unit.