KR100275193B1 - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device such as a ROM of the present invention mainly consists of a plurality of memory cells and dummy cells, the memory cells are connected to bit lines, and the dummy cells are provided in parallel with the bit lines, respectively. Is connected to. The memory cell and the dummy cell are selectively driven by word lines arranged to intersect the bit line and the dummy line. A pair of memory cells and the dummy cell which are related to each other are simultaneously driven to the same word line. Data is stored in memory cells in a fixed manner in accordance with a mask program, and inverse data, which is the inverse of the data recorded in the memory cells, is stored in the dummy cells in a fixed manner. A differential sensing circuit is provided that is used to detect the difference between the output of one bit line and the output of one dummy bit line.

Therefore, high speed performance and excellent noise response can be realized in the read operation of the semiconductor memory device. Further, a memory cell (i.e., a MOS transistor) is formed on a silicon substrate, and a dummy cell (i.e., a transistor having a thin film transistor structure) is formed in a film layer laminated on the memory cell. As a result, the semiconductor memory device can be integrated at a high density.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device such as a mask ROM in which data is stored in a fixed manner in accordance with a mask program.

In general, programming is performed by writing data into a memory cell of a mask ROM in a fixed manner. Here data '0' and '1' are identified by making a determination as to whether the selected memory cell induces a current. Normally, a sensing circuit for reading out data from the mask ROM is composed of a current-voltage converter circuit and a differential amplifier circuit. Here, the current-voltage conversion circuit is connected to the bit line and the differential amplifier circuit compares the output voltage of the voltage-current conversion circuit with an arbitrary reference voltage.

In order to ensure the high speed operation of the mask ROM, it is important to suppress the voltage variation of the bit line as low as possible regardless of the data of '1' and '0'. Detection is made as to whether a current is induced in response to data of '1' or '0'. Therefore, in the differential amplifier circuit provided in the sensing circuit, it is necessary to have the ability to detect a small potential difference with respect to the reference voltage, thus making it difficult to ensure a sufficient noise response. When the potential variation of the bit line is increased, the noise response is correspondingly improved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of improving noise response without compromising high speed performance.

1 is a circuit diagram showing an equivalent circuit of a NOR type mask ROM designed in accordance with one embodiment of the present invention.

2 is a circuit diagram showing a detailed configuration of the differential sensing circuit of FIG.

3 is a circuit diagram showing an equivalent circuit of a NAND type mask ROM designed in accordance with another embodiment of the present invention.

4A is a plan view showing an integrated configuration of a metal oxide semiconductor corresponding to the mask ROM of FIG.

4 (b) is a cross-sectional view showing an integrated structure of the semiconductor of FIG. 4 (a).

FIG. 5A is a plan view showing an integrated structure of a metal oxide semiconductor corresponding to the mask ROM of FIG.

FIG. 5 (b) is a cross-sectional view showing an integrated structure of the semiconductor of FIG. 5 (a).

FIG. 6 is a plan view showing a modification of the integrated structure of FIG. 4 (b). FIG.

* Explanation of symbols for main parts of the drawings

41: P-type silicon substrate 42,47: gate oxide film

43,48 gate electrode 44 n-type diffusion layer

45 layer insulating film 46 silicon film

49: n-type diffusion layer

The semiconductor memory device of the present invention, such as a mask ROM, is mainly composed of a plurality of memory cells and dummy cells, wherein the memory cells are connected to bit lines, and the dummy cells are provided in parallel with the bit lines, respectively. Is connected to the line. The memory cell and the dummy cell are selectively driven by word lines arranged to intersect the bit line and the dummy line. A pair of memory cells and the dummy cell which are related to each other are simultaneously driven to the same word line. Data is stored in memory cells in a fixed manner in accordance with a mask program, and inverse data, which is the inverse of the data recorded in the memory cells, is stored in the dummy cells in a fixed manner. A differential sensing circuit is provided that is used to detect the difference between the output of one bit line and the output of one dummy bit line. Therefore, high speed performance and excellent noise response can be realized in the read operation of the semiconductor memory device. Further, a memory cell (i.e., a MOS transistor) is formed on a silicon substrate, and a dummy cell (i.e., a transistor having a thin film transistor structure) is formed in a film layer laminated on the memory cell. As a result, the semiconductor memory device can be integrated at a high density.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In some drawings, parts, such as copper, are designated by the same reference numerals, and descriptions thereof will be omitted as necessary.

FIG. 1 is an equivalent circuit diagram showing an essential structure of a N0R type mask ROM designed according to an embodiment of the present invention, wherein the mask ROM includes a plurality of memory cells, each of which is represented by ' _ij (where I is 0, 1, .....; and j uses memory cell arrays specified by 0,1 ...). Each memory cell MC _ij is composed of n-channel MOS transistors. The memory cell array along the bit line BL _i, and are selectively driven by the word line WL _j intersecting the bit lines BL _i. Each memory cell MC _ij responds to data '0' and '1' according to a mask program and enters a threshold value state (simply "HiVt state") or an enhancement state (simply "E-type state"). Therefore, data is written to the memory cell in a fixed manner.

In addition to the memory cell arrays described above, the embodiment provides dummy bit lines, each of which is designated DBL _i and located in parallel adjacent each bit line BL _i . In addition, a plurality of dummy cells each designated DC _ij are connected to the memory cell and provided along the dummy bit line. Therefore, the dummy cell DC _ij coupled to the dummy bit line DBL _i is provided by being connected to the memory cell MC _ij coupled to the bit line BL _ij . The _dummy cell DC _ij and the memory cell MC _ij are simultaneously driven by the same word line WL _j .

Inverse data which is the inverse of the data recorded in the memory cell MC _ij is written to the _dummy cell DC _ij in a fixed manner. For example, when data '0', '1', and '0' are respectively written in the memory cells MC ₀ , MC ₁ , and MC _O2 provided along the bit line BL _o , the inverse data '1', '0', ' 1 'is written to dummy cells DC ₀ , DC ₁ , and DC ₂ provided along dummy bit line DBL ₀ , respectively.

The data read operation is performed by applying an H-level voltage (i.e., 5V) to the selected word line and an L-level voltage (i.e., OV) to another word line that is not selected. Therefore, detection is made as to whether a current is induced by the selected memory cell. Here, the H-level voltage is between the threshold voltage in the HiVt state and the threshold voltage in the E-type state. As described above, the data for the memory cells MC _ij and the dummy cell DC _ij are located adjacent to each other, and the data recorded in the MC _ij is inverse data of the data recorded in the DC _ij . When the memory cell MC _ij is connected to the bit line BL _i , while the dummy cell DC _ij is connected to the dummy bit line DBL _i , a current is induced in one cell and a current is not induced in another cell. Furthermore, the differential sensing circuit SA _i is provided to detect the difference between the signals transmitted on the bit lines BL _ij and the dummy bit lines DBL _i , respectively.

The example differential sensing circuit SA _i shown in FIG. 2 is composed of pre-sensing amplifiers 21a and 21b and differential amplifiers (i.e., main sense amplifiers 22). Here, the pre-sensing amplifier 21a is composed of a current-voltage conversion circuit for detecting current induced from the bit line BL _i , and the pre-sensing amplifier 21b is current for detecting current induced from the dummy bit line DBL _i . It consists of a voltage conversion circuit. The differential amplifier 22 detects the difference between the output potentials of the pre-sensing amplifiers 21a and 21b. In particular, the pre-sensing amplifier 21a is composed of NMOS transistors Q ₂₁ and Q ₂₂ and inverters I and PMOS transistors Q ₂₃ . Here, NMOS transistors Q ₂₁ and Q ₂₂ are connected in series between bit line BL _i and power supply V _DD , and inverter I is provided to apply negative feedback to the gates of transistors Q ₂₁ and Q ₂₂ , and PMOS transistor Q ₂₃ is a current. Provided for driving. The other pre-sense amplifier 21b is configured in a similar manner to the above.

According to the above embodiment, differential detection is performed by using a dummy bit line for outputting data in compensating relation with data output on one bit line. Therefore, the present invention can perform the data sensing operation in a stable manner, as compared with the conventional method of performing the detection of data by comparing the fixing with a reference voltage. Therefore, by changing the output change of the bit line smaller than the conventional method, it is possible to execute the high speed read operation while having the same noise margin as the conventional method.

FIG. 3 shows an essential part of a NAND type mask ROM designed according to another embodiment of the present invention. The mask ROM of FIG. 3 is composed of a plurality of NAND type cells, each of which is represented by 'MT _ij '. It consists of a transistor. The memory transistor MT _ij is connected to the two select gate transistors S _i1a, the bit line BL via the S _{i2a i.} Similar to the embodiment of FIG. 1, one dummy bit line DBL _i is provided in parallel with one bit line BL _i . A dummy NAND cell consisting of 16 dummy memory transistors, each represented by 'DM _ij ', is provided in connection with a NAND cell connected to a bit line BL _i . The dummy memory transistor DM is _connected to the dummy bit line DBL _i through two selection gate transistors S _ilb and S _i2b .

The data '0' and '1' are written in the memory transistor MT _ij in a fixed manner according to a mask program so that the memory transistor is depleted or enhanced in correspondence with the data '0' or '1' recorded therein. Similar to the above embodiment, inverse data, which is the inverse of the data recorded in the memory transistor MT _ij, is written to the corresponding dummy memory transistor DM _ij in a fixed manner.

The type of the selection gate transistor provided between the bit line BL _i and the dummy bit line DBL _i is determined in connection with the selection gate line (ie, SG ₁ or SG ₂ ). In particular, all of the selection gate transistors S _02a and S _02b selectively driven by the selection gate line SG ₁ are D-type (ie, depletion type), and the selection gate transistors S _02a and S selectively driven by the selection gate line SG ₂ . _{All of 02b} becomes E type (that is, enhancement type). Therefore, when the data of the NAND type cell is read out on the bit line BL _i, the inverse data of the dummy NAND type cell is simultaneously read out on the dummy bit line DBL _i . Similar to the above, in the embodiment of FIG. 3, the differential sensing circuit SA _i is provided to detect a difference between the data of the bit line BL _{i and} the data of the dummy bit line DBL _i .

The embodiment of FIG. 3 can provide an effect similar to that of the above embodiment.

Although the embodiment of FIG. 1 provides one differential sensing circuit in relation to a pair of bit lines and a dummy bit line, in a practical circuit design, one differential sensing circuit is commonly used by several pairs of bit lines and dummy bit lines. Can be used.

If the memory cells and the dummy cells are formed on the substrate in a stacked structure in the vertical direction, an increase in chip area generated by using the same number of memory cells and the dummy cells can be prevented. Specific examples of such a laminated structure will be described below.

4 (a) and 4 (b) show an example metal oxide semiconductor using a stacked structure for the memory cells MC _ij and _dummy cell DC _{ij shown} in FIG. 1, in particular, FIG. 4 (a) shows a semiconductor. 4 (b) is a sectional view of FIG. 4 (a) taken along the line AA ′. The memory cell MC _ij is formed on the P-type silicon substrate 41 in accordance with a conventional manufacturing process for MOS LSI. In particular, the gate electrode 43 operating as a word line is formed through the gate oxide film 42, and an n-type diffusion layer 44 which functions as a source and a drain, respectively, is formed. In this manufacturing process state, data is recorded in the memo cell by the selected ion implantation technique.

Next, a silicon film 46 is deposited on the substrate through, for example, a layer insulating film 45, and a memory cell is formed on the substrate. After that, the semiconductor is processed in a predetermined pattern by performing a crystallization process. The gate electrode 48 is formed on the silicon film 46 through the gate oxide film 47, and then an n-type diffusion layer 49 is formed. Therefore, the _dummy cell DC _ij can be obtained using TFT (Thin-Film Transistor) manufacturing. In this manufacturing process state, the inverse data, which is the inverse of the data recorded in the memory cell MC _ij, is recorded in the _dummy cell DC _ij using the selective ion implantation technique. The silicon film 46 is in contact with the n-type diffusion layer 49 serving as the source of the memory cell by contacting the n-type diffusion layer 44 serving as the source of the memory cell through the contact hole 50 formed in advance.

After that, an insulating film 57 is deposited on the semiconductor, and contact holes 51, 52, and 56 are processed to deposit an Al film, and patterning is performed to form the bit line 53, the dummy bit line 54, and the ground line 55. ) Are placed respectively. The gate electrodes 43 and 48 are spaced apart from each other in the vertical direction and extend in parallel to each other to form a word line. Therefore, the electrode is commonly connected to the periphery (not shown) of one chip.

5 (a) and 5 (b) show an example metal oxide semiconductor using an integrated structure for the NAND type cell and the dummy NAND type cell used in the embodiment of FIG. 3, in particular, FIG. The top view of a semiconductor is a sectional drawing of FIG. 5 (a) cut along the BB 'line. The basic structure and manufacturing process of FIGS. 5 (a) and 5 (b) are substantially the same as those of the semiconductors of FIGS. 4 (a) and 4 (b). Therefore, the same reference numerals are used in the drawings and detailed description thereof will be omitted. As a mask program, a selective ion implantation technique is used to obtain a depletion state.

In general, thin film transistors (ie TFTs) are of lower quality than MOS transistors, which are formed on single crystal silicon due to leakage characteristics. This embodiment uses a unique TFT structure in which memory cells are formed by a normal LSI structure, and a dummy cell is formed by stacking on the memory cells. According to such a unique TFT structure, even if the TFT structure is poor in leakage characteristics, the memory The property is not so badly affected. For this reason, the dummy cell functions as an aid to the operation of reading data from the memory cell.

In the embodiment described so far, the A1 wiring is formed in a two-layer structure, but the unit cell area can be further reduced.

FIG. 6 shows another example integrated structure formed by modifying the integrated structure of FIG. 4 (b). Compared to the structure of FIG. 4 (b), the structure of FIG. 6 has the gate electrode 48 removed from the upper portion of the semiconductor. It is simplified. The gate electrode 43 provided in the lower portion of the semiconductor is used not only for the memory cell but also for the dummy cell. Therefore, the gate electrode 43 extends to form a word line commonly used by memory cells and dummy cells. Although the present invention has been described so far according to one embodiment, those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention.

Further, a memory cell (i.e., a MOS transistor) is formed on a silicon substrate, and a dummy cell (i.e., a transistor having a thin film transistor structure) is formed in a film layer laminated on the memory cell. As a result, even when the semiconductor memory device is composed of a memory cell and a dummy cell, the semiconductor memory device can be densely integrated.

Claims (7)

A plurality of bit lines; A plurality of memory cells connected to the plurality of bit lines and each of which writes data in a fixed manner according to a mask program; A plurality of word lines arranged to intersect the plurality of bit lines and selectively driving the plurality of memory cells; A plurality of dummy bit lines arranged in parallel with each of the plurality of bit lines; A plurality of dummy cells connected to the plurality of dummy bit lines and arranged in association with the plurality of memory cells, wherein a pair of related memory cells and dummy cells are simultaneously driven to the same word line in the plurality of word lines; A plurality of dummy cells in which inverse data, which is the inverse of the data recorded in the plurality of memory cells, is respectively written in the plurality of dummy cells in a fixed manner; And a differential sensing sensor for detecting a difference between the output of the bit line and the output of the dummy bit line. The semiconductor memory device according to claim 1, wherein the plurality of memory cells are formed on a semiconductor substrate and the plurality of memory cells are formed in a film layer stacked on the plurality of memory cells. A plurality of bit lines; A plurality of MOS transistors having a predetermined number of MOS transistors connected to one bit line in the plurality of bit lines; A plurality of word lines arranged to cross each of the plurality of bit lines; A plurality of dummy bit lines arranged to cross each of the plurality of bit lines; A plurality of transistors connected to one dummy bit line in the plurality of dummy bit lines and having a predetermined number of transistors respectively associated with the predetermined number of MOS transistors; And differential sensing means for detecting a difference between the output of the one bit line and the output of the one dummy line, wherein data is written to the plurality of MOS transistors in a fixed manner according to a mask program, respectively, and to the plurality of MOS transistors. Inverse data, which is the inverse of the recorded data, is written in a plurality of transistors in a fixed manner, respectively. The method of claim 3, wherein a plurality of MOS transistors are formed on a silicon substrate, and a plurality of transistors are formed in the film layer according to a structure of a thin film transistor associated with the plurality of MOS transistors by stacking a film layer on the plurality of MOS transistors. A semiconductor memory device, characterized in that. The MOS transistor of claim 3, wherein the plurality of MOS transistors are formed of an n-channel MOS transistor formed on a P-type silicon substrate, and the plurality of transistors are each formed on the plurality of MOS transistors using a thin film transistor structure. A semiconductor memory device, characterized in that. Forming a MOS transistor on the silicon substrate; Writing data on the MOS transistor using a selective ion implantation technique according to a mask program, forming a film layer on the MOS transistor; Forming a transistor having a thin film transistor structure on the film layer; Storing inverse data which is the inverse of the data recorded in the MOS transistor in the transistor by a selective ion implantation technique, wherein the data and inverse data are respectively written in the MOS transistor and the transistor in a fixed manner. Semiconductor Memory Manufacturing Method. 7. The method of claim 6, wherein the MOS transistor is composed of n-channel MOS transistors formed on a P-type silicon substrate.