KR100273901B1 - Fabricating method for actuated mirror arrays - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film actuated mirror array is provided to prevent a MOS transistor from being damaged owing to a thermal cause. CONSTITUTION: The first sacrifice layer is formed by depositing and patterning a sacrifice material layer on an entire surface of an insulation substrate(510). A membrane(540) is formed on the first sacrifice layer, and one side thereof is contact with the insulation substrate(510). A MOS transistor(550) having a gate oxide layer(550a), a gate electrode(550b), a source region(550c), and a drain region(550d) is formed on the exposed insulation substrate(510) of a side of the membrane(540). An interlayer insulation layer(560) is formed so as to protect a top of the MOS transistor and isolate the MOS transistor from the exterior. A bottom electrode is formed on the membrane(540). An active layer(580) is formed on the bottom electrode(570) so that a part of the bottom electrode(570) may be exposed. A part of the interlayer insulation layer(560) is removed so that a part of the source region(550c) and a part of the drain region(550d) may be exposed. A top electrode(590) is formed on the active layer(580), and a drain pad(610) is formed so as to connect the drain region(550d) and the bottom electrode(570), which is exposed from the active layer(580). A passivation layer(620) is formed on the drain pad(610) and the MOS transistor(550). A common wiring layer(630) is formed on the passivation layer(620) so as to be connected with the top electrode(590). A mirror support part(660) is formed so as to be connected and supported with and by a part of the top electrode(590). A mirror(670) is formed on a top of the mirror support part(660).

Description

Manufacturing method of thin film type optical path control device {FABRICATING METHOD FOR ACTUATED MIRROR ARRAYS}

The present invention relates to a method for manufacturing a thin film type optical path control device, and more particularly, to a method for manufacturing a thin film type optical path control device which can prevent the MOS transistor formed on the driving substrate from being damaged by the high temperature process involved in forming the membrane. .

An image display device is classified into a direct view type image display device and a projection type image display device according to a display method. The projection image display apparatus has a feature that can display a high quality image even on a large screen as compared to the direct view image display apparatus.

The light path adjusting device of the projection image display device includes an actuator and a mirror formed thereon. Since the actuator includes a strained layer formed of electrostrictive or piezoelectric material, when the electrical signal is applied, the strained layer is deformed in proportion to the magnitude of the electrical signal. In addition, the actuator is also deformed by the deformation of the deformation layer, so that the mirror formed on the actuator is inclined. Therefore, when the mirror is tilted, the path of the light beam incident from the optical system is changed. Next, when the path of the luminous flux is changed, the amount of luminous flux passing through the slit of the optical system is changed to adjust the intensity of the luminous flux. The light beam passing through the slit of the optical system appears on the screen via a projection lens or the like.

In general, a method of manufacturing a thin film type optical path control apparatus has a problem in which a drain pad in a driving substrate is thermally damaged during a high temperature process (that is, a membrane process) in the process of forming an actuator on the driving substrate, and one electrode of the actuator and the inside of the driving substrate In order to solve the problem that a defect occurs in the connection layer connecting the drain pad of the MOS transistor, the same content as the domestic application No. 96-42748 has been proposed.

1A to 1I are cross-sectional views showing a manufacturing method for a conventional thin film type optical path control apparatus published in Korean Application No. 96-42748.

Referring to FIG. 1A, a portion of the insulating substrate 10 is oxidized to form a field oxide layer 20. The field oxide layer 20 defines an active region A and an inactive region B in which the MOS transistor 30 is formed.

Next, the MOS transistor 30 including the gate oxide layer 30a, the gate electrode 30b, the source region 30c, and the drain region 30d is formed in the active region A defined by the field oxide layer 20. .

Subsequently, the first protective layer 40 is formed of Phospo-Silicate Glass (PSG) on the field oxide layer 20 and the MOS transistor 30. The first protective layer 40 is formed by a chemical vapor deposition (CVD) method. The first protective layer 40 prevents the MOS transistor 30 from being damaged during subsequent processing.

Subsequently, the etch stop layer 50 is formed of silicon nitride (Si ₃ N ₄ ) on the first protective layer 40. The etch stop layer 50 is formed using a low pressure chemical vapor deposition (LPCVD) method for depositing a thin film.

Referring to FIG. 1B, a sacrificial material layer 60 ′ is formed on the etch stop layer 50. The sacrificial material layer 60 ′ is formed by using an atmospheric pressure chemical vapor deposition (APCVD) process of an silicate glass (PSG) having a high concentration of phosphorus (P).

Meanwhile, since the sacrificial material layer 60 ′ covers the surface of the insulating substrate 10 on which the MOS transistors 30 are formed, the surface flatness is very poor. Accordingly, the surface of the sacrificial material layer 60 'is planarized by using spin on glass (SOG) made of siloxane or silicate mixed with alcohol-based solvent, or by using a chemical mechanical polishing (CMP) process. .

Subsequently, the sacrificial layer 60 is formed by patterning the planarized sacrificial material layer 60 ′ in a dry process or a wet process. The sacrificial layer 60 separates a predetermined portion of the insulating substrate 10 into a supporting region B and a driving region C of the actuator 120. That is, from the active region A to one end of the sacrificial layer 60 becomes the support region B of the actuator 120, and the driving region C of the actuator 120 is formed at the portion where the sacrificial layer 60 is formed. do.

Next, a membrane material layer 70 ′ made of silicon nitride is formed on the etch stop layer 50 and the sacrificial layer 60. The membrane material layer 70 'is formed by a low pressure chemical vapor deposition method similarly to the method of forming the etch stop layer 50 made of silicon nitride.

Subsequently, a lower electrode material layer 80 'is formed on the membrane material layer 70' by sputtering a material having excellent electrical conductivity, for example, platinum (Pt) or platinum / tantalum (Pt / Ta).

Referring to FIG. 1C, a piezoelectric ceramic or an anti-distortion ceramic is formed on the lower electrode material layer 80 ′ by a sol-gel method to form a strain material layer 90 ′. Next, the strained material layer 90 'is subjected to rapid heat treatment to cause phase change.

Next, the strained material layer 90 ′ is patterned to form the strained layer 90. In this case, the deformation layer 90 is formed in the driving region C of the actuator 120, and is not formed in the active region A, the supporting region B and the inactive region D of the actuator 120.

Referring to FIG. 1D, the lower electrode material layer 80 ′ and the membrane material layer 70 ′ are sequentially patterned to form the lower electrode 80 and the membrane 70. In this case, the lower electrode 80 and the membrane 70 are formed in the support region B and the driving region C of the actuator 120, but are not formed in the active region A and the inactive region D. Therefore, the etch stop layer 50 formed in the active region A and the inactive region D is exposed. In addition, a portion of the sacrificial layer 50 formed under the membrane 70 is also exposed. In addition, in the supporting region B of the actuator 120, the etch stop layer 50 and the membrane 70 are in contact with each other.

Referring to FIG. 1E, the etch transistor layer 50 and the first passivation layer 40 formed in the active region A are selectively removed to expose the MOS transistor 30. In this case, the first protective layer 40 surrounding the gate electrode 30b and the gate oxide layer 30a is not removed, thereby performing the function of the interlayer insulating layer. Thus, a portion of the source region 30c and the drain region 30d are exposed.

Referring to FIG. 1F, platinum (Pt) or aluminum (Al) having excellent reflection characteristics and electrical conductivity is stacked on the insulating substrate 10 to form an upper electrode material layer 100 ′. Subsequently, the upper electrode material layer 100 ′ is patterned to have a predetermined shape to form the source line 130, the drain pad 140, and the upper electrode 100.

Therefore, the upper electrode 100 is formed on the strained layer 90, and one side of the source line 130 is formed from the source region 30c to a predetermined portion of the etch stop layer 50 of the inactive region D. The other side is formed from a source region 30c to a predetermined portion of the first protective layer 40 formed on the gate electrode 30b.

In addition, one side of the drain pad 140 is formed from a drain region 30d to a predetermined portion of the lower electrode 80 formed in the actuator 120 support region B so that the image signal applied to the outside is applied to the lower electrode 80. The other side is formed in the drain region 30d to a predetermined portion of the first protective layer 40 formed on the gate electrode 30b.

In addition, the source line 130 and the drain pad 140 formed on the first passivation layer 40 formed on the gate electrode 30b are spaced apart by a predetermined distance so as not to be electrically connected to each other.

Referring to FIG. 1G, a protective material layer 110 ′ is deposited on an upper surface of the substrate 10 with insociated glass (PSG). Subsequently, the second protective layer 110 is formed by etching the remaining portion of the protective material layer 110 ′ except for the portion surrounding the drain pad 140 in the source line 140. The second passivation layer 110 prevents the source line 130 and the drain pad 140 from being damaged by the etching solution in a subsequent sacrificial layer 60 removal process.

Referring to FIG. 1H, an air gap 150 is formed by removing the sacrificial layer 60 partially exposed under the membrane 70 with hydrofluoric acid gas.

In the conventional method of manufacturing a thin film type optical path control device, a MOS transistor may be formed on the side of the actuator instead of directly underneath the actuator, so that the connection layer may be simultaneously formed at the time of forming the upper electrode. There was a problem of being thermally damaged.

The present invention has been made to solve the above-mentioned conventional problems, and can prevent the MOS transistor formed on the insulating substrate from being damaged due to thermal factors due to the high temperature involved in the process of forming the membrane of the actuator. It is an object of the present invention to provide a method for manufacturing a thin film type optical path control device.

In order to achieve the above object, the present invention provides a method for manufacturing a thin film type optical path control device having M x N (M, N is an integer) actuators, a) patterning after laminating a sacrificial material layer on the entire surface of the insulating substrate To form a first sacrificial layer; B) forming a membrane on top of the first sacrificial layer by contacting and extending one end on the insulating substrate; C) forming a MOS transistor having a gate oxide layer, a gate electrode, a source region and a drain region on the exposed insulating substrate on the membrane side; D) forming an interlayer insulating layer to insulate the MOS transistor from the outside while protecting the upper portion of the MOS transistor; E) forming a lower electrode on the membrane; F) forming a strained layer on the lower electrode to expose a portion of the lower electrode; G) removing a portion of the interlayer insulating layer so that a portion of the source region and a portion of the drain region are exposed; (H) forming a drain pad connecting the drain region and the lower electrode exposed from the strain layer while forming an upper electrode on the strain layer; I) forming a protective layer on the drain pad and the MOS transistor; Forming a common wiring layer connected to the upper electrode on the protective layer; K) forming a mirror support part which is in contact with and supported by a partial region of the upper electrode; And (ii) forming a mirror that is in contact with and supported in the upper region of the mirror support.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

1A to 1I are cross-sectional views showing a manufacturing method for a conventional thin film type optical path control device;

2 is a plan view of a thin film type optical path control apparatus according to the present invention,

3 is a cross-sectional view taken along line A-A 'of the apparatus shown in FIG. 2;

4A to 4H are manufacturing process diagrams of the apparatus shown in FIG.

<Explanation of symbols for main parts of drawing>

510: insulating substrate 520: field oxide layer 530: first sacrificial layer

540: membrane 550: MOS transistor 560: interlayer insulating layer

570: lower electrode 580: strained layer 590: upper electrode

600: source line 610: drain pad 620: protective layer

630: common wiring layer 640: gate line 650: etching prevention layer

660: mirror support 670: mirror

2 is a plan view of a thin film type optical path control device according to the present invention, Figure 3 is a cross-sectional view taken along the line AA 'of the device shown in FIG.

2 and 3, the thin film type optical path control apparatus includes an insulating substrate 510 and an actuator 700 formed thereon.

The insulating substrate 510 is divided into an active region A, an actuator 700 support region B, an actuator 700 driving region C, and an inactive region D.

Here, the active region A is defined by the field oxide layer 520, and the gate oxide layer 550a, the gate electrode 550b, the source region 550c, the drain region 550d, and the interlayer insulating layer 560 are formed. An MOS transistor 550 is formed.

In addition, the support region B of the actuator 700 is defined from the field oxide layer 520 in the direction of the drain region 550d to one end of the air gap 690, and has an interlayer insulating layer on the field oxide layer 520. 560, the membrane 540 and the lower electrode 570 are sequentially formed. One end of the drain pad 610 is extended to be electrically connected to the lower electrode 570.

The driving region C of the actuator 700 is formed such that the membrane 540 is spaced apart from the field oxide layer 520 by a predetermined distance through the air gap 690. The lower electrode 570, the strain layer 580, the upper electrode 590, the mirror support 660, and the mirror 670 are sequentially formed on the membrane 540.

In the inactive region D, the field oxide layer 520 and the interlayer insulating layer 560 are sequentially formed, and a portion of the source line 600 and the gate line 640 are formed on the interlayer insulating layer 560. In this case, the source line 600 and the gate line 640 are not electrically connected to each other by a predetermined distance.

The protective layer 620 is formed in the remaining portion except for the driving region C of the insulating substrate 510. The common wiring layer 630 is formed on one side of the protective layer 620. One side of the common wiring layer 630 is formed to be electrically connected to the upper electrode 590, and the other side thereof is extended to the active region A of the actuator 700. In addition, an etch stop layer 650 is formed on the passivation layer 620 and the common wiring layer 630.

Referring to FIG. 2, the actuator 700 in which the membrane 540, the lower electrode 570, the strained layer 580, the upper electrode 590, and the mirror support 660 are sequentially formed has two pixels in one pixel. Dogs are formed, and the actuators 700 are formed spaced apart from each other by a predetermined distance.

In addition, one side of the upper electrode 590 and the common wiring layer 630 are in contact with each other and electrically connected to each other, and one side of the lower electrode 570 and the drain pad 610 are in contact with each other and electrically connected to each other. However, since the common wiring layer 630 and the drain pad 610 are formed to be spaced apart from each other by the protective layer 620 as shown in FIG. 3, they are electrically separated. In addition, the drain pad 600 is formed in a 'U' shape, and the same image signal is supplied to the lower electrode 570 of each actuator 700 on the same pixel.

In addition, since the MOS transistor 550 including the gate oxide layer 550a, the gate electrode 550b, the source region 550c, the drain region 550d, and the like is formed at the lower side and not directly under the actuator 700, the actuator ( After the membrane 540 of 700 is formed, the MOS transistor 550 is formed.

Hereinafter, a manufacturing method of a thin film type optical path control device according to the present invention will be described in detail with reference to the accompanying drawings.

4A to 4H are cross-sectional views illustrating a method of manufacturing a thin film type optical path control device according to the present invention. 4A to 4H, the same reference numerals are given to the same structural members as those in FIG.

Referring to FIG. 4A, a portion of the insulating substrate 510 is oxidized to form a field oxide layer 520. The field oxide layer 520 defines an active region A and an inactive region D in which the MOS transistor 550 is formed.

Next, a sacrificial material layer 530 ′ is formed on the upper surface of the insulating substrate 510 on which the field oxide layer 520 is formed. The sacrificial material layer 530 ′ is formed of an silicate glass (PSG) having a high concentration of phosphorus (PG) by using an atmospheric pressure chemical vapor deposition (APCVD) process.

Subsequently, the first sacrificial layer 530 is formed by patterning the sacrificial material layer 530 ′ in a dry process or a wet process. In this case, the insulating substrate 510 is separated into a supporting region B and a driving region C of the actuator 700 to be described later by the first sacrificial layer 530. That is, from the active region A to one end of the sacrificial layer 530 becomes the support region B of the actuator 700, and the driving region C of the actuator 700 is formed in the portion where the sacrificial layer 530 is formed. do.

Referring to FIG. 4B, a membrane material layer 540 ′ formed of silicon nitride is formed on the insulating substrate 510 and the sacrificial layer 530. Membrane material layer 540 'forms silicon nitride by low pressure chemical vapor deposition.

Subsequently, the membrane material layer 540 ′ is patterned into a predetermined shape to form the membrane 540. In this case, the membrane 540 is formed in the support region B and the driving region C of the actuator 700, and the membrane 540 is not formed in the active region A and the inactive region D. In this case, a portion of the sacrificial layer 530 formed under the membrane 540 is exposed.

Referring to FIG. 4C, the MOS transistor 550 including the gate oxide layer 550a, the gate electrode 550b, the source region 550c, and the drain region 550d is formed in the active region A. Referring to FIG.

Subsequently, an upper surface of the substrate 510 is coated with an insulating material, and then patterned to form an interlayer insulating layer 560. In detail, the interlayer insulating layer 560 is formed on the field oxide layer 520 in the inactive region D and the actuator 700 support region B, and in the active region A, the gate oxide layer 550a. And the gate electrode 550b. In this case, in the actuator 700 supporting region B, the interlayer insulating layer 560 is formed lower than the membrane 540.

Next, a lower electrode material layer 570 ′ is formed on the membrane 540 and the substrate 510 by sputtering a material having excellent electrical conductivity, for example, platinum (Pt) or platinum / tantalum (Pt / Ta). do.

Subsequently, the lower electrode material layer 570 ′ is patterned to form the lower electrode 570. In this case, the lower electrode 570 is formed on the membrane 540, and the lower electrode 570 is not formed in the active region A and the inactive region D.

Referring to FIG. 4D, a piezoelectric ceramic or an anti-distortion ceramic is formed on the upper surface of the lower electrode 570 and the upper surface of the substrate 510 by using a sol-gel method. Next, the strained material layer 580 ′ is patterned into a predetermined shape to form the strained layer 580. In this case, the strained layer 580 is formed on the lower electrode 570 of the actuator 700 driving region C, and is formed on the active region A, the inactive region D, and the support region B of the actuator 700. The strained layer 580 is not formed.

Referring to FIG. 4E, the upper electrode 590, the source line 600, the drain pad 610, and the gate line 640 are simultaneously formed by a lift off method. First, the upper electrode material layer 590 ′ is formed on the upper surface of the substrate 510 using platinum (Pt) or platinum / tantalum (Pt / Ta), which is a material having excellent electrical conductivity. Subsequently, the upper electrode material layer 590 ′ is patterned to have a predetermined shape to form the upper electrode 590, the source line 600, the drain pad 610, and the gate line 640. The upper electrode 590 is formed on the strained layer 580.

One side of the source line 600 is formed from an upper portion of the source region 550c to a predetermined portion of the inactive region D, and the other side thereof is an interlayer insulating layer formed on the gate electrode 550b in the source region 550c. Up to a predetermined portion of 560 is formed.

One side of the drain pad 550d is formed to a predetermined portion of the lower electrode 570 of the actuator 700 supporting region B, and the other side thereof is formed to the upper portion of the interlayer insulating layer 560 on the gate electrode 550b. do.

In this case, since the source line 600 and the drain pad 610 are formed to be spaced apart from each other by a predetermined distance, they are electrically separated from each other.

In addition, the gate line 640 is formed on the interlayer insulating layer 560 of the inactive region D, and is spaced apart from the source line 600 by a predetermined distance and is not electrically connected to each other.

Referring to FIG. 4F, a protective material layer 620 ′ is formed of Phospo-Silicate Glass (PSG) on the substrate 510 and the upper electrode 590. The protective material layer 620 ′ is formed by a chemical vapor deposition (CVD) method. Subsequently, the protective material layer 620 ′ is patterned to form a protective layer 620. That is, the protective layer 620 is not formed in the driving region C of the actuator 700, but is formed in the active region A, the support region B and the inactive region D of the actuator 700. In this case, the protective layer 620 is formed lower than the upper electrode 590. The protective layer 620 prevents the MOS transistor 550 from being damaged during subsequent processing.

Subsequently, the common wiring material layer 630 ′ is formed on the substrate 510 and the upper electrode 590. Subsequently, the common wiring material layer 630 ′ is patterned to form the common wiring layer 630. Accordingly, the common wiring layer 630 is formed from a predetermined portion of the upper electrode 590 to the active region A. FIG.

Referring to FIG. 4G, an etch stop layer 650 is formed on the passivation layer 620, the common wiring layer 630, and the upper electrode 590. The etch stop layer 650 prevents the protective layer 620, the common wiring layer 630, and the upper electrode 590 from being damaged during the subsequent etching process.

Subsequently, a second sacrificial material layer (not shown) is formed on the etch stop layer 650. The second sacrificial layer is formed of an silicate glass (PSG) having a high concentration of phosphorus (PG) by using an atmospheric pressure chemical vapor deposition (APCVD) process.

On the other hand, since the second sacrificial layer covers the surface of the insulating substrate 510 on which the MOS transistors 550 are formed, the flatness of the surface is very poor. Accordingly, the surface of the second sacrificial layer is planarized by using spin on glass (SOG) made of siloxane or silicate mixed with an alcohol-based solvent, or by using a chemical mechanical polishing (CMP) process.

Subsequently, after the predetermined portions of the second sacrificial layer and the etch stop layer 650 are removed, the mirror support part 660 is formed. Subsequently, after the mirror 670 is formed on the second sacrificial layer and the mirror support 660, the second sacrificial layer is removed to form the second air gap 680. In this case, the mirror 670 and the etch stop layer 650 are formed to be spaced apart from each other through the second air gap 680.

Referring to FIG. 4H, the first sacrificial layer 530 formed under the membrane 540 is removed with hydrofluoric acid to form a first air gap 690.

However, the mirror 670 may be formed in the following manner. First, an etch stop layer 650 is formed on the passivation layer 620, the common wiring layer 630, and the upper electrode 590.

Subsequently, the first air gap 690 is formed by removing the first sacrificial layer 530 formed under the membrane 540.

Next, the second sacrificial material layer is formed on the etch stop layer 650 and then planarized. The second sacrificial material layer is patterned to form a second sacrificial layer having a position where the mirror support 660 is to be formed.

Subsequently, after the mirror support 660 is formed on the second sacrificial layer, the mirror 670 is formed on the mirror support 660 and the second sacrificial layer.

As described above, the method for manufacturing the thin film type optical path control apparatus according to the present invention has an effect of preventing damage to the MOS transistor due to the high temperature process involved in forming the membrane by forming the membrane and then forming the MOS transistor.

As described above, although the present invention has been described with reference to the drawings, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (6)

In the manufacturing method of the thin film type optical path control apparatus which has MxN (M, N is integer) actuators 700, A) laminating a sacrificial material layer 530 'on the entire surface of the insulating substrate 510 and patterning the first sacrificial layer 530; B) forming a membrane 540 on the first sacrificial layer 530 by contacting and extending one end of the insulating substrate 510; C) A MOS transistor 550 having a gate oxide layer 550a, a gate electrode 550b, a source region 550c, and a drain region 550d is formed on the exposed insulating substrate 510 on the side of the membrane 540. Doing; D) forming an interlayer insulating layer 560 to insulate the MOS transistor 550 from the outside while protecting the upper portion of the MOS transistor 550; E) forming a lower electrode 570 on the membrane 540; F) forming a strained layer 580 on the lower electrode 570 so that a portion of the lower electrode 570 is exposed; G) removing a portion of the interlayer insulating layer 560 so that a portion of the source region 550c and a portion of the drain region 550d are exposed; The drain pad 610 connecting the drain region 550d and the lower electrode 570 exposed from the strain layer 580 while forming an upper electrode 590 on the strain layer 580. Forming a; I) forming a protective layer 620 on the drain pad 610 and the MOS transistor 550; Forming a common wiring layer 630 connected to the upper electrode 590 on the protective layer 620; (C) forming a mirror support part 660 which is in contact with and supported a partial region of the upper electrode 590; And T) forming a mirror (670) in contact with the upper region of the mirror support (660). The method of claim 1, wherein the step a) comprises: Forming a field oxide layer (520) on the insulating substrate (510) defining an active region (A) in which the MOS transistor (550) is to be formed; Forming the sacrificial material layer (530 ') over the field oxide layer (520) and the active region (A); And And forming a first sacrificial layer (530) by patterning the sacrificial material layer (530 ') so as to remain only in a predetermined region of the field oxide layer (520). The method of claim 1, wherein the step a) includes: a drain pad 610 connecting the exposed drain region 550c and the lower electrode 570, and a source contacting the exposed source region 550c. And a line (600) and a gate line (640) in contact with the gate electrode (550b) at the same time to form a thin film type optical path control device. 4. The method of claim 3, wherein the drain pad (610), the source line (600) and the gate line (640) are formed by a lift-off method. The method of claim 1, wherein the step of forming the protective layer 620 comprises at least one insulating material layer in which a material having an etch selectivity with the first sacrificial layer 530 is laminated on the uppermost layer. The manufacturing method of the thin film type optical path control apparatus characterized by the above-mentioned. The method of claim 1, The other steps are: After removing the first sacrificial layer (530), stacking a material which is easily etched to cover a predetermined height of the upper electrode (590); Planarizing the easy-to-etch material; Removing a portion of the easily etched material to expose a portion of the upper electrode 590; And And forming a mirror layer (670 ') by stacking a material having good reflectivity on the exposed upper electrode (590) and the easily etched material.

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