KR100271795B1 - A mothod of fabricating semiconductor device - Google Patents
A mothod of fabricating semiconductor device Download PDFInfo
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- KR100271795B1 KR100271795B1 KR1019980010266A KR19980010266A KR100271795B1 KR 100271795 B1 KR100271795 B1 KR 100271795B1 KR 1019980010266 A KR1019980010266 A KR 1019980010266A KR 19980010266 A KR19980010266 A KR 19980010266A KR 100271795 B1 KR100271795 B1 KR 100271795B1
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- gate
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- substrate
- conductivity type
- silicide layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 37
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 15
- -1 germanium ions Chemical class 0.000 claims abstract description 13
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 3
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000009413 insulation Methods 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서 특히, 졍션을 형성할 때 알파-실리콘층을 완충막으로 하고 여기에 게르마늄 또는 붕소이온을 주입하여 졍션 깊이를 얕게하여 누설전류를 감소시키고 졍션 저항을 낮춘 반도체장치의 셸로우 졍션 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, when forming a cushion, an alpha-silicon layer is used as a buffer film, and germanium or boron ions are injected therein to reduce the depth of the junction to reduce leakage current and lower the cushion resistance. A method of forming a shallow section of a semiconductor device.
종래의 기술에서 졍션을 형성할 때 금속과 실리콘기판의 실리콘이 직접 접촉하여 실리사이드(silicide)를 형성하게 되면, 졍션에서의 누설전류(leakage current)가 다량 발생하게 되고 졍션의 형성 깊이도 깊게되고 또한 졍션에서의 저항도 커지게 된다.In the prior art, when the metal and the silicon substrate are in direct contact with each other to form silicide, a large amount of leakage current in the junction is generated and the depth of formation of the cushion is also deepened. The resistance in the section will also increase.
종래 기술에 따른 반도체장치의 p+/n 졍션 형성방법은 금속층인 타이타늄(Ti)층과 실리콘기판의 실리콘층이 아무런 매개체 없이 직접 접촉하게 된다. 따라서 기판의 벌크(bulk) 실리콘이 졍션 형성에 직접 사용되어 누설전류가 발생하고 졍션의 형성 깊이도 깊어지게 된다.In the method of forming a p + / n section of the semiconductor device according to the prior art, the titanium (Ti) layer, which is a metal layer, and the silicon layer of the silicon substrate are in direct contact without any medium. As a result, the bulk silicon of the substrate is directly used to form the cushion, which causes leakage current and deepens the formation of the cushion.
따라서, 종래 기술에서 실리콘-타이타늄의 실리사이드층을 형성한 다음 이 실리사이드층에 p 형 불순물(dopant)인 붕소이온을 주입하지만, 이는 접촉저항과 졍션에서의 누설전류를 크게 하며 졍션의 깊이를 깊게한다. 왜냐하면, 실리사이드의 형성을 위한 열공정시 TiSi2층이 수평방향과 동시에 수직방향으로도 확산이 일어나기 때문이다.Therefore, in the prior art, a silicide layer of silicon-titanium is formed, and then a boron ion, which is a p-type impurity, is implanted into the silicide layer, which increases contact resistance and leakage current in the junction and deepens the depth of the section. . This is because the TiSi 2 layer diffuses in the vertical direction as well as the horizontal direction during the thermal process for forming silicide.
그러나, 상술한 종래 기술에 따른 반도체장치의 졍션 형성방법은 큰 접촉저항과 다량의 누설전류 및 깊게 형성된 졍션을 초래하여 소자의 특성을 열화시키는 문제점이 있다.However, the method of forming a section of the semiconductor device according to the related art described above has a problem of deteriorating the characteristics of the device by causing a large contact resistance, a large amount of leakage current and a deeply formed section.
따라서, 본 발명의 목적은 금속-실리콘 졍션을 형성할 때 알파-실리콘층을 완충막으로 하고 여기에 게르마늄 또는 붕소이온을 주입하여 졍션 깊이를 얕게하여 누설전류를 감소시키고 졍션 저항을 낮춘 반도체장치의 셸로우 졍션(shallow junction) 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to form a metal-silicon caption in which an alpha-silicon layer is used as a buffer film and germanium or boron ions are implanted therein to reduce the depth of the junction to reduce leakage current and lower the resistance of the caption. It is to provide a method of forming a shallow junction (shallow junction).
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 졍션 형성방법은 제 1 도전형 반도체기판 상의 소정 부위에 게이트와 게이트와 기판 사이에 개재된 게이트절연막을 형성하는 단계와, 게이트 하단에 위치한 기판에 제 2 도전형 저농도 불순물영역을 형성하는 단계와, 게이트와 게이트절연막 측면에 측벽을 형성하는 단계와, 게이트와 측벽 그리고 노출된 기판의 표면에 실리사이드층을 형성하는 단계와, 실리사이드층에 게르마늄 이온과 제 2 도전형 불순물이온을 도핑시키는 단계와, 도핑된 실리사이드층을 패터닝하여 졍션 형성부위에 도핑된 실리사이드층을 잔류시키는 단계와, 도핑된 실리사이드층의 제 2 도전형 불순물이온을 기판내로 침투시키는 단계로 이루어진 공정을 구비한다.The method for forming a section of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate insulating film interposed between the gate and the gate and the substrate at a predetermined portion on the first conductive semiconductor substrate, Forming a second conductivity type low concentration impurity region, forming sidewalls on the sidewalls of the gate and the gate insulating film, forming a silicide layer on the surfaces of the gate and the sidewalls and the exposed substrate, and forming germanium ions on the silicide layer; Doping the second conductivity type impurity ion, patterning the doped silicide layer to leave the doped silicide layer at the junction formation portion, and penetrating the second conductivity type impurity ion of the doped silicide layer into the substrate. It comprises a process consisting of.
도 1a 내지 도 1e는 본 발명에 따른 반도체장치의 졍션(junction) 형성방법을 도시하는 공정단면도1A to 1E are process cross-sectional views illustrating a method of forming a junction of a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a를 참조하면, 활성영역과 격리영역을 구분하기 위한 필드산화막(2)이 형성된 제 1 도전형인 n 형 반도체기판(1) 상에 열산화 방법에 의해 소정 두께의 게이트절연막인 제 1 산화막(3)을 형성한다. 이때, 반도체기판은 제 1 도전형 웰(well)일 수 있다. 그리고, 게이트절연막(3) 상에 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착하여 다결정실리콘층(4)을 형성한다.Referring to FIG. 1A, a first oxide film, which is a gate insulating film having a predetermined thickness, may be formed on a first conductive n-type semiconductor substrate 1 having a field oxide film 2 formed therebetween to distinguish an active region and an isolation region. 3) form. In this case, the semiconductor substrate may be a first conductivity type well. Then, polycrystalline silicon doped with impurities on the gate insulating film 3 is deposited by CVD to form the polysilicon layer 4.
다결정실리콘층(4)과 게이트절연막(3)을 패터닝하여 게이트(4)와 게이트(4) 하부에 게이트절연막(3)을 잔류시킨다.The polysilicon layer 4 and the gate insulating film 3 are patterned to leave the gate insulating film 3 under the gate 4 and the gate 4.
그리고 게이트를 마스크로 이용한 제 2 도전형인 p 형 불순물 이온주입을 기판(1)의 전면에 저농도로 실시하여 게이트 양측 하단에 엘디디(lightly doped drain) 형성부위(도시 안함)를 정의하고 다시 기판(1)의 전면에 제 2 산화막(5)을 증착한 후 이를 에치백하여 게이트(4)와 게이트절연막(3)의 측면에 잔류한 제 2 산화막(5)으로 이루어진 측벽(5)을 형성한다.Then, the second conductivity type p-type impurity ion implantation using the gate as a mask is carried out at low concentration on the entire surface of the substrate 1 to define a lightly doped drain formation portion (not shown) at the lower ends of both gates, and again the substrate ( The second oxide film 5 is deposited on the entire surface of 1) and then etched back to form a sidewall 5 formed of the gate oxide 4 and the second oxide film 5 remaining on the side of the gate insulating film 3.
그 다음 게이트(4) 등을 포함하는 기판(1)의 전면에 알파-실리콘층(6)을 저압화학기상증착법(LPCVD)으로 증착하여 형성한다.An alpha-silicon layer 6 is then formed on the entire surface of the substrate 1 including the gate 4 or the like by vapor deposition using low pressure chemical vapor deposition (LPCVD).
도 1b를 참조하면, 알파-실리콘층(6) 위에 금속층(7)인 타이타늄층(7)을 화학기상증착법(CVD)으로 증착하여 형성한다. 이때 금속층은 실리콘과 잘 융합하여 실리사이드를 형성할 수 있는 금속을 사용한다.Referring to FIG. 1B, a titanium layer 7, which is a metal layer 7, is deposited on the alpha-silicon layer 6 by chemical vapor deposition (CVD). At this time, the metal layer uses a metal that can fuse well with silicon to form a silicide.
도 1c를 참조하면, 알파-실리콘층(6)과 타이타늄층(7)에 약 650 도씨하에서 20 분간 가열하여 알파-실리콘과 타이타늄의 합금인 실리사이드층(67)을 형성한다. 이때 형성된 실리사이드는 TiSi2이다. 따라서 형성된 실리사이드층(67)의 일부는 n 형 실리콘기판(1)의 표면과 직접 접촉하게 된다.Referring to FIG. 1C, the alpha-silicon layer 6 and the titanium layer 7 are heated at about 650 degrees C for 20 minutes to form a silicide layer 67 which is an alloy of alpha-silicon and titanium. The silicide formed at this time is TiSi 2 . Thus, part of the formed silicide layer 67 is in direct contact with the surface of the n-type silicon substrate 1.
그리고 실리사이드층을 고농도의 p+형으로 도핑시키기 위하여 실리사이드층(67)의 전면에 각각, 게르마늄 이온주입을 60 - 80 KeV의 에너지와 5.0E14 도우즈로 하고 붕소 이온주입을 10 - 20 KeV의 에너지와 5.0E15 도우즈로 실시한다. 이때 게르마늄 이온은 이후 졍션의 전기 전도도를 향상시켜 졍션저항을 낮추고 붕소이온의 확산을 저지하는 역할을 한다. 또한 이온주입이 기판에 직접 실시되지 아니하고 실리사이드층(67)에 실시되므로 종래 기술에서와 비교하여 이온주입에 의한 벌크 실리콘 구조의 결함 발생을 최소화할 수 있다.In order to dope the silicide layer with a high concentration of p + type, germanium ion implantation was performed at 60-80 KeV energy and 5.0E14 dose, and boron ion implantation energy was applied at the front surface of the silicide layer 67, respectively. And 5.0E15 doses. In this case, germanium ions later improve the electrical conductivity of the cushion to lower the cushion resistance and serves to prevent the diffusion of boron ions. In addition, since the ion implantation is performed directly on the silicide layer 67 rather than directly on the substrate, it is possible to minimize the occurrence of defects in the bulk silicon structure by ion implantation, as compared with the conventional art.
도 1d를 참조하면, 고농도의 제 2 도전형인 p 형 이온으로 도핑된 실리사이드층(68) 위에 포토레지스트를 도포한 다음 소스/드레인 형성용 마스크를 이용한 사진공정을 실시하여 포토레지스트패턴(도시 안함)을 형성한 다음 이로부터 보호되지 아니하는 부위의 도핑된 실리사이드층(68)을 식각하여 잔류한 실리사이드층(68)으로 이루어진 실리사이드패턴(68)을 형성한다. 이때 실리사이드패턴(68)의 하부의 기판(1)이 소스/드레인 형성부위가 된다.Referring to FIG. 1D, a photoresist is applied onto a silicide layer 68 doped with a high concentration of a second conductivity type p-ion, followed by a photoresist pattern using a source / drain forming mask (not shown). And then the doped silicide layer 68 in portions not protected from it are etched to form a silicide pattern 68 made of the remaining silicide layer 68. At this time, the substrate 1 below the silicide pattern 68 becomes a source / drain formation site.
도 1e를 참조하면, 소스/드레인의 고농도로 도핑된 셸로우 졍션을 형성하기 위하여 도핑된 실리사이드층(68)에 드라이브-인(drive-in) 열공정을 실시하여 도핑된 실리사이드층(68)의 불순물이온들이 기판(1) 영역으로 확산되게 한다. 이때 확산되어 형성된 제 2 도전형 확산영역(8)이 소스/드레인 영역이 된다. 즉 이는 이전에 형성된 엘디디 부위(도시안함)와 연결되어 트랜지스터 소자를 완성하게 된다.Referring to FIG. 1E, the doped silicide layer 68 is subjected to a drive-in thermal process to form a heavily doped shallow section of the source / drain. Impurity ions are allowed to diffuse into the substrate 1 region. At this time, the second conductive diffusion region 8 formed by diffusion becomes a source / drain region. In other words, it is connected to a previously formed LED portion (not shown) to complete the transistor device.
따라서, 본 발명은 금속층과 실리콘층 사이에 알파-실리콘층을 개재시켜 금속층과 알파-실리콘층으로 부터 형성된 실리사이드를 만든 다음 여기에 게르마늄 이온과 붕소이온을 주입하므로서 이를 간접적으로 실리콘 기판에 드라이브-인시켜 얕은 깊이를 갖는 졍션을 형성하기 때문에 졍션의 누설전류를 감소시키고 졍션 저항을 낮추어 소자의 특성을 향상시키는 장점이 있다.Therefore, the present invention forms a silicide formed from the metal layer and the alpha-silicon layer by interposing an alpha-silicon layer between the metal layer and the silicon layer, and then injects germanium ions and boron ions into the silicon substrate to drive-in the silicon substrate indirectly. As a result, a shallow depth caption is formed, which reduces the leakage current of the caption and lowers the caption resistance, thereby improving the device characteristics.
또한 졍션 형성을 위한 이온주입이 실리사이드층에 실시되므로 벌크 실리콘 구조의 결함 발생을 최소화할 수 있는 장점이 있다.In addition, since ion implantation for the formation of the cushion is performed on the silicide layer, there is an advantage of minimizing the occurrence of defects in the bulk silicon structure.
Claims (8)
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| KR100442145B1 (en) * | 2001-12-27 | 2004-07-27 | 동부전자 주식회사 | Method for improvement silicide by using argon, germanium, arsenic gas |
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