KR100266669B1 - Circuit for generating internal clock of semiconductor memory - Google Patents

Abstract

PURPOSE: A circuit for generating an internal clock of a semiconductor memory is provided to prevent the waste of current with disabling a duty cycle correcting portion individually by preventing the waste of time with reaching the level needed in correcting the duty ratio in the duty cycle. CONSTITUTION: The circuit for generating the internal clock of the semiconductor memory includes a clock buffer(11), the first control portion(12), the second control portion(13), a duty cycle correcting portion(14) and a frequency doubling portion(15). The clock buffer(11) buffers the external clock. The first control portion(12) outputs the duty cycle correcting clock signal and permits or intercepts the first and second driving signals and the control signal and the duty cycle correcting driving signal. The duty cycle correcting portion(14) compensates the duty ratio of the duty cycle correcting clock signal outputs it and outputs the driving voltage for compensating the duty ratio. The second control portion(13) outputs the driving voltage to the duty cycle correcting portion(14) again. The frequency doubling portion(15) doubles the frequency of the output signal of the duty cycle correcting portion(14) and outputs it.

Description

Internal Clock Generation Circuit of Semiconductor Memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal clock generation circuit of a semiconductor memory, and more particularly, to generate an internal clock of a semiconductor memory that is suitable for operation at a low power supply by limiting the operation of active, standby and power down modes. It is about a circuit.

FIG. 1 is a block diagram showing an internal clock generation circuit of a conventional semiconductor memory. As shown in FIG. 1, a clock buffer 1 receives and buffers an external clock EXT_CLK and a reference voltage Vref; The output of the clock buffer 1 (CLK_BUF, A duty cycle corrector 2 for correcting the duty cycle and returning it to the clock buffer 1; The duty cycle corrector 2 receives the output of the clock buffer 1 whose duty cycle has been calibrated, and the divided clocks I_CLK, Q_CLK, , A quadrature dispensing unit 3 for generating); An exclusive orthogonal combination unit 4 which receives the output of the quadrature divider 3 and generates a doubled output DBL_CLK.

FIG. 2 is an internal circuit diagram of the duty cycle corrector 2. As shown in FIG. 2, the output of the clock buffer 1 (CLK_BUF, N) and NMOS transistors NM1 and NM2 connected to a common source; An enMOS transistor NM3 connected to the ground and the common source of the NMOS transistors NM1 and NM2, the driving signal Ven being input to the gate; PIM transistors PM1 and PM4 having a source connected to the power supply voltage VCC and having drains connected to drains of the NMOS transistors NM1 and NM2, respectively; A PMOS transistor PM2 having a source connected to the power supply voltage VCC, and a gate and a drain thereof commonly connected to the gate of the PMOS transistor PM1; A source is connected to the power supply voltage VCC, the gate and the drain are constituted by a PMOS transistor PM3 commonly connected to the gate of the PMOS transistor PM4, and the drains of the PMOS transistors PM1 and PM3 are common. Output signal inverted through the connected capacitor C1 ), The drains of the PMOS transistors PM2 and PM4 are commonly connected, and the output signal DCC is output through the grounded capacitor C2.

The operation of the conventional circuit as described above will be described below.

When the external clock (EXT_CLK) passes the clock buffer (1), it is input as a clock that is out of 50% duty ratio, unlike the clock given initially due to various factors (process change, temperature change, etc.) Get involved.

Therefore, the duty cycle corrector 2, which is an analog circuit, outputs the clock CLK_BUF, ) And the output signal (DCC, which is an analog voltage signal) by charging and discharging the capacitors (C2, C1) according to the pulse width. ) And this output signal (DCC, ) Is inputted to the clock buffer 1 by the feedback loop to output the clock buffer 1 (CLK_BUF, ) Pulse width is compensated by a clock with a 50% duty ratio.

The output of the clock buffer 1 compensated in this way (CLK_BUF, ) And the divided clocks (I_CLK, Q_CLK, , ), And the exclusive oar combination unit 4 symmetrically combines the output of the quadrature divider 3 to generate a doubled output DBL_CLK.

However, since the internal clock generation circuit of the conventional semiconductor memory as described above takes a long time until the output signal of the duty cycle correction unit reaches a constant level, the internal clock generation circuit must always be active even in the standby mode or the power down mode. There was a problem that the current is wasted.

The present invention has been made to solve the above problems, and an object of the present invention is to operate in a low power supply by limiting the operation of the active, standby and power down modes, and to switch from the standby or power down mode to the active mode. It is to provide an internal clock generation circuit of a semiconductor memory that can quickly calibrate the duty cycle.

1 is a block diagram showing an internal clock generation circuit of a conventional semiconductor memory.

2 is an internal circuit diagram of a duty cycle correction unit in FIG. 1;

Figure 3 is a block diagram showing an embodiment of the present invention.

FIG. 4 is a circuit diagram of the first control unit in FIG. 3; FIG.

FIG. 5 is a circuit diagram of the second control unit in FIG. 3; FIG.

6 is a waveform diagram of an input / output signal in FIG.

*** Description of the symbols for the main parts of the drawings ***

EXT_CLK: External Clock 11: Clock Buffer

ACTIVE: Active signal PWROK: Power ok signal

IN_EN: Input enable signal DCC_CLK: Duty cycle calibration clock signal

EN1, EN2: Drive signal CS1: Control signal

DCC_EN: Duty cycle calibration drive signal 12, 13: 1st, 2nd control part

CNTL: Drive Voltage CNTL_REF: Drive Reference Voltage

14: duty cycle correction unit 15: frequency doubling unit

DBL_CLK: Output signal

An object of the present invention as described above is a clock buffer for receiving and buffering an external clock; By logically combining the active signal, the power ok signal, and the input enable signal, which are inherent signals of the synchronous DRAM, the duty cycle correction clock is synchronized with the output signal of the clock buffer depending on whether the input enable signal is applied. A first control unit which outputs a signal and applies or blocks the first and second drive signals, the control signal and the duty cycle calibration drive signal; A duty cycle corrector configured to compensate for and output a duty ratio of the duty cycle correction clock signal according to the duty cycle correction drive signal input from the first controller, and output a driving voltage to compensate for the duty ratio; The first and second drive signals are input from the first controller, the drive voltage is input from the duty cycle corrector, and the drive voltage is maintained at the drive reference voltage. The duty cycle is changed back to the drive voltage according to the control signal. A second control unit outputting to the government; This is achieved by configuring a frequency doubling unit for doubling and outputting the frequency of the duty cycle corrector output signal. The internal clock generation circuit of the semiconductor memory according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing an embodiment of the present invention, and a clock buffer 11 for receiving and buffering an external clock EXT_CLK as shown therein; By combining the active signal ACTIVE, the power ok signal PWROK, and the input enable signal IN_EN, which are inherent signals of the synchronous DRAM, the clock buffer 11 is outputted according to whether the input enable signal IN_EN is applied. A first control unit for outputting the duty cycle correction clock signal DCC_CLK in synchronization with BUF_CLK, and applying or blocking the driving signals EN1 and EN2, the control signal CS1, and the duty cycle correction driving signal DCC_EN. 12); The duty cycle of the duty cycle correction clock signal DCC_CLK is compensated for and output according to the duty cycle correction driving signal DCC_EN input from the first controller 12, and a driving voltage CNTL for compensating for the duty ratio is output. A duty cycle corrector 14; The driving signals EN1 and EN2 are input from the first controller 12 and the driving voltage CNTL is input from the duty cycle corrector 14 to maintain the level of the driving voltage CNTL. A second controller 13 outputting the driving cycle CNTL to the duty cycle corrector 14 again; And a frequency doubling unit 15 which doubles the frequency of the output of the duty cycle corrector 14 and outputs the output signal as the output signal DBL_CLK. Hereinafter, the operation of one embodiment of the present invention as described above will be described.

First, the first controller 12 logically combines the active signal ACTIVE, the power ok signal PWROK, and the input enable signal IN_EN, thereby providing a clock buffer 11 according to whether the input enable signal IN_EN is applied. Outputs the duty cycle correction clock signal DCC_CLK in synchronization with the output signal BUF_CLK, and also applies or blocks the driving signals EN1 and EN2, the control signal CS1, and the duty cycle correction driving signal DCC_EN. .

The first control unit 12 receives the power ok signal PWROK through the inverter INV11 on one side and the active signal ACTIVE on the other side, as shown in the circuit diagram of FIG. 4. Noah gate (NOR11) and; A NAND gate NAND11 configured to receive an input enable signal IN_EN on one side and to NAND the output of the NOA gate NOR11 on the other side through the inverter INV12; An inverter INV13 that inverts the output of the NAND gate NAND11 to output the duty cycle correction drive signal DCC_EN, and an inverter INV14 that inverts the output of the inverter INV13 and outputs the control signal CS1; ; A flip-flop (F / F) which receives the output of the inverter (INV13) to the input terminal (D) and outputs it through the output terminal (Q) in synchronization with the output (BUF_CLK) of the clock buffer (11); Inverters INV15 and INV16 which invert the output of the flip-flop F / F in order to output the duty cycle correction clock signal DCC_CLK; Inverters INV17 and INV18 for inverting the output of the NAND gate NAND11 and outputting a driving signal EN1; A NAND gate NAND12 for directly inputting the output of the inverter INV18 to one side and receiving and inputting the input through the inverter INV19 and the delay unit 21 to the other side; An inverter INV20 for inverting the output of the NAND gate NAND12 and outputting the driving signal EN2.

Therefore, when power is initially applied, the duty cycle correction unit 14 outputs the duty cycle correction driving signal DCC_EN output from the first control unit 12 by the power ok signal PWROK and the input enable signal IN_EN. To correct the duty cycle so that the duty cycle correction clock signal DCC_CLK input to the duty cycle corrector 14 has a duty ratio of 50%, and the driving voltage CNTL for compensating for the duty ratio is a second value. It is input to the control part 13. On the other hand, the output of the duty cycle corrector 14 is input to the frequency doubling unit 15 to output the doubled output signal DBL_CLK.

The operation after the initial power-up is finished is controlled by the active signal ACTIVE. That is, the circuit operates by the active signal ACTIVE only in the active mode, and the duty cycle correction drive signal DCC_EN is disabled in the standby and power-down modes so that the duty cycle corrector 14 does not operate. do.

However, at this time, the second control unit 13 receives the driving signals EN1 and EN2 from the first control unit 12, receives the driving voltage CNTL from the duty cycle corrector 14, and receives the driving voltage CNTL. The level is maintained at the driving reference voltage CNTL_REF. Subsequently, when the standby mode and the power down mode are switched to the active mode, the driving reference voltage CNTL_REF is output to the duty cycle corrector 14 as the driving voltage CNTL according to the control signal CS1.

As shown in the circuit diagram of FIG. 5, the second control unit 13 receives the driving signals EN1 and EN2, respectively, the source is grounded, and the drain is commonly connected to the NMOS transistor NM11, NM12); A source is connected to the drain of the NMOS transistor NM11, a gate and a drain are commonly connected, and a source is connected to the drain of the NMOS13 and NMOS transistors grounded through the capacitor C11. And an MOS transistor NM14 whose gate is grounded through a capacitor C12; An MOS transistor (NM15) whose input signal is supplied to a gate thereof, whose source is connected to the gate of the NMOS transistor (NM13), and whose drain is connected to the gate of the NMOS transistor (NM14); The driving signal EN1 is input to each gate, a source is connected to the power supply voltage VDD, and a drain is connected to the PMOS transistors PM11 and PM12 respectively connected to the drains of the NMOS transistors NM13 and NM14. ; A PMOS transistor PM13 whose source is connected to the power supply voltage VDD and whose drain is connected to the drain of the PMOS transistor PM11; PMOS transistor PM14 having a source connected to the power supply voltage VDD, a gate connected to the gate of the PMOS transistor PM13, a drain connected to the gate, and commonly connected to the drain of the PMOS transistor PM12. It consists of.

Accordingly, when the standby cycle and the power down mode are switched to the active mode, the duty cycle corrector 14 is driven, and at this time, the level of the drive voltage CNTL is equal to that of the drive reference voltage CNTL_REF stored by the second controller 13. Having a level, it is within a few cycles to reach the level required for duty ratio correction.

The operation of one embodiment of the present invention as described above will be described in more detail with reference to FIG. 6, which is a waveform diagram of each signal.

The operation for duty ratio correction and frequency doubling in the period where the initial power ok signal PWROK is low potential (i.e., the power-on period) takes many cycles as in the prior art, but the period where the power ok signal PWROK is high potential ( That is, if the active signal ACTIVE is at high potential, the duty cycle correction driving signal DCC_EN is output at high potential to drive the duty cycle corrector 14 while the active signal ACTIVE is at low potential. The duty cycle correction driving signal DCC_EN is output at a low potential to block driving of the duty cycle corrector 14.

In addition, when the duty cycle corrector 14 is driven, the driving signal EN1 and the control signal CS1 are applied to the second control unit 13 at a low potential, so that the NMOS transistor NM15 is turned off and the capacitor ( C1) charges the high potential to the driving reference voltage CNTL_REF.

The driving reference voltage CNTL_REF is applied as the driving voltage CNTL by the control signal CS1 when the duty cycle corrector 14 is disabled and then driven again.

As described above, the internal clock generation circuit of the semiconductor memory according to the present invention prevents wasting time by reaching the level required for duty ratio correction within a few cycles when the duty cycle corrector is disabled and then driven again. The wealth can be independently disabled, preventing current waste.

Claims (3)

A clock buffer which receives and buffers an external clock; By combining the active signal, the power ok signal, and the input enable signal, which are inherent signals of the synchronous DRAM, the duty cycle correction clock signal is output in synchronization with the output signal of the clock buffer depending on whether the input enable signal is applied. A first control unit which applies or blocks the first and second drive signals, the control signal and the duty cycle calibration drive signal; A duty cycle corrector configured to compensate for and output a duty ratio of the duty cycle correction clock signal according to the duty cycle correction drive signal input from the first controller, and output a driving voltage to compensate for the duty ratio; The first and second drive signals are input from the first controller, the drive voltage is input from the duty cycle corrector, and the drive voltage is maintained at the drive reference voltage. The duty cycle is changed back to the drive voltage according to the control signal. A second control unit outputting to the government; And a frequency doubling unit for doubling and outputting the frequency of the duty cycle corrector output signal. 2. The apparatus of claim 1, wherein the first control unit comprises: a NOA gate receiving a power ok signal through a first inverter on one side and an NOA receiving on the other side; A first NAND gate configured to receive an input enable signal on one side, and to NAND the output of the NOA gate on the other side through a second inverter; A third inverter for inverting the output of the first NAND gate and outputting a duty cycle correction driving signal and a fourth inverter for inverting the output of the third inverter and outputting a control signal and a first driving signal; A flip-flop receiving an output of the third inverter at an input terminal and outputting a duty cycle corrected clock signal through an output terminal in synchronization with an output of a clock buffer; A second NAND gate that directly receives the output of the fourth inverter on one side and receives and inputs the NAND through the fifth inverter and the delay unit on the other side; And a sixth inverter for inverting the output of the second NAND gate and outputting a second drive signal. 2. The display device of claim 1, wherein the second control unit comprises: an MOS transistor (NM11, NM12) having a driving signal (EN1, EN2) respectively input to a gate, a source of which is grounded, and a drain of which is commonly connected; A source is connected to the drain of the NMOS transistor NM11, a gate and a drain are commonly connected, and a source is connected to the drain of the NMOS13 and NMOS transistors grounded through the capacitor C11. And an MOS transistor NM14 whose gate is grounded through a capacitor C12; An MOS transistor (NM15) whose input signal is supplied to a gate thereof, whose source is connected to the gate of the NMOS transistor (NM13), and whose drain is connected to the gate of the NMOS transistor (NM14); The driving signal EN1 is input to each gate, a source is connected to the power supply voltage VDD, and a drain is connected to the PMOS transistors PM11 and PM12 respectively connected to the drains of the NMOS transistors NM13 and NM14. ; A PMOS transistor PM13 having a source connected to the power supply voltage VDD and a drain connected to the drain of the PMOS transistor PM11; PMOS transistor PM14 having a source connected to the power supply voltage VDD, a gate connected to the gate of the PMOS transistor PM13, a drain connected to the gate, and commonly connected to the drain of the PMOS transistor PM12. An internal clock generation circuit of a semiconductor memory, characterized in that consisting of.