JP7506517B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device.

Semiconductor devices such as SoC (System on Chip) have a CPU, digital circuit, and ADC that operate based on a clock generated by a crystal oscillation circuit. ADC is an abbreviation for analog-to-digital conversion circuit. There is an increasing need for low-noise, high-resolution ADCs in the control of various sensors such as image sensors and area sensors, and in sensorless vector control of motors. A crystal oscillation circuit generates a clock by passing an excitation current through a crystal oscillator to oscillate the crystal oscillator, but this excitation current can cause noise. If the generated noise is coupled to the input terminal of the ADC, the conversion error of the ADC will increase. According to Patent Document 1, a crystal oscillation circuit that suppresses noise using an inverter circuit with constant current characteristics is proposed.

JP 2008-263312 A

However, simply adjusting the negative resistance of the crystal oscillator circuit makes it difficult to meet the noise requirements required for recent high-performance applications. Therefore, the present invention aims to provide a semiconductor device that is less susceptible to the effects of coupling noise in the clock signal generated by the oscillator circuit.

Therefore, the present invention provides
an oscillation circuit that supplies an excitation current to an oscillator to oscillate the oscillator and generate a clock signal;
A control circuit for controlling a drive level required for the oscillator circuit to oscillate the vibrator;
a sample and hold circuit that samples and holds an analog input signal;
an analog-to-digital conversion circuit that operates by receiving a system clock derived from the clock signal generated by oscillating the oscillator and converts the voltage of the analog input signal held by the sample-and-hold circuit into digital data;
having
The semiconductor device is characterized in that the control circuit is configured to reduce the excitation level required to oscillate the vibrator of the oscillation circuit from a first excitation level to an Nth excitation level between the start and end of the i-th sampling of the sample and hold circuit, and to return the excitation level of the oscillation circuit to the first excitation level between the end of the i-th sampling of the sample and hold circuit and the start of the i+1-th sampling of the sample and hold circuit.

The present invention provides a semiconductor device that is less susceptible to coupling noise in the clock signal generated by the oscillator circuit.

Block diagram showing a semiconductor device Circuit diagram showing the oscillator circuit Circuit diagram showing a tri-state inverter Block diagram showing the main control circuits Flowchart showing the control method Timing chart of signals related to the oscillator circuit and ADC Block diagram showing the main control circuits Flowchart showing the control method Timing chart of signals related to the oscillator circuit and ADC

The embodiments are described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe multiple features, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicate explanations are omitted.

Example 1
(1) Semiconductor Device As shown in FIG. 1, a semiconductor device 1 has various circuits. An oscillation circuit 10 generates a clock signal by supplying an excitation current to a crystal oscillator 2 to vibrate the crystal oscillator 2. A PLL (Phase Locked Loop) 12 generates a system clock by multiplying a clock signal (reference clock) generated by the oscillation circuit 10. A CPU 14, a GPIO 16, an ADC 17, and a functional block (not shown) are a group of circuits that operate by receiving the system clock. GPIO is an abbreviation for general-purpose input/output circuit. A switching circuit 15 switches the connection of an external signal terminal IO between an ADC 17 and a GPIO 16. The ADC 17 converts the voltage of an analog input signal input from the external signal terminal IO into digital data. The GPIO 16 switches whether to function as an input terminal of the external signal terminal IO or as an output terminal. The internal power supply 13 converts the voltage supplied from the external power supply terminal VCC to generate a voltage for operating the internal logic, and outputs the voltage to the internal power supply terminal VDD. In this way, by providing the internal power supply 13, it becomes possible to mix a plurality of circuit groups with different operating voltages inside the semiconductor device 1. The external power supply terminal VCC is connected to the internal power supply 13, the oscillation circuit 10, the ADC 17, and the switching circuit 15. The internal power supply terminal VDD is connected to the PLL 12, the CPU 14, and the GPIO 16. The external ground terminal VSS is a terminal connected to the ground layer or frame ground of the printed circuit board on which the semiconductor device 1 is mounted.

(2) Oscillation Circuit As shown in FIG. 2, the oscillation circuit 10 has a feedback resistor R1 and n tri-state inverters IV1, IV2, ..., IVn, each of which is connected in parallel to the crystal resonator 2. The sizes of the n tri-state inverters IV1, IV2, ..., IVn may be different or the same. Hereinafter, the tri-state inverters IV1, IV2, ..., IVn may be collectively referred to as tri-state inverters IV. The tri-state inverter IV has a select terminal E, an output terminal O, and an input terminal I. When the logic of the select terminal E becomes "L", the state of the output terminal O becomes a floating state independent of the logic of the input terminal I. When the logic of the select terminal E becomes "H", the logic of the output terminal O becomes the inverse of the logic of the input terminal I. The CPU 14 adjusts the negative resistance and the excitation level of the oscillation circuit 10 by switching the logic of the enable signals E1, E2, ..., En. The logical combination of the enable signals E1, E2, ..., En is selected so as to obtain a sufficiently large negative resistance with respect to the equivalent series resistance of the crystal unit 2. The drive level is selected within a range not exceeding the power rating of the crystal unit 2.

A capacitor C1 is connected between one end of the crystal oscillator 2 and ground. A capacitor C2 is connected between the other end of the crystal oscillator 2 and ground. The crystal oscillator 2 connected in parallel to the oscillation circuit 10 may be another type of oscillator, such as a ceramic oscillator.

(3) Tri-state inverter As shown in Fig. 3, the tri-state inverter IV has six transistors. The PMOS transistors QP1 and QP2 are connected in series between the power supply node and the output terminal O. The NMOS transistors QN1 and QN2 are connected in series between the GND (ground) node and the output terminal O. The input terminal I is connected to the gates of the MOS transistors QP2 and QN1, respectively. The PMOS transistor QP3 and NMOS transistor QN3 are connected in series between the power supply node and the GND node. The select terminal S is connected to the gate of the MOS transistor QP3, the gate of QN3, and the gate of the NMOS transistor QN2. The drains of the MOS transistors QP3 and QN3 are connected to the gate of the PMOS transistor QP1.

When the logic of the select terminal S becomes "L", the NMOS transistor QN2 turns off. Also, when the logic of the select terminal S becomes "L", the PMOS transistor QP1 also turns off. This is because a signal generated by inverting the logic of the signal applied to the select terminal S by the MOS transistors QP3 and QN3 is applied to the gate of the PMOS transistor QP1. As a result, the output terminal O becomes floating, regardless of the logic of the input terminal I.

When the logic of the select terminal S becomes "H", the PMOS transistor QP1 and the NMOS transistor QN2 are turned on. When the logic of the select terminal S becomes "H", the inverted logic of the signal applied to the input terminal I is output to the output terminal O. The drive current per tri-state inverter IV is determined depending on the sizes of the MOS transistors QP1, QP2, QN1, and QN2.

Here, a CMOS logic type has been described as an example of the tri-state inverter IV. However, the tri-state inverter IV may be configured with a CMOS analog circuit such as an inverting amplifier or a comparator. The MOS transistors QP1 and QN2 may be replaced with a constant current source.

(4) Peripheral Blocks As shown in FIG. 4, the CPU 14 writes instructions to a register 261 of the GPIO control unit 26 , a register 271 of the ADC control unit 27 , and a register 201 of the oscillation control unit 20 via the internal bus 100 .

The GPIO control unit 26 determines the connection destination of the switching circuit 15 according to the digital/analog switching setting stored in the register 261 by the CPU 14. When digital is selected, the switching circuit 15 connects the external signal terminal IO to the GPIO 16. The GPIO control unit 26 sends the input or output switching setting specified by the CPU 14 to the GPIO 16. When the GPIO 16 is switched to output, the GPIO control unit 26 sets an output value (logic) to the GPIO 16. When the GPIO 16 is switched to input, the GPIO control unit 26 receives an input value (logic) from the GPIO 16.

The GPIO control unit 26 determines the connection destination of the switching circuit 15 to the ADC 17 according to the digital/analog switching setting stored in the register 261. The ADC 17 is a successive approximation type analog-to-digital conversion circuit. The ADC 17 includes a sample-and-hold switch 171, a sample-and-hold capacitor Csh, and a conversion unit 172. In particular, the sample-and-hold switch 171 and the sample-and-hold capacitor Csh form a sample-and-hold circuit. When the sample-and-hold switch 171 is turned on, the voltage of the external signal terminal IO is applied to the sample-and-hold capacitor Csh, and the sample-and-hold capacitor Csh is charged. When the sample-and-hold switch 171 is turned off, the voltage of the sample-and-hold capacitor Csh is held. The conversion unit 172 converts the voltage held in the sample-and-hold capacitor Csh into a digital value. The digital value may be called digital data or ADC data.

The ADC control unit 27 includes a register 271 and a timing generation unit 272. The CPU 14 stores in the register 271 a command for starting/stopping the ADC 17 and setting values such as the on-timing and off-timing of the sample-and-hold switch 171. The timing generation unit 272 controls the H/L timing of the sample-and-hold signal and the output timing of the excitation level switching signal based on the values set by the register 271. The ADC control unit 27 stores the ADC data generated by the conversion unit 172 in the register 271. As a result, the CPU 14 acquires the ADC data via the register 271.

The oscillation control unit 20 includes a register 201, a selector 202, and a decoder 203. The register 201 stores at least two excitation level setting values to be set in the oscillation circuit 10. In the first embodiment, for convenience, the first excitation level setting value and the second excitation level setting value are stored in the register 201. The first excitation level is greater than the second excitation level. The selector 202 selects either the first excitation level or the second excitation level in response to a switching signal output from the timing generation unit 272. The decoder 203 converts the excitation level setting value selected by the selector 202 into an enable signal EN for the oscillation circuit 10.

The CPU 14 accesses the memory 18 via the internal bus 100. The memory 18 has a ROM area and a RAM area. The ROM area stores the control program.

5 shows a control procedure executed by the CPU 14 in accordance with a control program. In step S501, when power is supplied to the semiconductor device 1 from an external power source, the CPU 14 reads out and starts the control program stored in the memory 18.

In S502, the CPU 14 sets the excitation level during steady-state operation of the oscillator circuit 10 and the excitation level when the ADC 17 is performing sampling. The set values of these excitation levels are stored in the memory 18. The CPU 14 reads these set values from the memory 18 and sets them in the register 201.

In S503, the CPU 14 sets the sampling time (the period T during which the sample-and-hold signal SH is "H"). For example, the CPU 14 writes the sampling time to the register 271 via the internal bus 100.

In S504, the CPU 14 sets the switching time tx of the excitation level. For example, the CPU 14 writes the switching time tx to the register 271 via the internal bus 100. In S505, the CPU 14 instructs the ADC control unit 27 to start the ADC 17. The ADC control unit 27 starts the ADC 17 according to the instruction from the CPU 14.

(6) Timing Chart FIG. 6 is a timing chart of signals related to the oscillator circuit 10 and the ADC 17. In FIG. 6, the drive level is simply written as level. It is assumed that the ADC 17 is started at time t0. At time t1, the sample hold signal is switched from L to H. Time t1 is the timing specified by the CPU 14. Time t2 is the timing when the drive level is switched from the first drive level to the second drive level. Time t3 is the timing when the sample hold signal is switched from H to L. Time t4 is the timing when the drive level is switched from the second drive level to the first drive level. The switching time tx is the period from time t2 to time t4.

The reference clock CLK generated by the oscillator circuit 10 fluctuates the voltage of the external power supply terminal VCC and the voltage of the external ground terminal VSS. This fluctuation can occur at the rising and falling edges of the reference clock CLK. When the voltage of the external power supply terminal VCC and the voltage of the external ground terminal VSS fluctuate, the output of the external signal terminal IO also fluctuates. As described above, the switching circuit 15 and the sample-and-hold switch 171 are powered by the same power supply. Therefore, the rising noise and falling noise of the reference clock CLK can be coupled to the external signal terminal IO via these stray capacitances.

On the other hand, the system clock generated by the PLL 12 is used as an operating clock for logic circuits (e.g., the CPU 14, the ADC control unit 27, and the oscillation control unit 20). When the ADC control unit 27 starts the ADC 17 according to the instruction of the CPU 14, the external signal terminal IO is connected to the sample hold capacitor Csh in synchronization with the rising edge of the preset sample hold signal SH. The voltage of the external signal terminal IO fluctuates due to switching noise generated when the sample hold switch 171 is turned on from off. The fluctuating voltage converges according to a time constant that depends on the external impedance connected to the sample hold capacitor Csh and the external signal terminal IO, and is held in synchronization with the falling edge of the sample hold signal SH. The falling timing of the sample hold signal and the rising or falling timing of the reference clock CLK may overlap. In this case, the voltage of the sample hold capacitor Csh is held in a state that is significantly different from the original voltage due to the influence of the coupling noise of the reference clock CLK.

Therefore, in the first embodiment, the excitation level switching signal transitions from "L" to "H" at a timing (time t2) after the rising timing (time t1) of the sample and hold signal. Furthermore, the excitation level switching signal transitions from "H" to "L" at a timing (time t4) after the falling timing (time t3) of the sample and hold signal. This causes the excitation level to drop from the first excitation level to the second excitation level at the voltage holding timing of the sample and hold capacitor Csh. In other words, the excitation level is maintained at the second excitation level for only the switching time tx. As a result, the influence of coupling noise of the reference clock CLK is reduced.

The amount of reduction in the excitation level is set so as to ensure the stability of the reference clock CLK and to satisfy the required conversion accuracy of the ADC 17. The amount of reduction in the excitation level is the difference between the first excitation level and the second excitation level.

The setting of the period T (the period from t1 to t2) during which the excitation level switching signal is "H" may be adjusted by a circuit or device connected to the external signal terminal IO. If the capacitance of the capacitor connected to the external signal terminal IO is large, the fluctuation of the terminal voltage due to the influence of coupling noise will be small. Therefore, the period T may be set to as short a time as possible. For example, the period T may be set to a time longer than the rise time or fall time of the reference clock CLK and shorter than one period of the reference clock CLK.

When the external impedance connected to the external signal terminal IO is low, convergence is fast regardless of the amount of fluctuation in the terminal voltage due to the influence of coupling noise. Therefore, the period T is set to a short time. On the other hand, when the external impedance is high, the fluctuation in the terminal voltage due to the influence of coupling noise becomes large. Therefore, the period T is set to the longest possible time. For example, the period T is set to the settling time determined by the external impedance and the sample-and-hold capacitor Csh.

As explained above, by temporarily lowering the excitation level, the coupling noise generated at the external signal terminal IO is significantly reduced. As a result, the voltage of the input analog signal is held with high precision by the sample-and-hold capacitor Csh. The conversion unit 172 of the ADC 17 converts this voltage to generate ADC data, allowing the CPU 14 to obtain highly accurate ADC data.

Only one external signal terminal IO is connected to ADC17, but this is merely one example. By replacing switching circuit 15 with a multiplexed switching circuit, it is possible to connect multiple external signal terminals IO to ADC17. In this case, register 201 may store an excitation level for each of the multiple external signal terminals IO. In other words, CPU 14 reads from memory 18 the first excitation level and second excitation level corresponding to one external signal terminal IO selected from the multiple external signal terminals IO, and writes them to register 201. This would be effective when the appropriate combination of two excitation levels differs for each external signal terminal IO.

Example 2
In the first embodiment, an example in which the first excitation level is temporarily lowered to the second excitation level is described. However, when the first excitation level is switched to the second excitation level, the frequency of the reference clock CLK generated from the oscillation circuit 10 may fluctuate. The allowable range of the frequency fluctuation of the reference clock CLK is a range in which the peripheral circuits that are supplied with the reference clock CLK and operate can operate normally. If the difference between the first excitation level and the second excitation level is too large, the frequency fluctuation of the reference clock CLK exceeds the allowable range. Therefore, in the second embodiment, the frequency fluctuation of the reference clock CLK is kept within the allowable range by switching three or more excitation levels in a stepwise manner.

Figure 7 shows the oscillation control unit 30 of the second embodiment. Descriptions of the second embodiment common to the first embodiment will be omitted. The oscillation control unit 30 includes a register 301, a selection unit 302, and a decoder 303. The register 301 stores the set values of N excitation levels, the number of switches X, the switching time tx, and the like written by the CPU 14. N is an integer equal to or greater than 3. The number of switches X is N-1. The switching time tx is the duration for which one excitation level continues.

The selection unit 302 selects the excitation level in synchronization with the switching signal generated by the ADC control unit 27. The selection unit 302 may select the excitation level according to the switching number X and the switching time tx. The selection unit 302 switches the excitation level when the switching signal is input. Furthermore, the selection unit 302 switches between the multiple excitation levels in sequence, starting from the timing when the switching signal is input and using the switching time tx as a period. For example, the first excitation level is switched to the second excitation level at the timing when the switching signal is input. The selection unit 302 adds 1 to the count value each time switching is performed. When the count value becomes the switching number X, the selection unit 302 may return the excitation level to the first excitation level. The decoder 303 converts the setting value of the selected excitation level into an enable signal EN and outputs it to the oscillation circuit 10.

Figure 8 shows the control procedure executed by the CPU 14 according to the control program. In S801, when power is supplied to the semiconductor device 1 from an external power source, the CPU 14 reads and starts the control program stored in the memory 18.

In S802, the CPU 14 sets the first excitation level during steady-state operation of the oscillator circuit 10, and the second excitation level to the Nth excitation level when the ADC 17 is performing sampling. The setting values of these excitation levels are stored in the memory 18. The CPU 14 reads these setting values from the memory 18 and sets them in the register 301.

In S803, the CPU 14 sets the sampling time (the period T during which the sample and hold signal SH is "H"). For example, the CPU 14 writes the sampling time to the register 271 via the internal bus 100.

In S804, the CPU 14 sets the start timing (time t2), end timing (time t4), and switching time tx for switching the excitation level. For example, the CPU 14 writes the start timing, end timing, and switching time tx to the register 301.

In S805, the CPU 14 sets the excitation level switching number X. For example, the CPU 14 writes the switching number X to the register 301.

In S806, the CPU 14 instructs the ADC control unit 27 to start the ADC 17. The ADC control unit 27 starts the ADC 17 according to the instruction from the CPU 14.

Figure 9 is a timing chart of signals related to the oscillator circuit 10 and ADC 17. Here, it is assumed that N=6. It is assumed that the ADC 17 is started at time t0. At time t1, the sample hold signal is switched from L to H. Time t1 is the timing specified by the CPU 14. Time t2 is the timing when the excitation level is switched from the first excitation level to the second excitation level. Time t3 is the timing when the sample hold signal is switched from H to L. Time t4 is the timing when the excitation level is switched from the second excitation level to the first excitation level.

In the second embodiment, the excitation level switching signal also transitions from "L" to "H" at a timing (time t2) after the rising timing (time t1) of the sample hold signal. As shown in FIG. 9, the excitation level is switched from the first excitation level to the second excitation level at the start timing, time t2. After that, the selection unit 302 selects the next excitation level and outputs it to the decoder 303 every time a switching time tx has elapsed from the timing of switching. For example, when the switching time tx has elapsed from time t2, the selection unit 302 switches the excitation level from the second excitation level to the third excitation level. When the switching time 2×tx has elapsed from time t2, the selection unit 302 switches the excitation level from the third excitation level to the fourth excitation level. When the switching time 3×tx has elapsed from time t3, the selection unit 302 switches the excitation level from the fourth excitation level to the fifth excitation level. When the switching time 4×tx has elapsed since time t2, the selection unit 302 switches the excitation level from the fifth excitation level to the sixth excitation level. When the end timing, time t4, arrives, the selection unit 302 returns the excitation level to the first excitation level. In this way, N-1 excitation levels are switched in sequence between time t2 and time t4.

The switching time tx may be set to be one or more periods of the reference clock CLK. Of the six excitation levels, the first excitation level is the excitation level set in the normal state. The fourth excitation level is the excitation level that can reduce noise the most. As shown in FIG. 9, during the period in which the fourth excitation level is applied, the ADC 17 executes a hold. The other excitation levels are determined to interpolate between the first excitation level and the fourth excitation level. For example, it is assumed that the jth excitation level of the N excitation levels is the smallest excitation level. In this case, the ith excitation level is lower than the i-1th excitation level (i is an integer from 2 to j). When i is an integer from j+1 to N, the ith excitation level is higher than the i-1th excitation level. The difference between the ith excitation level and the i-1th excitation level is constant. However, if the fluctuation of the reference clock CLK is within an allowable range, the difference between the ith excitation level and the i-1th excitation level does not have to be constant. In this way, the other excitation levels are gradually lowered or increased within a range in which the PLL 12 does not become unlocked due to frequency fluctuations in the reference clock CLK.

By gradually decreasing and increasing the excitation current of the oscillator circuit 10, the frequency fluctuation of the reference clock CLK becomes gentler, and it becomes possible to set the excitation level of the hold timing even lower. Therefore, compared to the first embodiment, the second embodiment can reduce the influence of coupling noise more. In other words, the noise applied to the external signal terminal IO is reduced, and the CPU 14 can obtain more accurate ADC data.

In FIG. 9, N is 6, but N may be greater than 6, or less than 6 and equal to or greater than 2. In addition, the selection unit 302 or the CPU 14 may determine other excitation levels using a linear or quadratic function that interpolates between the maximum and minimum excitation levels.

<Summary>
[Point 1]
The oscillator circuit 10 is an example of an oscillator circuit that generates a clock signal by supplying an excitation current to an oscillator to oscillate the oscillator. The CPU 14 and the oscillation control units 20 and 30 are an example of a control circuit that controls an excitation level required for the oscillator circuit to oscillate the oscillator. The ADC 17 is an example of a sample-and-hold circuit and an analog-to-digital conversion circuit. The sample-and-hold circuit samples and holds an analog input signal. The analog-to-digital conversion circuit operates by being supplied with a system clock derived from a clock signal. The analog-to-digital conversion circuit converts the voltage of the analog input signal held by the sample-and-hold circuit into digital data. The control circuit reduces the excitation level of the oscillator circuit from the first excitation level to the Nth excitation level from the start to the end of the i-th sampling of the sample-and-hold circuit. The control circuit returns the excitation level of the oscillator circuit to the first excitation level from the end of the i-th sampling of the sample-and-hold circuit to the start of the i+1-th sampling of the sample-and-hold circuit. This provides a semiconductor device that is less susceptible to coupling noise of the clock signal generated by the oscillator circuit. As a result, the accuracy of AD conversion by the analog-to-digital conversion circuit is improved.

[Points 2 and 3]
As shown in Example 1, N may be 2. As shown in Example 2, N may be an integer of 3 or more.

[Points 4 and 5]
The control circuit may be configured to change the excitation level of the oscillator circuit stepwise from the first excitation level to the Nth excitation level. For example, as illustrated in FIG. 9, the control circuit may stepwise or gradually decrease the excitation level of the oscillator circuit from the first excitation level to the jth excitation level. Furthermore, the control circuit may stepwise or gradually increase the excitation level from the jth excitation level to the Nth excitation level. This may further reduce the effect of coupling noise.

[Point 6]
The jth excitation level may be the smallest excitation level among N excitation levels from the first excitation level to the Nth excitation level. An example of j=4 is shown in FIG. 9. If the excitation level is suddenly lowered from the first excitation level to the jth excitation level, the frequency fluctuation of the reference clock CLK becomes large. However, by gradually lowering the excitation level from the first excitation level to the jth excitation level, it is possible to set the jth excitation level small, and the frequency fluctuation of the reference clock CLK also becomes small.

[Point 7]
As shown in FIG. 9, the duration of each of the N excitation levels from the second excitation level to the Nth excitation level among the N excitation levels from the first excitation level to the Nth excitation level may be constant.

[Point 8]
As shown in Fig. 4, a PLL circuit may be provided that multiplies the clock signal to generate a system clock. The control circuit may control the switching timing of the multiple drive levels based on the system clock.

[Points 9 and 10]
The time period during which the control circuit reduces the drive level below the first drive level and returns the drive level to the first drive level is longer than the time required for the clock signal to rise or fall, and may be shorter than a period of the clock signal, or may be equal to the settling time of the analog-to-digital conversion circuit.

[Point 11]
The power supply for the sample-and-hold circuit and the power supply for the oscillator circuit may be common. When such a configuration is adopted, the effect of coupling noise tends to be significant. Therefore, the first and second embodiments are particularly effective.

[Point 12]
2, the oscillator circuit may include a plurality of inverters and a feedback resistor, each of which is connected in parallel.

[Point 13]
The external input terminal IO is an example of an input terminal. The switching circuit 15 is an example of a switch circuit that switches between connecting the input terminal to a sample-and-hold circuit or connecting the input terminal to another circuit (e.g., GPIO 16). In this way, by sharing the terminal among a plurality of uses, it becomes easier to miniaturize the semiconductor device and increase the uses of the semiconductor device. In the first and second embodiments, the influence of coupling noise that sneaks into such an input terminal is reduced.

The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Therefore, the following claims are appended to disclose the scope of the invention.

1: Semiconductor device, 10: Oscillator circuit, 14, CPU, 17: ADC, 20, 30: Oscillation control unit

Claims (13)

an oscillation circuit that supplies an excitation current to an oscillator to oscillate the oscillator and generate a clock signal;
A control circuit for controlling a drive level required for the oscillator circuit to oscillate the vibrator;
a sample and hold circuit that samples and holds an analog input signal;
an analog-to-digital conversion circuit that operates by receiving a system clock derived from the clock signal generated by oscillating the oscillator and converts the voltage of the analog input signal held by the sample-and-hold circuit into digital data;
having
the control circuit is configured to reduce an excitation level required for oscillating the oscillator of the oscillation circuit from a first excitation level to an Nth excitation level between the start and end of an i-th sampling of the sample and hold circuit, and to return the excitation level of the oscillation circuit to the first excitation level between the end of the i-th sampling of the sample and hold circuit and the start of an i+1-th sampling of the sample and hold circuit. The semiconductor device according to claim 1, characterized in that N is 2. The semiconductor device according to claim 1, characterized in that N is an integer equal to or greater than 3. The semiconductor device according to claim 3, characterized in that the control circuit is configured to change the excitation level of the oscillator circuit stepwise from the first excitation level to the Nth excitation level. The semiconductor device according to claim 4, characterized in that the control circuit is configured to stepwise or gradually decrease the excitation level of the oscillator circuit from the first excitation level to the jth excitation level, and stepwise or gradually increase the excitation level from the jth excitation level to the Nth excitation level. The semiconductor device according to claim 5, characterized in that the jth excitation level is the smallest excitation level among the N excitation levels from the first excitation level to the Nth excitation level. The semiconductor device according to any one of claims 4 to 6, characterized in that the duration of each of the N excitation levels from the second excitation level to the N excitation level among the N excitation levels from the first excitation level to the N excitation level is constant. a PLL circuit for multiplying the clock signal to generate the system clock;
8. The semiconductor device according to claim 1, wherein the control circuit is configured to control timing for switching between a plurality of drive levels based on the system clock. 8. The semiconductor device according to claim 3, wherein a period from when the control circuit reduces the drive level below the first drive level to when the control circuit returns the drive level to the first drive level is longer than a time required for the clock signal to rise or fall and shorter than a period of the clock signal. The semiconductor device according to any one of claims 1 to 8, characterized in that the period from when the control circuit reduces the drive level below the first drive level to when the control circuit returns the drive level to the first drive level again is equal to the settling time of the analog-to-digital conversion circuit. The semiconductor device according to any one of claims 1 to 10, characterized in that the power supply of the sample-and-hold circuit and the power supply of the oscillator circuit are common. the oscillator circuit includes a plurality of inverters and a feedback resistor;
12. The semiconductor device according to claim 1, wherein the plurality of inverters and the feedback resistor are connected in parallel to each other. An input terminal;
13. The semiconductor device according to claim 1, further comprising a switch circuit for switching between connecting the input terminal to the sample-and-hold circuit and connecting the input terminal to another circuit.

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