KR100257396B1 - Fabrication method for semiconductor lead frame - Google Patents

Fabrication method for semiconductor lead frame Download PDF

Info

Publication number
KR100257396B1
KR100257396B1 KR1019960080133A KR19960080133A KR100257396B1 KR 100257396 B1 KR100257396 B1 KR 100257396B1 KR 1019960080133 A KR1019960080133 A KR 1019960080133A KR 19960080133 A KR19960080133 A KR 19960080133A KR 100257396 B1 KR100257396 B1 KR 100257396B1
Authority
KR
South Korea
Prior art keywords
lead
lead frame
plating layer
chip
semiconductor
Prior art date
Application number
KR1019960080133A
Other languages
Korean (ko)
Other versions
KR19980060767A (en
Inventor
서만철
노형호
Original Assignee
유무성
삼성항공산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유무성, 삼성항공산업주식회사 filed Critical 유무성
Priority to KR1019960080133A priority Critical patent/KR100257396B1/en
Publication of KR19980060767A publication Critical patent/KR19980060767A/en
Application granted granted Critical
Publication of KR100257396B1 publication Critical patent/KR100257396B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

PURPOSE: A lead frame fabricating method is to easily protect a plating surface when forming a semiconductor package and to improve a bonding state of a double-sided tape by reversing a step of forming a plating layer on an internal lead and a step of forming the double-sided insulating tape. CONSTITUTION: A semiconductor lead frame serves as a lead to connect inside and outside of a semiconductor package and as a supporter to support a chip. The lead frame consists of a pad on which the chip as a storage unit is mounted. The pad keeps the chip in a static state, and an internal lead and an external lead for connecting the chip to exterior. Fabrication of a basic shape of the lead frame is completed by a stamping process or an etching process. Then, a plating layer of metallic material such as Au or Ag is formed on top surface of tip of the internal lead. A double-sided insulating tape is bonded to a surface opposite to the internal lead corresponding to the plating layer. A non-adhesive problem between an insulating tape and a tip of the lead is prevented by a height difference between a part having the plating layer and a part having no plating layer.

Description

반도체 리드 프레임 제조방법{Fabrication method for semiconductor lead frame}Fabrication method for semiconductor lead frame

본 발명은 반도체 리드 프레임의 제조방법에 관한 것으로서, 보다 상세하게는 LOC(lead on chip) 구조의 반도체 패키지에 적용되는 리드 프레임에 있어서 내부 리드에 형성되는 도금층의 형성 과정을 개선한 리드 프레임 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor lead frame, and more particularly, to a lead frame manufacturing method of improving a process of forming a plating layer formed on an internal lead in a lead frame applied to a semiconductor package having a lead on chip (LOC) structure. It is about.

반도체 리드프레임은 기억소자인 칩과 함께 반도체 패키지를 이루는 핵심 구성요소의 하나로서, 반도체 패키지의 내부와 외부를 연결해 주는 도선(lead)의 역할과 칩을 지지해 주는 지지체의 역할을 한다.The semiconductor lead frame is one of the core components of the semiconductor package together with the chip, which is a memory device, and serves as a lead for connecting the inside and the outside of the semiconductor package and a support for supporting the chip.

이러한 반도체 리드 프레임은 기억소자인 칩을 탑재하여 정적인 상태로 유지하여 주는 패드(Pad)와, 칩을 외부회로에 연결해 주는 내부 리드(Internal lead) 및 외부 리드(External lead)를 포함하는 구조로 이루어진다. 이와 같은 구조를 가지는 리드 프레임은 통상 스템핑(Stamping) 프로세스와, 에칭(Etching) 프로세스라는 두가지 방법에 의해 제조된다. 상기 스템핑 프로세스는 순차적으로 이송되는 프레스 금형장치를 이용하여 박판의 소재를 소정 형상으로 타발하여 성형하는 것으로서, 이는 리드 프레임을 대량생산하는 경우에 주로 적용된다. 그리고, 상기 에칭 프로세스는 화학약품을 이용하여 소재의 국소 부위를 부식시킴으로써 제품을 형성하는 화학적 식각방법으로, 소량생산의 경우에 주로 적용된다.The semiconductor lead frame includes a pad that holds a chip, which is a memory device, and maintains a static state, and an internal lead and an external lead that connect the chip to an external circuit. Is done. A lead frame having such a structure is usually manufactured by two methods, a stamping process and an etching process. The stamping process is to form and mold the material of the thin plate by using a press mold apparatus which is sequentially transferred, which is mainly applied to the mass production of the lead frame. In addition, the etching process is a chemical etching method of forming a product by corroding a local part of a material using chemicals, and is mainly applied in the case of a small quantity production.

통상, 상기 두가지 제조방법 중 어느 하나의 방법에 의해 제조되는 리드 프레임은 다른 부품, 예를 들면 기억소자인 칩 등과의 조립 과정을 거쳐 반도체 패키지를 이루게 된다.In general, a lead frame manufactured by one of the above two manufacturing methods forms a semiconductor package through an assembly process with another component, for example, a chip, which is a memory device.

이러한 반도체 패키지는 최근 칩의 고집적화에 따른 소형화 및 박형화되는 추세이고, 이에 따라 리드 프레임의 설계도 나날이 변경, 개선되고 있다.Such semiconductor packages have been recently miniaturized and thinned due to high integration of chips. Accordingly, the design of lead frames is being changed and improved day by day.

통상의 리드 프레임에서 실장율을 높이는 방법중의 하나로 패드는 크게 하고 내부리드의 길이는 짧게 하는 것을 시도할 수 있는데, 내부 리드의 길이가 너무 짧아지면 몰딩후 외부 리드가 잡아 당기는 힘에 의해 패키지 밖으로 빠져 나올수 있게 되므로 내부리드를 줄이는 것은 한계가 있다.One of the methods of increasing the mounting rate in a conventional lead frame may be to increase the pad length and short the inner lead length. If the length of the inner lead becomes too short, after the molding, the external lead pulls out of the package. There is a limit to reducing internal lead as it can be pulled out.

이러한 단점을 개선한 것이 중앙의 패드와 이를 지지하는 서포트 바아를 삭제하고, 칩 쪽으로 길게 연장된 내부리드가 직접 칩을 지지하도록 한 LOC(Lead On Chip) 구조로서, 이는 도 1에 도시된 바와 같이 중앙에 형성된 공간부로 뻗은 내부 리드(11)의 저면 테두리부에 양면 접착 테이프(12)를 붙이고, 이 테이프(12)에 칩(13)의 윗면이 접착되도록 한 것이다.An improvement of this disadvantage is to remove the center pad and the support bar supporting the same, and the lead on chip (LOC) structure in which the inner lead extended to the chip directly supports the chip, as shown in FIG. The double-sided adhesive tape 12 is attached to the bottom rim of the inner lead 11 extending into the space formed at the center, and the upper surface of the chip 13 is adhered to the tape 12.

이러한 LOC 반도체 패키지의 형성 과정중 리드 프레임(10)의 내부 리드(11)의 와이어 본딩성과 다이 특성을 좋도록 하기 위해서 내부 리드(11)에 선단부에 금(Au)이나 은(Ag)과 같은 금속 소재를 도금한 도금층(14)을 형성하게 된다.In order to improve wire bonding properties and die characteristics of the internal lead 11 of the lead frame 10 during the formation of the LOC semiconductor package, a metal such as gold (Au) or silver (Ag) is formed at the tip of the internal lead 11. The plating layer 14 which plated the raw material is formed.

그런데, 이러한 도금층(14)의 형성 과정은 종래에는 도 2에 도시되어 있는 바와 같이 반도체 패키지용 리드 프레임의 제조 과정에 있어서 스템핑 프로세스 또는 에칭 프로세스에 의해 기본적인 형상의 제작이 완료된 리드 프레임(10)의 내부 리드(11)의 선단부 상면에 금(Au)이나 은(Ag)과 같은 금속 소재의 도금층(14)을 형성한 다음, 이 도금층(14)과 대응되는 내부 리드의 반대면 테두리부에 양면 절연 테이프(13)를 부착하는 단계를 순차적으로 거쳐 리드 프레임(10)의 제작을 완료하게 된다. 도면에서 부호 15는 기판 등 외부와의 접속을 위한 외부 리드이다.However, the formation process of the plating layer 14 is conventionally, as shown in FIG. 2, in the manufacturing process of the lead frame for a semiconductor package, the lead frame 10 in which the basic shape is manufactured by a stamping process or an etching process is completed. A plating layer 14 made of a metal material such as gold (Au) or silver (Ag) is formed on the top of the distal end of the inner lead 11 of the inner lead 11, and then both sides of the inner edge of the inner lead corresponding to the plating layer 14 Fabrication of the lead frame 10 is completed by sequentially attaching the insulating tape 13. In the figure, reference numeral 15 denotes an external lead for connection with the outside such as a substrate.

그러나, 상기한 바와 같은 종래의 리드 프레임 도금 과정은 내부 리드에 먼저 도금층(14)을 형성한 후, 그 반대면에 양면 절연 테이프(13)를 부착하므로 도금면의 보호가 용이하지 않고 도금층이 형성된 부분과 도금층이 형성되어 있지 않은 부분의 높이 단차로 인하여 도금층이 형성된 내부 리드 반대면의 선단부와 절연 테이프 사이에 미접착 상태가 발생하는 문제점이 있었다.However, in the conventional lead frame plating process as described above, since the plating layer 14 is first formed on the inner lead and then the double-sided insulating tape 13 is attached to the opposite side, the plating layer is not easily protected and the plating layer is formed. Due to the height difference between the portion and the portion where the plating layer is not formed, there is a problem in that an unbonded state occurs between the front end portion of the inner lead opposite surface where the plating layer is formed and the insulating tape.

따라서, 본 발명은 상기한 바와 같은 종래 기술에 의한 반도체 리드 프레임의 제조방법이 가지는 문제점을 감안하여 이를 개선코자 창출된 것으로서, 본 발명은 도금층의 보호가 용이하고 도금층이 형성된 부위의 리드 접착력을 높일 수 있는 반도체 리드 프레임의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention was created in view of the problems with the manufacturing method of the semiconductor lead frame according to the prior art as described above to improve this, the present invention is easy to protect the plating layer and increase the lead adhesion of the portion where the plating layer is formed. It is an object of the present invention to provide a method for manufacturing a semiconductor lead frame.

도 1은 일반적인 LOC구조의 리드 프레임을 나타내 보인 개략적 단면도이다.1 is a schematic cross-sectional view showing a lead frame of a general LOC structure.

도 2는 종래의 기술에 의한 반도체 리드 프레임의 단계별 제조과정을 개략적으로 나타내 보인 블럭도이다.2 is a block diagram schematically illustrating a step-by-step manufacturing process of a semiconductor lead frame according to the prior art.

도 3은 본 발명에 의한 반도체 리드 프레임의 단계별 제조과정을 개략적으로 나타내 보인 블록도이다.3 is a block diagram schematically illustrating a step-by-step manufacturing process of a semiconductor lead frame according to the present invention.

〈도면 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

10..리드 프레임 11..내부 리드10. Lead frame 11. Internal lead

12..양면 절연 테이프 13..칩12. Double-sided insulating tape 13. Chip

14..도금층 15..외부 리드14..Plated layer 15..External lead

상기한 목적을 달성하기 위하여 본 발명에 따른 반도체 리드 프레임의 제조방법은, 반도체 칩을 지지하고, 내부와 외부를 연결해 주는 도선 역할을 하는 반도체 패키지용 리드 프레임의 형상을 형성하는 제1단계와; 상기 리드 프레임의 내부 도전 리드의 선단부 배면에 칩 소자를 부착하기 위하여 절연 테이프를 부착하는 제2단계와; 상기 리드 프레임의 내부 도전 리드의 선단부 상면에 도금층을 형성하는 제3단계;를 순차 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor lead frame according to the present invention includes: a first step of forming a shape of a lead frame for a semiconductor package that serves as a conductor for supporting a semiconductor chip and connecting an inside and an outside thereof; Attaching an insulating tape to attach a chip element to a rear surface of a front end portion of the inner conductive lead of the lead frame; And a third step of forming a plating layer on an upper surface of a front end portion of the inner conductive lead of the lead frame.

이하, 첨부된 도면을 참조하여 바람직한 실시에에 따른 본 발명의 반도체 리드 프레임 제조방법을 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor lead frame according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 의한 반도체 리드 프레임의 단계별 제조과정을 개략적으로 나타내 보인 블록도이다. 도 1에 도시된 LOC 구조의 리드 프레임과 도 3에 도시된 리드 프레임의 제조 과정에 대한 블록도를 참조하면 본 발명에 의한 반도체 리드 프레임의 제조방법은, 먼저 스템핑 프로세스 또는 에칭 프로세스에 의해 기본적인 형상 제작이 완료된 리드 프레임(10)의 내부 리드(11)의 선단부 상면에 금(Au)이나 은(Ag)과 같은 금속 소재의 도금층(14)을 형성한 다음, 이 도금층(14)과 대응되는 내부 리드의 반대면에 양면 절연 테이프(12)를 부착하는 단계를 순차적으로 거쳐 리드 프레임의 제작을 완료하게 된다.3 is a block diagram schematically illustrating a step-by-step manufacturing process of a semiconductor lead frame according to the present invention. Referring to the block diagram of the lead frame of the LOC structure shown in FIG. 1 and the manufacturing process of the lead frame shown in FIG. 3, a method of manufacturing a semiconductor lead frame according to the present invention is basically performed by a stamping process or an etching process. The plating layer 14 made of a metal material such as gold (Au) or silver (Ag) is formed on the upper surface of the front end of the inner lead 11 of the lead frame 10 in which the shape is completed, and then the corresponding plating layer 14 Fabrication of the lead frame is completed by sequentially attaching the double-sided insulating tape 12 to the opposite side of the inner lead.

이와 같이 내부 리드(11)에 먼저 도금층(14)을 형성한 후, 그 반대면에 양면 절연 테이프(12)를 부착하여 리드 프레임의 제작을 완료하게 되는 본 발명에 따른 리드 프레임의 제조방법에 의하면, 반도체 패키지 형성시에 도금면의 보호가 용이하고 도금층이 형성된 부분과 도금층이 형성되어 있지 않은 부분의 높이 단차로 인하여 도금층이 형성된 반대면의 리드 선단부와 절연 테이프 사이에 미접착 상태가 발생하는 문제를 방지할 수 있다.According to the method of manufacturing a lead frame according to the present invention in which the plating layer 14 is first formed on the inner lead 11 and then the double-sided insulating tape 12 is attached to the opposite surface to complete the manufacture of the lead frame. When the semiconductor package is formed, it is easy to protect the plating surface, and there is an unbonded state between the lead end portion of the opposite surface where the plating layer is formed and the insulating tape due to the height difference between the portion where the plating layer is formed and the portion where the plating layer is not formed. Can be prevented.

이상에서 설명한 바와 같이, 본 발명에 의한 반도체 리드 프레임의 제조방법은 내부 리드에 도금층을 형성하는 단계와 양면 절연 테이프를 형성하는 단계의 순서를 바꾸어서 행하도록 그 절차를 개선함으로써 패키지 형성시에 도금면의 보호가 용이하고 칩을 부착하기 위한 양면 절연 테이프의 접착 상태를 개선할 수 있다.As described above, in the method of manufacturing a semiconductor lead frame according to the present invention, the plating surface at the time of package formation is improved by improving the procedure to change the order of forming the plating layer on the inner lead and forming the double-sided insulating tape. It is easy to protect and improve the adhesion state of the double-sided insulating tape for attaching the chip.

Claims (1)

반도체 칩을 지지하고, 내부와 외부를 연결해 주는 도선 역할을 하는 반도체 패키지용 리드 프레임의 형상을 형성하는 제1단계와;A first step of supporting a semiconductor chip and forming a shape of a lead frame for a semiconductor package, which serves as a conductor connecting the inside and the outside; 상기 리드 프레임의 내부 도전 리드의 선단부 배면에 칩 소자를 부착하기 위하여 절연 테이프를 부착하는 제2단계와;Attaching an insulating tape to attach a chip element to a rear surface of a front end portion of the inner conductive lead of the lead frame; 상기 리드 프레임의 내부 도전 리드의 선단부 상면에 도금층을 형성하는 제3단계;를 순차 포함하는 것을 특징으로 하는 반도체 패키지용 리드 프레임의 제조방법.And a third step of forming a plating layer on an upper surface of a leading end portion of the inner conductive lead of the lead frame.
KR1019960080133A 1996-12-31 1996-12-31 Fabrication method for semiconductor lead frame KR100257396B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960080133A KR100257396B1 (en) 1996-12-31 1996-12-31 Fabrication method for semiconductor lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960080133A KR100257396B1 (en) 1996-12-31 1996-12-31 Fabrication method for semiconductor lead frame

Publications (2)

Publication Number Publication Date
KR19980060767A KR19980060767A (en) 1998-10-07
KR100257396B1 true KR100257396B1 (en) 2000-05-15

Family

ID=19493455

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960080133A KR100257396B1 (en) 1996-12-31 1996-12-31 Fabrication method for semiconductor lead frame

Country Status (1)

Country Link
KR (1) KR100257396B1 (en)

Also Published As

Publication number Publication date
KR19980060767A (en) 1998-10-07

Similar Documents

Publication Publication Date Title
JP3169919B2 (en) Ball grid array type semiconductor device and method of manufacturing the same
JP2017028333A (en) Semiconductor device manufacturing method
JP3535879B2 (en) Semiconductor package assembly method
JPH11340409A (en) Lead frame and its manufacture and resin encapsulated semiconductor device and its manufacture
JPH1168006A (en) Lead frame, semiconductor device provided therewith, and manufacture of them
US6396129B1 (en) Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package
KR100257396B1 (en) Fabrication method for semiconductor lead frame
JP4243178B2 (en) Manufacturing method of semiconductor device
JP2795069B2 (en) Semiconductor device
KR0134650B1 (en) Thin film semiconductor package and the manufacture method
KR0183653B1 (en) Loc package
US20020062971A1 (en) Ultra-thin-film package
KR100215112B1 (en) Semicomductor package
JPS61241954A (en) Semiconductor device
JPS61128551A (en) Lead frame for semiconductor device
KR100229223B1 (en) Lead on chip type semiconductor package
KR20000009009A (en) Lead frame and semiconductor package using thereof
KR100481927B1 (en) Semiconductor Package and Manufacturing Method
KR100451488B1 (en) Semiconductor package having reduced size and thin thickness and fabricating method thereof
JPH11186465A (en) Semiconductor device and its manufacture
KR100234161B1 (en) Loc type semiconductor package
JPH0284744A (en) Manufacture of semiconductor device
KR100460072B1 (en) Semiconductor Package
JP2865458B2 (en) Method for manufacturing semiconductor device
KR200295664Y1 (en) Stack semiconductor package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090202

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee